Commit a9905320 authored by Tadeusz Struk's avatar Tadeusz Struk Committed by Herbert Xu

crypto: qat - Add support for RSA algorithm

Add RSA support to QAT driver.
Removed unused RNG rings.
Signed-off-by: default avatarTadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 28cfaf67
...@@ -3,11 +3,13 @@ config CRYPTO_DEV_QAT ...@@ -3,11 +3,13 @@ config CRYPTO_DEV_QAT
select CRYPTO_AEAD select CRYPTO_AEAD
select CRYPTO_AUTHENC select CRYPTO_AUTHENC
select CRYPTO_BLKCIPHER select CRYPTO_BLKCIPHER
select CRYPTO_AKCIPHER
select CRYPTO_HMAC select CRYPTO_HMAC
select CRYPTO_SHA1 select CRYPTO_SHA1
select CRYPTO_SHA256 select CRYPTO_SHA256
select CRYPTO_SHA512 select CRYPTO_SHA512
select FW_LOADER select FW_LOADER
select ASN1
config CRYPTO_DEV_QAT_DH895xCC config CRYPTO_DEV_QAT_DH895xCC
tristate "Support for Intel(R) DH895xCC" tristate "Support for Intel(R) DH895xCC"
......
$(obj)/qat_rsakey-asn1.o: $(obj)/qat_rsakey-asn1.c $(obj)/qat_rsakey-asn1.h
clean-files += qat_rsakey-asn1.c qat_rsakey-asn1.h
obj-$(CONFIG_CRYPTO_DEV_QAT) += intel_qat.o obj-$(CONFIG_CRYPTO_DEV_QAT) += intel_qat.o
intel_qat-objs := adf_cfg.o \ intel_qat-objs := adf_cfg.o \
adf_ctl_drv.o \ adf_ctl_drv.o \
...@@ -8,6 +11,8 @@ intel_qat-objs := adf_cfg.o \ ...@@ -8,6 +11,8 @@ intel_qat-objs := adf_cfg.o \
adf_transport.o \ adf_transport.o \
qat_crypto.o \ qat_crypto.o \
qat_algs.o \ qat_algs.o \
qat_rsakey-asn1.o \
qat_asym_algs.o \
qat_uclo.o \ qat_uclo.o \
qat_hal.o qat_hal.o
......
...@@ -55,7 +55,7 @@ ...@@ -55,7 +55,7 @@
#define ADF_MAJOR_VERSION 0 #define ADF_MAJOR_VERSION 0
#define ADF_MINOR_VERSION 1 #define ADF_MINOR_VERSION 1
#define ADF_BUILD_VERSION 3 #define ADF_BUILD_VERSION 4
#define ADF_DRV_VERSION __stringify(ADF_MAJOR_VERSION) "." \ #define ADF_DRV_VERSION __stringify(ADF_MAJOR_VERSION) "." \
__stringify(ADF_MINOR_VERSION) "." \ __stringify(ADF_MINOR_VERSION) "." \
__stringify(ADF_BUILD_VERSION) __stringify(ADF_BUILD_VERSION)
...@@ -94,6 +94,11 @@ struct service_hndl { ...@@ -94,6 +94,11 @@ struct service_hndl {
int admin; int admin;
}; };
static inline int get_current_node(void)
{
return cpu_data(current_thread_info()->cpu).phys_proc_id;
}
int adf_service_register(struct service_hndl *service); int adf_service_register(struct service_hndl *service);
int adf_service_unregister(struct service_hndl *service); int adf_service_unregister(struct service_hndl *service);
...@@ -141,10 +146,13 @@ int qat_crypto_unregister(void); ...@@ -141,10 +146,13 @@ int qat_crypto_unregister(void);
struct qat_crypto_instance *qat_crypto_get_instance_node(int node); struct qat_crypto_instance *qat_crypto_get_instance_node(int node);
void qat_crypto_put_instance(struct qat_crypto_instance *inst); void qat_crypto_put_instance(struct qat_crypto_instance *inst);
void qat_alg_callback(void *resp); void qat_alg_callback(void *resp);
void qat_alg_asym_callback(void *resp);
int qat_algs_init(void); int qat_algs_init(void);
void qat_algs_exit(void); void qat_algs_exit(void);
int qat_algs_register(void); int qat_algs_register(void);
int qat_algs_unregister(void); int qat_algs_unregister(void);
int qat_asym_algs_register(void);
void qat_asym_algs_unregister(void);
int qat_hal_init(struct adf_accel_dev *accel_dev); int qat_hal_init(struct adf_accel_dev *accel_dev);
void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle); void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle);
......
...@@ -257,7 +257,7 @@ int adf_dev_start(struct adf_accel_dev *accel_dev) ...@@ -257,7 +257,7 @@ int adf_dev_start(struct adf_accel_dev *accel_dev)
clear_bit(ADF_STATUS_STARTING, &accel_dev->status); clear_bit(ADF_STATUS_STARTING, &accel_dev->status);
set_bit(ADF_STATUS_STARTED, &accel_dev->status); set_bit(ADF_STATUS_STARTED, &accel_dev->status);
if (qat_algs_register()) { if (qat_algs_register() || qat_asym_algs_register()) {
dev_err(&GET_DEV(accel_dev), dev_err(&GET_DEV(accel_dev),
"Failed to register crypto algs\n"); "Failed to register crypto algs\n");
set_bit(ADF_STATUS_STARTING, &accel_dev->status); set_bit(ADF_STATUS_STARTING, &accel_dev->status);
...@@ -296,6 +296,8 @@ int adf_dev_stop(struct adf_accel_dev *accel_dev) ...@@ -296,6 +296,8 @@ int adf_dev_stop(struct adf_accel_dev *accel_dev)
dev_err(&GET_DEV(accel_dev), dev_err(&GET_DEV(accel_dev),
"Failed to unregister crypto algs\n"); "Failed to unregister crypto algs\n");
qat_asym_algs_unregister();
list_for_each(list_itr, &service_table) { list_for_each(list_itr, &service_table) {
service = list_entry(list_itr, struct service_hndl, list); service = list_entry(list_itr, struct service_hndl, list);
if (service->admin) if (service->admin)
......
...@@ -249,6 +249,8 @@ struct icp_qat_fw_comn_resp { ...@@ -249,6 +249,8 @@ struct icp_qat_fw_comn_resp {
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
......
/*
This file is provided under a dual BSD/GPLv2 license. When using or
redistributing this file, you may do so under either license.
GPL LICENSE SUMMARY
Copyright(c) 2014 Intel Corporation.
This program is free software; you can redistribute it and/or modify
it under the terms of version 2 of the GNU General Public License as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Contact Information:
qat-linux@intel.com
BSD LICENSE
Copyright(c) 2014 Intel Corporation.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ICP_QAT_FW_PKE_
#define _ICP_QAT_FW_PKE_
#include "icp_qat_fw.h"
struct icp_qat_fw_req_hdr_pke_cd_pars {
u64 content_desc_addr;
u32 content_desc_resrvd;
u32 func_id;
};
struct icp_qat_fw_req_pke_mid {
u64 opaque;
u64 src_data_addr;
u64 dest_data_addr;
};
struct icp_qat_fw_req_pke_hdr {
u8 resrvd1;
u8 resrvd2;
u8 service_type;
u8 hdr_flags;
u16 comn_req_flags;
u16 resrvd4;
struct icp_qat_fw_req_hdr_pke_cd_pars cd_pars;
};
struct icp_qat_fw_pke_request {
struct icp_qat_fw_req_pke_hdr pke_hdr;
struct icp_qat_fw_req_pke_mid pke_mid;
u8 output_param_count;
u8 input_param_count;
u16 resrvd1;
u32 resrvd2;
u64 next_req_adr;
};
struct icp_qat_fw_resp_pke_hdr {
u8 resrvd1;
u8 resrvd2;
u8 response_type;
u8 hdr_flags;
u16 comn_resp_flags;
u16 resrvd4;
};
struct icp_qat_fw_pke_resp {
struct icp_qat_fw_resp_pke_hdr pke_resp_hdr;
u64 opaque;
u64 src_data_addr;
u64 dest_data_addr;
};
#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(status_word) \
QAT_FIELD_GET(((status_word >> ICP_QAT_FW_COMN_ONE_BYTE_SHIFT) & \
ICP_QAT_FW_COMN_SINGLE_BYTE_MASK), \
QAT_COMN_RESP_PKE_STATUS_BITPOS, \
QAT_COMN_RESP_PKE_STATUS_MASK)
#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(hdr_t, val) \
QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS, \
ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
#endif
...@@ -129,11 +129,6 @@ struct qat_alg_ablkcipher_ctx { ...@@ -129,11 +129,6 @@ struct qat_alg_ablkcipher_ctx {
spinlock_t lock; /* protects qat_alg_ablkcipher_ctx struct */ spinlock_t lock; /* protects qat_alg_ablkcipher_ctx struct */
}; };
static int get_current_node(void)
{
return cpu_data(current_thread_info()->cpu).phys_proc_id;
}
static int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg) static int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg)
{ {
switch (qat_hash_alg) { switch (qat_hash_alg) {
......
This diff is collapsed.
...@@ -88,12 +88,6 @@ static int qat_crypto_free_instances(struct adf_accel_dev *accel_dev) ...@@ -88,12 +88,6 @@ static int qat_crypto_free_instances(struct adf_accel_dev *accel_dev)
if (inst->pke_rx) if (inst->pke_rx)
adf_remove_ring(inst->pke_rx); adf_remove_ring(inst->pke_rx);
if (inst->rnd_tx)
adf_remove_ring(inst->rnd_tx);
if (inst->rnd_rx)
adf_remove_ring(inst->rnd_rx);
list_del(list_ptr); list_del(list_ptr);
kfree(inst); kfree(inst);
} }
...@@ -202,11 +196,6 @@ static int qat_crypto_create_instances(struct adf_accel_dev *accel_dev) ...@@ -202,11 +196,6 @@ static int qat_crypto_create_instances(struct adf_accel_dev *accel_dev)
msg_size, key, NULL, 0, &inst->sym_tx)) msg_size, key, NULL, 0, &inst->sym_tx))
goto err; goto err;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_RND_TX, i);
if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym,
msg_size, key, NULL, 0, &inst->rnd_tx))
goto err;
msg_size = msg_size >> 1; msg_size = msg_size >> 1;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i); snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);
if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym, if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym,
...@@ -220,15 +209,9 @@ static int qat_crypto_create_instances(struct adf_accel_dev *accel_dev) ...@@ -220,15 +209,9 @@ static int qat_crypto_create_instances(struct adf_accel_dev *accel_dev)
&inst->sym_rx)) &inst->sym_rx))
goto err; goto err;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_RND_RX, i);
if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym,
msg_size, key, qat_alg_callback, 0,
&inst->rnd_rx))
goto err;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i); snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);
if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym, if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym,
msg_size, key, qat_alg_callback, 0, msg_size, key, qat_alg_asym_callback, 0,
&inst->pke_rx)) &inst->pke_rx))
goto err; goto err;
} }
......
...@@ -57,8 +57,6 @@ struct qat_crypto_instance { ...@@ -57,8 +57,6 @@ struct qat_crypto_instance {
struct adf_etr_ring_data *sym_rx; struct adf_etr_ring_data *sym_rx;
struct adf_etr_ring_data *pke_tx; struct adf_etr_ring_data *pke_tx;
struct adf_etr_ring_data *pke_rx; struct adf_etr_ring_data *pke_rx;
struct adf_etr_ring_data *rnd_tx;
struct adf_etr_ring_data *rnd_rx;
struct adf_accel_dev *accel_dev; struct adf_accel_dev *accel_dev;
struct list_head list; struct list_head list;
unsigned long state; unsigned long state;
......
RsaKey ::= SEQUENCE {
n INTEGER ({ qat_rsa_get_n }),
e INTEGER ({ qat_rsa_get_e }),
d INTEGER ({ qat_rsa_get_d })
}
...@@ -167,12 +167,6 @@ static int adf_dev_configure(struct adf_accel_dev *accel_dev) ...@@ -167,12 +167,6 @@ static int adf_dev_configure(struct adf_accel_dev *accel_dev)
key, (void *)&val, ADF_DEC)) key, (void *)&val, ADF_DEC))
goto err; goto err;
val = 4;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_RND_TX, i);
if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, (void *)&val, ADF_DEC))
goto err;
val = 8; val = 8;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i); snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);
if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
...@@ -185,12 +179,6 @@ static int adf_dev_configure(struct adf_accel_dev *accel_dev) ...@@ -185,12 +179,6 @@ static int adf_dev_configure(struct adf_accel_dev *accel_dev)
key, (void *)&val, ADF_DEC)) key, (void *)&val, ADF_DEC))
goto err; goto err;
val = 12;
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_RND_RX, i);
if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
key, (void *)&val, ADF_DEC))
goto err;
val = ADF_COALESCING_DEF_TIME; val = ADF_COALESCING_DEF_TIME;
snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i); snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);
if (adf_cfg_add_key_value_param(accel_dev, "Accelerator0", if (adf_cfg_add_key_value_param(accel_dev, "Accelerator0",
......
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