Commit a9a6e7a0 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle

MIPS: Trap exception handling fixes

2a0b24f5 broke Trap exception handling in
the standard MIPS mode.  Additionally the microMIPS-mode trap code mask is
wrong, as it's a 4-bit field.  Here's a fix.
Signed-off-by: default avatarMaciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5309/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8f657933
......@@ -897,22 +897,24 @@ asmlinkage void do_bp(struct pt_regs *regs)
asmlinkage void do_tr(struct pt_regs *regs)
{
unsigned int opcode, tcode = 0;
u32 opcode, tcode = 0;
u16 instr[2];
unsigned long epc = exception_epc(regs);
unsigned long epc = msk_isa16_mode(exception_epc(regs));
if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) ||
(__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))
if (get_isa16_mode(regs->cp0_epc)) {
if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
__get_user(instr[1], (u16 __user *)(epc + 2)))
goto out_sigsegv;
opcode = (instr[0] << 16) | instr[1];
/* Immediate versions don't provide a code. */
if (!(opcode & OPCODE)) {
if (get_isa16_mode(regs->cp0_epc))
/* microMIPS */
tcode = (opcode >> 12) & 0x1f;
else
tcode = ((opcode >> 6) & ((1 << 10) - 1));
if (!(opcode & OPCODE))
tcode = (opcode >> 12) & ((1 << 4) - 1);
} else {
if (__get_user(opcode, (u32 __user *)epc))
goto out_sigsegv;
/* Immediate versions don't provide a code. */
if (!(opcode & OPCODE))
tcode = (opcode >> 6) & ((1 << 10) - 1);
}
do_trap_or_bp(regs, tcode, "Trap");
......
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