Commit aa2aa888 authored by Bao Xiaowei's avatar Bao Xiaowei Committed by Shawn Guo

arm64: dts: fsl: Add the status property disable PCIe

Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: default avatarBao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 26a06c6e
...@@ -496,6 +496,7 @@ pcie@3400000 { ...@@ -496,6 +496,7 @@ pcie@3400000 {
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
}; };
......
...@@ -683,6 +683,7 @@ pcie@3400000 { ...@@ -683,6 +683,7 @@ pcie@3400000 {
<0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 2 &gic 0 111 0x4>,
<0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>; <0000 0 0 4 &gic 0 113 0x4>;
status = "disabled";
}; };
pcie@3500000 { pcie@3500000 {
...@@ -708,6 +709,7 @@ pcie@3500000 { ...@@ -708,6 +709,7 @@ pcie@3500000 {
<0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 2 &gic 0 121 0x4>,
<0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>; <0000 0 0 4 &gic 0 123 0x4>;
status = "disabled";
}; };
pcie@3600000 { pcie@3600000 {
...@@ -733,6 +735,7 @@ pcie@3600000 { ...@@ -733,6 +735,7 @@ pcie@3600000 {
<0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 2 &gic 0 155 0x4>,
<0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>; <0000 0 0 4 &gic 0 157 0x4>;
status = "disabled";
}; };
}; };
......
...@@ -652,6 +652,7 @@ pcie@3400000 { ...@@ -652,6 +652,7 @@ pcie@3400000 {
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3500000 { pcie@3500000 {
...@@ -677,6 +678,7 @@ pcie@3500000 { ...@@ -677,6 +678,7 @@ pcie@3500000 {
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3600000 { pcie@3600000 {
...@@ -702,6 +704,7 @@ pcie@3600000 { ...@@ -702,6 +704,7 @@ pcie@3600000 {
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
}; };
......
...@@ -533,6 +533,7 @@ pcie@3400000 { ...@@ -533,6 +533,7 @@ pcie@3400000 {
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3500000 { pcie@3500000 {
...@@ -557,6 +558,7 @@ pcie@3500000 { ...@@ -557,6 +558,7 @@ pcie@3500000 {
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
pcie@3600000 { pcie@3600000 {
...@@ -581,6 +583,7 @@ pcie@3600000 { ...@@ -581,6 +583,7 @@ pcie@3600000 {
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
}; };
cluster1_core0_watchdog: wdt@c000000 { cluster1_core0_watchdog: wdt@c000000 {
......
...@@ -648,6 +648,7 @@ pcie1: pcie@3400000 { ...@@ -648,6 +648,7 @@ pcie1: pcie@3400000 {
<0000 0 0 2 &gic 0 0 0 110 4>, <0000 0 0 2 &gic 0 0 0 110 4>,
<0000 0 0 3 &gic 0 0 0 111 4>, <0000 0 0 3 &gic 0 0 0 111 4>,
<0000 0 0 4 &gic 0 0 0 112 4>; <0000 0 0 4 &gic 0 0 0 112 4>;
status = "disabled";
}; };
pcie2: pcie@3500000 { pcie2: pcie@3500000 {
...@@ -669,6 +670,7 @@ pcie2: pcie@3500000 { ...@@ -669,6 +670,7 @@ pcie2: pcie@3500000 {
<0000 0 0 2 &gic 0 0 0 115 4>, <0000 0 0 2 &gic 0 0 0 115 4>,
<0000 0 0 3 &gic 0 0 0 116 4>, <0000 0 0 3 &gic 0 0 0 116 4>,
<0000 0 0 4 &gic 0 0 0 117 4>; <0000 0 0 4 &gic 0 0 0 117 4>;
status = "disabled";
}; };
pcie3: pcie@3600000 { pcie3: pcie@3600000 {
...@@ -690,6 +692,7 @@ pcie3: pcie@3600000 { ...@@ -690,6 +692,7 @@ pcie3: pcie@3600000 {
<0000 0 0 2 &gic 0 0 0 120 4>, <0000 0 0 2 &gic 0 0 0 120 4>,
<0000 0 0 3 &gic 0 0 0 121 4>, <0000 0 0 3 &gic 0 0 0 121 4>,
<0000 0 0 4 &gic 0 0 0 122 4>; <0000 0 0 4 &gic 0 0 0 122 4>;
status = "disabled";
}; };
pcie4: pcie@3700000 { pcie4: pcie@3700000 {
...@@ -711,6 +714,7 @@ pcie4: pcie@3700000 { ...@@ -711,6 +714,7 @@ pcie4: pcie@3700000 {
<0000 0 0 2 &gic 0 0 0 125 4>, <0000 0 0 2 &gic 0 0 0 125 4>,
<0000 0 0 3 &gic 0 0 0 126 4>, <0000 0 0 3 &gic 0 0 0 126 4>,
<0000 0 0 4 &gic 0 0 0 127 4>; <0000 0 0 4 &gic 0 0 0 127 4>;
status = "disabled";
}; };
sata0: sata@3200000 { sata0: sata@3200000 {
......
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