Commit aa2b2178 authored by Tim Harvey's avatar Tim Harvey Committed by Shawn Guo

ARM: dts: imx: ventana: add PWM nodes for Ventana boards

Ventana boards have an off-board connector with signals that can be pinmuxed
as either GPIO or PWM. This patch adds pwm device-tree nodes in the disabled
state which the bootloader can decide to enable based on bootloader config.
Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 058c0c1a
...@@ -174,6 +174,24 @@ &pcie { ...@@ -174,6 +174,24 @@ &pcie {
status = "okay"; status = "okay";
}; };
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;
...@@ -294,6 +312,24 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 ...@@ -294,6 +312,24 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>; >;
}; };
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
......
...@@ -282,6 +282,18 @@ &pcie { ...@@ -282,6 +282,18 @@ &pcie {
status = "okay"; status = "okay";
}; };
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 { &pwm4 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; pinctrl-0 = <&pinctrl_pwm4>;
...@@ -436,6 +448,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 ...@@ -436,6 +448,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>; >;
}; };
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp { pinctrl_pwm4: pwm4grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
......
...@@ -287,6 +287,18 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */ ...@@ -287,6 +287,18 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
}; };
}; };
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 { &pwm4 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; pinctrl-0 = <&pinctrl_pwm4>;
...@@ -442,6 +454,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 ...@@ -442,6 +454,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>; >;
}; };
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp { pinctrl_pwm4: pwm4grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
......
...@@ -378,6 +378,24 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */ ...@@ -378,6 +378,24 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
}; };
}; };
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 { &pwm4 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; pinctrl-0 = <&pinctrl_pwm4>;
...@@ -537,6 +555,24 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 ...@@ -537,6 +555,24 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>; >;
}; };
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp { pinctrl_pwm4: pwm4grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
......
...@@ -198,6 +198,18 @@ &pcie { ...@@ -198,6 +198,18 @@ &pcie {
status = "okay"; status = "okay";
}; };
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&ssi1 { &ssi1 {
status = "okay"; status = "okay";
}; };
...@@ -290,6 +302,18 @@ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ ...@@ -290,6 +302,18 @@ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
>; >;
}; };
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
......
...@@ -164,6 +164,18 @@ &pcie { ...@@ -164,6 +164,18 @@ &pcie {
status = "okay"; status = "okay";
}; };
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&uart2 { &uart2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>; pinctrl-0 = <&pinctrl_uart2>;
...@@ -242,6 +254,18 @@ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 ...@@ -242,6 +254,18 @@ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>; >;
}; };
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
......
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