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Commit aa32a955 authored by David Daney's avatar David Daney Committed by Ralf Baechle
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MIPS: Octeon: Update register definitions for CN63XX chips 

The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b93b2abc
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Showing with 4212 additions and 2161 deletions
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
View file @ aa32a955
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com * Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK * This file is part of the OCTEON SDK
* *
* Copyright (c) 2003-2008 Cavium Networks * Copyright (c) 2003-2010 Cavium Networks
* *
* This file is free software; you can redistribute it and/or modify * This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as * it under the terms of the GNU General Public License, Version 2, as
...@@ -28,29 +28,22 @@ ...@@ -28,29 +28,22 @@
#ifndef __CVMX_GPIO_DEFS_H__ #ifndef __CVMX_GPIO_DEFS_H__
#define __CVMX_GPIO_DEFS_H__ #define __CVMX_GPIO_DEFS_H__
#define CVMX_GPIO_BIT_CFGX(offset) \ #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8)) #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
#define CVMX_GPIO_BOOT_ENA \ #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
CVMX_ADD_IO_SEG(0x00010700000008A8ull) #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
#define CVMX_GPIO_CLK_GENX(offset) \ #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8)) #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
#define CVMX_GPIO_DBG_ENA \ #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
CVMX_ADD_IO_SEG(0x00010700000008A0ull) #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
#define CVMX_GPIO_INT_CLR \ #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
CVMX_ADD_IO_SEG(0x0001070000000898ull) #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
#define CVMX_GPIO_RX_DAT \
CVMX_ADD_IO_SEG(0x0001070000000880ull)
#define CVMX_GPIO_TX_CLR \
CVMX_ADD_IO_SEG(0x0001070000000890ull)
#define CVMX_GPIO_TX_SET \
CVMX_ADD_IO_SEG(0x0001070000000888ull)
#define CVMX_GPIO_XBIT_CFGX(offset) \
CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
union cvmx_gpio_bit_cfgx { union cvmx_gpio_bit_cfgx {
uint64_t u64; uint64_t u64;
struct cvmx_gpio_bit_cfgx_s { struct cvmx_gpio_bit_cfgx_s {
uint64_t reserved_15_63:49; uint64_t reserved_17_63:47;
uint64_t synce_sel:2;
uint64_t clk_gen:1; uint64_t clk_gen:1;
uint64_t clk_sel:2; uint64_t clk_sel:2;
uint64_t fil_sel:4; uint64_t fil_sel:4;
...@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx { ...@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx {
struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
struct cvmx_gpio_bit_cfgx_s cn52xx; struct cvmx_gpio_bit_cfgx_cn52xx {
struct cvmx_gpio_bit_cfgx_s cn52xxp1; uint64_t reserved_15_63:49;
struct cvmx_gpio_bit_cfgx_s cn56xx; uint64_t clk_gen:1;
struct cvmx_gpio_bit_cfgx_s cn56xxp1; uint64_t clk_sel:2;
uint64_t fil_sel:4;
uint64_t fil_cnt:4;
uint64_t int_type:1;
uint64_t int_en:1;
uint64_t rx_xor:1;
uint64_t tx_oe:1;
} cn52xx;
struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
struct cvmx_gpio_bit_cfgx_s cn63xx;
struct cvmx_gpio_bit_cfgx_s cn63xxp1;
}; };
union cvmx_gpio_boot_ena { union cvmx_gpio_boot_ena {
...@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx { ...@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx {
struct cvmx_gpio_clk_genx_s cn52xxp1; struct cvmx_gpio_clk_genx_s cn52xxp1;
struct cvmx_gpio_clk_genx_s cn56xx; struct cvmx_gpio_clk_genx_s cn56xx;
struct cvmx_gpio_clk_genx_s cn56xxp1; struct cvmx_gpio_clk_genx_s cn56xxp1;
struct cvmx_gpio_clk_genx_s cn63xx;
struct cvmx_gpio_clk_genx_s cn63xxp1;
};
union cvmx_gpio_clk_qlmx {
uint64_t u64;
struct cvmx_gpio_clk_qlmx_s {
uint64_t reserved_3_63:61;
uint64_t div:1;
uint64_t lane_sel:2;
} s;
struct cvmx_gpio_clk_qlmx_s cn63xx;
struct cvmx_gpio_clk_qlmx_s cn63xxp1;
}; };
union cvmx_gpio_dbg_ena { union cvmx_gpio_dbg_ena {
...@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr { ...@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr {
struct cvmx_gpio_int_clr_s cn56xxp1; struct cvmx_gpio_int_clr_s cn56xxp1;
struct cvmx_gpio_int_clr_s cn58xx; struct cvmx_gpio_int_clr_s cn58xx;
struct cvmx_gpio_int_clr_s cn58xxp1; struct cvmx_gpio_int_clr_s cn58xxp1;
struct cvmx_gpio_int_clr_s cn63xx;
struct cvmx_gpio_int_clr_s cn63xxp1;
}; };
union cvmx_gpio_rx_dat { union cvmx_gpio_rx_dat {
...@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat { ...@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat {
struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
struct cvmx_gpio_rx_dat_cn38xx cn58xx; struct cvmx_gpio_rx_dat_cn38xx cn58xx;
struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
struct cvmx_gpio_rx_dat_cn38xx cn63xx;
struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
}; };
union cvmx_gpio_tx_clr { union cvmx_gpio_tx_clr {
...@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr { ...@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr {
struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
struct cvmx_gpio_tx_clr_cn38xx cn58xx; struct cvmx_gpio_tx_clr_cn38xx cn58xx;
struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
struct cvmx_gpio_tx_clr_cn38xx cn63xx;
struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
}; };
union cvmx_gpio_tx_set { union cvmx_gpio_tx_set {
...@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set { ...@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set {
struct cvmx_gpio_tx_set_cn38xx cn56xxp1; struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
struct cvmx_gpio_tx_set_cn38xx cn58xx; struct cvmx_gpio_tx_set_cn38xx cn58xx;
struct cvmx_gpio_tx_set_cn38xx cn58xxp1; struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
struct cvmx_gpio_tx_set_cn38xx cn63xx;
struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
}; };
union cvmx_gpio_xbit_cfgx { union cvmx_gpio_xbit_cfgx {
......
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
View file @ aa32a955
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com * Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK * This file is part of the OCTEON SDK
* *
* Copyright (c) 2003-2008 Cavium Networks * Copyright (c) 2003-2010 Cavium Networks
* *
* This file is free software; you can redistribute it and/or modify * This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as * it under the terms of the GNU General Public License, Version 2, as
...@@ -28,30 +28,18 @@ ...@@ -28,30 +28,18 @@
#ifndef __CVMX_L2D_DEFS_H__ #ifndef __CVMX_L2D_DEFS_H__
#define __CVMX_L2D_DEFS_H__ #define __CVMX_L2D_DEFS_H__
#define CVMX_L2D_BST0 \ #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
CVMX_ADD_IO_SEG(0x0001180080000780ull) #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
#define CVMX_L2D_BST1 \ #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
CVMX_ADD_IO_SEG(0x0001180080000788ull) #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
#define CVMX_L2D_BST2 \ #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
CVMX_ADD_IO_SEG(0x0001180080000790ull) #define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
#define CVMX_L2D_BST3 \ #define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
CVMX_ADD_IO_SEG(0x0001180080000798ull) #define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
#define CVMX_L2D_ERR \ #define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
CVMX_ADD_IO_SEG(0x0001180080000010ull) #define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
#define CVMX_L2D_FADR \ #define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
CVMX_ADD_IO_SEG(0x0001180080000018ull) #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
#define CVMX_L2D_FSYN0 \
CVMX_ADD_IO_SEG(0x0001180080000020ull)
#define CVMX_L2D_FSYN1 \
CVMX_ADD_IO_SEG(0x0001180080000028ull)
#define CVMX_L2D_FUS0 \
CVMX_ADD_IO_SEG(0x00011800800007A0ull)
#define CVMX_L2D_FUS1 \
CVMX_ADD_IO_SEG(0x00011800800007A8ull)
#define CVMX_L2D_FUS2 \
CVMX_ADD_IO_SEG(0x00011800800007B0ull)
#define CVMX_L2D_FUS3 \
CVMX_ADD_IO_SEG(0x00011800800007B8ull)
union cvmx_l2d_bst0 { union cvmx_l2d_bst0 {
uint64_t u64; uint64_t u64;
......
arch/mips/include/asm/octeon/cvmx-l2t-defs.h
View file @ aa32a955
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com * Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK * This file is part of the OCTEON SDK
* *
* Copyright (c) 2003-2008 Cavium Networks * Copyright (c) 2003-2010 Cavium Networks
* *
* This file is free software; you can redistribute it and/or modify * This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as * it under the terms of the GNU General Public License, Version 2, as
...@@ -28,8 +28,7 @@ ...@@ -28,8 +28,7 @@
#ifndef __CVMX_L2T_DEFS_H__ #ifndef __CVMX_L2T_DEFS_H__
#define __CVMX_L2T_DEFS_H__ #define __CVMX_L2T_DEFS_H__
#define CVMX_L2T_ERR \ #define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
CVMX_ADD_IO_SEG(0x0001180080000008ull)
union cvmx_l2t_err { union cvmx_l2t_err {
uint64_t u64; uint64_t u64;
......
arch/mips/include/asm/octeon/cvmx-led-defs.h
View file @ aa32a955
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com * Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK * This file is part of the OCTEON SDK
* *
* Copyright (c) 2003-2008 Cavium Networks * Copyright (c) 2003-2010 Cavium Networks
* *
* This file is free software; you can redistribute it and/or modify * This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as * it under the terms of the GNU General Public License, Version 2, as
...@@ -28,32 +28,19 @@ ...@@ -28,32 +28,19 @@
#ifndef __CVMX_LED_DEFS_H__ #ifndef __CVMX_LED_DEFS_H__
#define __CVMX_LED_DEFS_H__ #define __CVMX_LED_DEFS_H__
#define CVMX_LED_BLINK \ #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
CVMX_ADD_IO_SEG(0x0001180000001A48ull) #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
#define CVMX_LED_CLK_PHASE \ #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
CVMX_ADD_IO_SEG(0x0001180000001A08ull) #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
#define CVMX_LED_CYLON \ #define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
CVMX_ADD_IO_SEG(0x0001180000001AF8ull) #define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
#define CVMX_LED_DBG \ #define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
CVMX_ADD_IO_SEG(0x0001180000001A18ull) #define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
#define CVMX_LED_EN \ #define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
CVMX_ADD_IO_SEG(0x0001180000001A00ull) #define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
#define CVMX_LED_POLARITY \ #define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
CVMX_ADD_IO_SEG(0x0001180000001A50ull) #define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
#define CVMX_LED_PRT \ #define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
CVMX_ADD_IO_SEG(0x0001180000001A10ull)
#define CVMX_LED_PRT_FMT \
CVMX_ADD_IO_SEG(0x0001180000001A30ull)
#define CVMX_LED_PRT_STATUSX(offset) \
CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
#define CVMX_LED_UDD_CNTX(offset) \
CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
#define CVMX_LED_UDD_DATX(offset) \
CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
#define CVMX_LED_UDD_DAT_CLRX(offset) \
CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
#define CVMX_LED_UDD_DAT_SETX(offset) \
CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
union cvmx_led_blink { union cvmx_led_blink {
uint64_t u64; uint64_t u64;
......
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
View file @ aa32a955
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com * Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK * This file is part of the OCTEON SDK
* *
* Copyright (c) 2003-2008 Cavium Networks * Copyright (c) 2003-2010 Cavium Networks
* *
* This file is free software; you can redistribute it and/or modify * This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as * it under the terms of the GNU General Public License, Version 2, as
...@@ -28,38 +28,22 @@ ...@@ -28,38 +28,22 @@
#ifndef __CVMX_PESCX_DEFS_H__ #ifndef __CVMX_PESCX_DEFS_H__
#define __CVMX_PESCX_DEFS_H__ #define __CVMX_PESCX_DEFS_H__
#define CVMX_PESCX_BIST_STATUS(block_id) \ #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_BIST_STATUS2(block_id) \ #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_CFG_RD(block_id) \ #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_CFG_WR(block_id) \ #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_CPL_LUT_VALID(block_id) \ #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_CTL_STATUS(block_id) \ #define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_CTL_STATUS2(block_id) \ #define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
#define CVMX_PESCX_DBG_INFO(block_id) \ #define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull)) #define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_PESCX_DBG_INFO_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_DIAG_STATUS(block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_P2N_BAR0_START(block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_P2N_BAR1_START(block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_P2N_BAR2_START(block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PESCX_TLP_CREDITS(block_id) \
CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
union cvmx_pescx_bist_status { union cvmx_pescx_bist_status {
uint64_t u64; uint64_t u64;
......
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