Commit aa685acd authored by Nikita Danilov's avatar Nikita Danilov Committed by David S. Miller

atlatnic: enable Nbase-t speeds with base-t

When 2.5G is advertised, N-Base should be advertised against the T-base
caps. N5G is out of use in baseline code and driver should treat both 5G
and N5G (and also 2.5G and N2.5G) equally from user perspective.

Fixes: 5cfd54d7 ("net: atlantic: minimal A2 fw_ops")
Signed-off-by: default avatarNikita Danilov <ndanilov@aquantia.com>
Signed-off-by: default avatarSudarsana Reddy Kalluru <skalluru@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent aa1dcb56
...@@ -53,20 +53,19 @@ ...@@ -53,20 +53,19 @@
#define AQ_NIC_RATE_10G BIT(0) #define AQ_NIC_RATE_10G BIT(0)
#define AQ_NIC_RATE_5G BIT(1) #define AQ_NIC_RATE_5G BIT(1)
#define AQ_NIC_RATE_5GSR BIT(2) #define AQ_NIC_RATE_2G5 BIT(2)
#define AQ_NIC_RATE_2G5 BIT(3) #define AQ_NIC_RATE_1G BIT(3)
#define AQ_NIC_RATE_1G BIT(4) #define AQ_NIC_RATE_100M BIT(4)
#define AQ_NIC_RATE_100M BIT(5) #define AQ_NIC_RATE_10M BIT(5)
#define AQ_NIC_RATE_10M BIT(6) #define AQ_NIC_RATE_1G_HALF BIT(6)
#define AQ_NIC_RATE_1G_HALF BIT(7) #define AQ_NIC_RATE_100M_HALF BIT(7)
#define AQ_NIC_RATE_100M_HALF BIT(8) #define AQ_NIC_RATE_10M_HALF BIT(8)
#define AQ_NIC_RATE_10M_HALF BIT(9)
#define AQ_NIC_RATE_EEE_10G BIT(10) #define AQ_NIC_RATE_EEE_10G BIT(9)
#define AQ_NIC_RATE_EEE_5G BIT(11) #define AQ_NIC_RATE_EEE_5G BIT(10)
#define AQ_NIC_RATE_EEE_2G5 BIT(12) #define AQ_NIC_RATE_EEE_2G5 BIT(11)
#define AQ_NIC_RATE_EEE_1G BIT(13) #define AQ_NIC_RATE_EEE_1G BIT(12)
#define AQ_NIC_RATE_EEE_100M BIT(14) #define AQ_NIC_RATE_EEE_100M BIT(13)
#define AQ_NIC_RATE_EEE_MSK (AQ_NIC_RATE_EEE_10G |\ #define AQ_NIC_RATE_EEE_MSK (AQ_NIC_RATE_EEE_10G |\
AQ_NIC_RATE_EEE_5G |\ AQ_NIC_RATE_EEE_5G |\
AQ_NIC_RATE_EEE_2G5 |\ AQ_NIC_RATE_EEE_2G5 |\
......
...@@ -132,9 +132,6 @@ static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed) ...@@ -132,9 +132,6 @@ static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
if (speed & AQ_NIC_RATE_5G) if (speed & AQ_NIC_RATE_5G)
rate |= FW2X_RATE_5G; rate |= FW2X_RATE_5G;
if (speed & AQ_NIC_RATE_5GSR)
rate |= FW2X_RATE_5G;
if (speed & AQ_NIC_RATE_2G5) if (speed & AQ_NIC_RATE_2G5)
rate |= FW2X_RATE_2G5; rate |= FW2X_RATE_2G5;
......
...@@ -154,7 +154,7 @@ static void a2_link_speed_mask2fw(u32 speed, ...@@ -154,7 +154,7 @@ static void a2_link_speed_mask2fw(u32 speed,
{ {
link_options->rate_10G = !!(speed & AQ_NIC_RATE_10G); link_options->rate_10G = !!(speed & AQ_NIC_RATE_10G);
link_options->rate_5G = !!(speed & AQ_NIC_RATE_5G); link_options->rate_5G = !!(speed & AQ_NIC_RATE_5G);
link_options->rate_N5G = !!(speed & AQ_NIC_RATE_5GSR); link_options->rate_N5G = link_options->rate_5G;
link_options->rate_2P5G = !!(speed & AQ_NIC_RATE_2G5); link_options->rate_2P5G = !!(speed & AQ_NIC_RATE_2G5);
link_options->rate_N2P5G = link_options->rate_2P5G; link_options->rate_N2P5G = link_options->rate_2P5G;
link_options->rate_1G = !!(speed & AQ_NIC_RATE_1G); link_options->rate_1G = !!(speed & AQ_NIC_RATE_1G);
...@@ -192,8 +192,6 @@ static u32 a2_fw_lkp_to_mask(struct lkp_link_caps_s *lkp_link_caps) ...@@ -192,8 +192,6 @@ static u32 a2_fw_lkp_to_mask(struct lkp_link_caps_s *lkp_link_caps)
rate |= AQ_NIC_RATE_10G; rate |= AQ_NIC_RATE_10G;
if (lkp_link_caps->rate_5G) if (lkp_link_caps->rate_5G)
rate |= AQ_NIC_RATE_5G; rate |= AQ_NIC_RATE_5G;
if (lkp_link_caps->rate_N5G)
rate |= AQ_NIC_RATE_5GSR;
if (lkp_link_caps->rate_2P5G) if (lkp_link_caps->rate_2P5G)
rate |= AQ_NIC_RATE_2G5; rate |= AQ_NIC_RATE_2G5;
if (lkp_link_caps->rate_1G) if (lkp_link_caps->rate_1G)
......
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