Commit aa83fa5b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov

drm/msm/dpu: drop DPU_HW_SUBBLK_INFO macro

As the subblock info is now mostly gone, inline and drop the macro
DPU_HW_SUBBLK_INFO.
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/570106/
Link: https://lore.kernel.org/r/20231201234234.2065610-8-dmitry.baryshkov@linaro.org
parent 0fd20541
...@@ -248,49 +248,51 @@ enum { ...@@ -248,49 +248,51 @@ enum {
u32 len; \ u32 len; \
unsigned long features unsigned long features
/**
* MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU
* @name: string name for debug purposes
* @base: offset of this sub-block relative to the block
* offset
* @len register block length of this sub-block
*/
#define DPU_HW_SUBBLK_INFO \
char name[DPU_HW_BLK_NAME_LEN]; \
u32 base; \
u32 len
/** /**
* struct dpu_scaler_blk: Scaler information * struct dpu_scaler_blk: Scaler information
* @info: HW register and features supported by this sub-blk * @name: string name for debug purposes
* @base: offset of this sub-block relative to the block offset
* @len: register block length of this sub-block
* @version: qseed block revision, on QSEED3+ platforms this is the value of * @version: qseed block revision, on QSEED3+ platforms this is the value of
* scaler_blk.base + QSEED3_HW_VERSION registers. * scaler_blk.base + QSEED3_HW_VERSION registers.
*/ */
struct dpu_scaler_blk { struct dpu_scaler_blk {
DPU_HW_SUBBLK_INFO; char name[DPU_HW_BLK_NAME_LEN];
u32 base;
u32 len;
u32 version; u32 version;
}; };
struct dpu_csc_blk { struct dpu_csc_blk {
DPU_HW_SUBBLK_INFO; char name[DPU_HW_BLK_NAME_LEN];
u32 base;
u32 len;
}; };
/** /**
* struct dpu_pp_blk : Pixel processing sub-blk information * struct dpu_pp_blk : Pixel processing sub-blk information
* @info: HW register and features supported by this sub-blk * @name: string name for debug purposes
* @base: offset of this sub-block relative to the block offset
* @len: register block length of this sub-block
* @version: HW Algorithm version * @version: HW Algorithm version
*/ */
struct dpu_pp_blk { struct dpu_pp_blk {
DPU_HW_SUBBLK_INFO; char name[DPU_HW_BLK_NAME_LEN];
u32 base;
u32 len;
u32 version; u32 version;
}; };
/** /**
* struct dpu_dsc_blk - DSC Encoder sub-blk information * struct dpu_dsc_blk - DSC Encoder sub-blk information
* @info: HW register and features supported by this sub-blk * @name: string name for debug purposes
* @base: offset of this sub-block relative to the block offset
* @len: register block length of this sub-block
*/ */
struct dpu_dsc_blk { struct dpu_dsc_blk {
DPU_HW_SUBBLK_INFO; char name[DPU_HW_BLK_NAME_LEN];
u32 base;
u32 len;
}; };
/** /**
......
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