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Commit ab3ff12a authored by Simon Horman's avatar Simon Horman
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Merge branch 'soc' into boards 

Conflicts:
	arch/arm/configs/marzen_defconfig
parents 631a7b5d 29446286
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arch/arm/boot/dts/sh7377.dtsi deleted 100644 → 0
View file @ 631a7b5d
/*
* Device Tree Source for the sh7377 SoC
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,sh7377";
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
};
arch/arm/configs/armadillo800eva_defconfig
View file @ ab3ff12a
......@@ -7,6 +7,7 @@ CONFIG_LOG_BUF_SHIFT=16
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
......
arch/arm/mach-shmobile/Kconfig
View file @ ab3ff12a
......@@ -2,18 +2,6 @@ if ARCH_SHMOBILE
comment "SH-Mobile System Type"
config ARCH_SH7367
bool "SH-Mobile G3 (SH7367)"
select ARCH_WANT_OPTIONAL_GPIOLIB
select CPU_V6
select SH_CLK_CPG
config ARCH_SH7377
bool "SH-Mobile G4 (SH7377)"
select ARCH_WANT_OPTIONAL_GPIOLIB
select CPU_V7
select SH_CLK_CPG
config ARCH_SH7372
bool "SH-Mobile AP4 (SH7372)"
select ARCH_WANT_OPTIONAL_GPIOLIB
......
arch/arm/mach-shmobile/Makefile
View file @ ab3ff12a
......@@ -6,8 +6,6 @@
obj-y := timer.o console.o clock.o
# CPU objects
obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
......@@ -23,16 +21,12 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
# Pinmux setup
pfc-y :=
pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
# IRQ objects
obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
......
arch/arm/mach-shmobile/board-ap4evb.c
View file @ ab3ff12a
......@@ -728,7 +728,7 @@ static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
{
struct clk *fsib_clk;
struct clk *fdiv_clk = &sh7372_fsidivb_clk;
struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
long fsib_rate = 0;
long fdiv_rate = 0;
int ackmd_bpfmd;
......
arch/arm/mach-shmobile/board-mackerel.c
View file @ ab3ff12a
......@@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
static int fsi_b_set_rate(struct device *dev, int rate, int enable)
{
struct clk *fsib_clk;
struct clk *fdiv_clk = &sh7372_fsidivb_clk;
struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
long fsib_rate = 0;
long fdiv_rate = 0;
int ackmd_bpfmd;
......
arch/arm/mach-shmobile/clock-r8a7740.c
View file @ ab3ff12a
......@@ -65,6 +65,9 @@
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
#define FSIDIVA IOMEM(0xFE1F8000)
#define FSIDIVB IOMEM(0xFE1F8008)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk extalr_clk = {
.rate = 32768,
......@@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = {
};
/* USB clock */
/*
* USBCKCR is controlling usb24 clock
* bit[7] : parent clock
* bit[6] : clock divide rate
* And this bit[7] is used as a "usb24s" from other devices.
* (Video clock / Sub clock / SPU clock)
* You can controll this clock as a below.
*
* struct clk *usb24 = clk_get(dev, "usb24");
* struct clk *usb24s = clk_get(NULL, "usb24s");
* struct clk *system = clk_get(NULL, "system_clk");
* int rate = clk_get_rate(system);
*
* clk_set_parent(usb24s, system); // for bit[7]
* clk_set_rate(usb24, rate / 2); // for bit[6]
*/
static struct clk *usb24s_parents[] = {
[0] = &system_clk,
[1] = &extal2_clk
......@@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = {
&hdmi2_clk,
};
/* FSI DIV */
enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
static struct clk fsidivs[] = {
[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
};
/* MSTP */
enum {
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
......@@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
};
void __init r8a7740_clock_init(u8 md_ck)
......@@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck)
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
if (!ret)
ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
......
arch/arm/mach-shmobile/clock-r8a7779.c
View file @ ab3ff12a
......@@ -87,8 +87,11 @@ static struct clk div4_clks[DIV4_NR] = {
};
enum { MSTP323, MSTP322, MSTP321, MSTP320,
MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
MSTP101, MSTP100,
MSTP030,
MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
MSTP016, MSTP015, MSTP014,
MSTP007,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
......@@ -96,6 +99,12 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */
[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
......@@ -105,6 +114,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */
};
static unsigned long mul4_recalc(struct clk *clk)
......@@ -146,14 +156,25 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
......
arch/arm/mach-shmobile/clock-sh7367.c deleted 100644 → 0
View file @ 631a7b5d
/*
* SH7367 clock framework support
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/common.h>
/* SH7367 registers */
#define RTFRQCR IOMEM(0xe6150000)
#define SYFRQCR IOMEM(0xe6150004)
#define CMFRQCR IOMEM(0xe61500E0)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000C)
#define VCLKCR3 IOMEM(0xe615001C)
#define SCLKACR IOMEM(0xe6150010)
#define SCLKBCR IOMEM(0xe6150014)
#define SUBUSBCKCR IOMEM(0xe6158080)
#define SPUCKCR IOMEM(0xe6150084)
#define MSUCKCR IOMEM(0xe6150088)
#define MVI3CKCR IOMEM(0xe6150090)
#define VOUCKCR IOMEM(0xe6150094)
#define MFCK1CR IOMEM(0xe6150098)
#define MFCK2CR IOMEM(0xe615009C)
#define PLLC1CR IOMEM(0xe6150028)
#define PLLC2CR IOMEM(0xe615002C)
#define RTMSTPCR0 IOMEM(0xe6158030)
#define RTMSTPCR2 IOMEM(0xe6158038)
#define SYMSTPCR0 IOMEM(0xe6158040)
#define SYMSTPCR2 IOMEM(0xe6158048)
#define CMMSTPCR0 IOMEM(0xe615804c)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {
.rate = 32768,
};
/*
* 26MHz default rate for the EXTALB1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7367_extalb1_clk = {
.rate = 26666666,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7367_extal2_clk = {
.rate = 48000000,
};
/* A fixed divide-by-2 block */
static unsigned long div2_recalc(struct clk *clk)
{
return clk->parent->rate / 2;
}
static struct sh_clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
/* Divide extalb1 by two */
static struct clk extalb1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7367_extalb1_clk,
};
/* Divide extal2 by two */
static struct clk extal2_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7367_extal2_clk,
};
/* PLLC1 */
static unsigned long pllc1_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC1CR) & (1 << 14))
mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct sh_clk_ops pllc1_clk_ops = {
.recalc = pllc1_recalc,
};
static struct clk pllc1_clk = {
.ops = &pllc1_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalb1_div2_clk,
};
/* Divide PLLC1 by two */
static struct clk pllc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pllc1_clk,
};
/* PLLC2 */
static unsigned long pllc2_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC2CR) & (1 << 31))
mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct sh_clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
};
static struct clk pllc2_clk = {
.ops = &pllc2_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalb1_div2_clk,
};
static struct clk *main_clks[] = {
&r_clk,
&sh7367_extalb1_clk,
&sh7367_extal2_clk,
&extalb1_div2_clk,
&extal2_div2_clk,
&pllc1_clk,
&pllc1_div2_clk,
&pllc2_clk,
};
static void div4_kick(struct clk *clk)
{
unsigned long value;
/* set KICK bit in SYFRQCR to update hardware setting */
value = __raw_readl(SYFRQCR);
value |= (1 << 31);
__raw_writel(value, SYFRQCR);
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48, 0, 72, 0, 0 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
[DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
[DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
[DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
[DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
[DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
[DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
[DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
[DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
};
enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
DIV6_MVI3, DIV6_MF1, DIV6_MF2,
DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
DIV6_NR };
static struct clk div6_clks[DIV6_NR] = {
[DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
[DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
[DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
[DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
[DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
[DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
[DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
};
enum { RTMSTP001,
RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
CMMSTP003,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[MSTP_NR] = {
[RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
[RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
[RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
[RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
[RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
[RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
[RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
[RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
[RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
[RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
[SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
[SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
[SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
[SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
[SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
[SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
[SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
[SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
[SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
[SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
[SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
[SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
[SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
[SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
[SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
[SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
[SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
[CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
/* DIV6 clocks */
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
};
void __init sh7367_clock_init(void)
{
int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
shmobile_clk_init();
else
panic("failed to setup sh7367 clocks\n");
}
arch/arm/mach-shmobile/clock-sh7372.c
View file @ ab3ff12a
......@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
};
/* FSI DIV */
static unsigned long fsidiv_recalc(struct clk *clk)
{
unsigned long value;
value = __raw_readl(clk->mapping->base);
value >>= 16;
if (value < 2)
return 0;
return clk->parent->rate / value;
}
static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_div_range_round(clk, 2, 0xffff, rate);
}
static void fsidiv_disable(struct clk *clk)
{
__raw_writel(0, clk->mapping->base);
}
static int fsidiv_enable(struct clk *clk)
{
unsigned long value;
value = __raw_readl(clk->mapping->base) >> 16;
if (value < 2)
return -EIO;
__raw_writel((value << 16) | 0x3, clk->mapping->base);
return 0;
}
static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
{
int idx;
idx = (clk->parent->rate / rate) & 0xffff;
if (idx < 2)
return -EINVAL;
__raw_writel(idx << 16, clk->mapping->base);
return 0;
}
static struct sh_clk_ops fsidiv_clk_ops = {
.recalc = fsidiv_recalc,
.round_rate = fsidiv_round_rate,
.set_rate = fsidiv_set_rate,
.enable = fsidiv_enable,
.disable = fsidiv_disable,
};
static struct clk_mapping fsidiva_clk_mapping = {
.phys = FSIDIVA,
.len = 8,
};
struct clk sh7372_fsidiva_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
.mapping = &fsidiva_clk_mapping,
};
enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
static struct clk_mapping fsidivb_clk_mapping = {
.phys = FSIDIVB,
.len = 8,
};
struct clk sh7372_fsidivb_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
.mapping = &fsidivb_clk_mapping,
};
static struct clk *late_main_clks[] = {
&sh7372_fsidiva_clk,
&sh7372_fsidivb_clk,
static struct clk fsidivs[] = {
[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
};
enum { MSTP001, MSTP000,
......@@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
......@@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
CLKDEV_ICK_ID("xcka", "sh_fsi2", &sh7372_fsiack_clk),
CLKDEV_ICK_ID("xckb", "sh_fsi2", &sh7372_fsibck_clk),
};
void __init sh7372_clock_init(void)
......@@ -706,8 +636,8 @@ void __init sh7372_clock_init(void)
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
if (!ret)
ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
......
arch/arm/mach-shmobile/clock-sh7377.c deleted 100644 → 0
View file @ 631a7b5d
/*
* SH7377 clock framework support
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/common.h>
/* SH7377 registers */
#define RTFRQCR IOMEM(0xe6150000)
#define SYFRQCR IOMEM(0xe6150004)
#define CMFRQCR IOMEM(0xe61500E0)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000C)
#define VCLKCR3 IOMEM(0xe615001C)
#define FMSICKCR IOMEM(0xe6150010)
#define FMSOCKCR IOMEM(0xe6150014)
#define FSICKCR IOMEM(0xe6150018)
#define PLLC1CR IOMEM(0xe6150028)
#define PLLC2CR IOMEM(0xe615002C)
#define SUBUSBCKCR IOMEM(0xe6150080)
#define SPUCKCR IOMEM(0xe6150084)
#define MSUCKCR IOMEM(0xe6150088)
#define MVI3CKCR IOMEM(0xe6150090)
#define HDMICKCR IOMEM(0xe6150094)
#define MFCK1CR IOMEM(0xe6150098)
#define MFCK2CR IOMEM(0xe615009C)
#define DSITCKCR IOMEM(0xe6150060)
#define DSIPCKCR IOMEM(0xe6150064)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013C)
#define SMSTPCR4 IOMEM(0xe6150140)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {
.rate = 32768,
};
/*
* 26MHz default rate for the EXTALC1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7377_extalc1_clk = {
.rate = 26666666,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh7377_extal2_clk = {
.rate = 48000000,
};
/* A fixed divide-by-2 block */
static unsigned long div2_recalc(struct clk *clk)
{
return clk->parent->rate / 2;
}
static struct sh_clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
/* Divide extalc1 by two */
static struct clk extalc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7377_extalc1_clk,
};
/* Divide extal2 by two */
static struct clk extal2_div2_clk = {
.ops = &div2_clk_ops,
.parent = &sh7377_extal2_clk,
};
/* Divide extal2 by four */
static struct clk extal2_div4_clk = {
.ops = &div2_clk_ops,
.parent = &extal2_div2_clk,
};
/* PLLC1 */
static unsigned long pllc1_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC1CR) & (1 << 14))
mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct sh_clk_ops pllc1_clk_ops = {
.recalc = pllc1_recalc,
};
static struct clk pllc1_clk = {
.ops = &pllc1_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalc1_div2_clk,
};
/* Divide PLLC1 by two */
static struct clk pllc1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pllc1_clk,
};
/* PLLC2 */
static unsigned long pllc2_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC2CR) & (1 << 31))
mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
return clk->parent->rate * mult;
}
static struct sh_clk_ops pllc2_clk_ops = {
.recalc = pllc2_recalc,
};
static struct clk pllc2_clk = {
.ops = &pllc2_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &extalc1_div2_clk,
};
static struct clk *main_clks[] = {
&r_clk,
&sh7377_extalc1_clk,
&sh7377_extal2_clk,
&extalc1_div2_clk,
&extal2_div2_clk,
&extal2_div4_clk,
&pllc1_clk,
&pllc1_div2_clk,
&pllc2_clk,
};
static void div4_kick(struct clk *clk)
{
unsigned long value;
/* set KICK bit in SYFRQCR to update hardware setting */
value = __raw_readl(SYFRQCR);
value |= (1 << 31);
__raw_writel(value, SYFRQCR);
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48, 0, 72, 96, 0 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
[DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
[DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
[DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
[DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
[DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
[DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
[DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
[DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
};
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
DIV6_NR };
static struct clk div6_clks[] = {
[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
[DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
[DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
[DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
[DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
[DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
[DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
[DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
[DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
};
enum { MSTP001,
MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
MSTP315, MSTP314, MSTP313,
MSTP403,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[] = {
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
[MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
/* DIV6 clocks */
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
};
void __init sh7377_clock_init(void)
{
int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
shmobile_clk_init();
else
panic("failed to setup sh7377 clocks\n");
}
arch/arm/mach-shmobile/include/mach/common.h
View file @ ab3ff12a
......@@ -18,24 +18,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
extern void sh7367_init_irq(void);
extern void sh7367_map_io(void);
extern void sh7367_add_early_devices(void);
extern void sh7367_add_standard_devices(void);
extern void sh7367_clock_init(void);
extern void sh7367_pinmux_init(void);
extern struct clk sh7367_extalb1_clk;
extern struct clk sh7367_extal2_clk;
extern void sh7377_init_irq(void);
extern void sh7377_map_io(void);
extern void sh7377_add_early_devices(void);
extern void sh7377_add_standard_devices(void);
extern void sh7377_clock_init(void);
extern void sh7377_pinmux_init(void);
extern struct clk sh7377_extalc1_clk;
extern struct clk sh7377_extal2_clk;
extern void sh7372_init_irq(void);
extern void sh7372_map_io(void);
extern void sh7372_add_early_devices(void);
......
arch/arm/mach-shmobile/include/mach/r8a7779.h
View file @ ab3ff12a
......@@ -71,7 +71,7 @@ enum {
GPIO_FN_A19,
/* IPSR0 */
GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
......
arch/arm/mach-shmobile/include/mach/sh7367.h deleted 100644 → 0
View file @ 631a7b5d
#ifndef __ASM_SH7367_H__
#define __ASM_SH7367_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* 49-1 -> 49-6 (GPIO) */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
/* Special Pull-up / Pull-down Functions */
GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
GPIO_FN_PORT58_KEYIN6_PU,
/* 49-1 (FN) */
GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
/* 49-2 (FN) */
GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
GPIO_FN_XTALB1L,
GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
GPIO_FN_NMI, GPIO_FN_TPU4TO0,
GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
GPIO_FN_IRQ_TMPB,
GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
/* 49-3 (FN) */
GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
GPIO_FN_SCIFA5_RXD,
GPIO_FN_SCIFA5_TXD,
GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
GPIO_FN_A0_EA0, GPIO_FN_BS,
GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
/* 49-4 (FN) */
GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
GPIO_FN_VIO_CKO,
GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
GPIO_FN_LCDD6, GPIO_FN_DV_D6,
GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
GPIO_FN_LCDD7, GPIO_FN_DV_D7,
GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
GPIO_FN_D26, GPIO_FN_ED26,
GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
GPIO_FN_D27, GPIO_FN_ED27,
GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
GPIO_FN_D28, GPIO_FN_ED28,
GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
GPIO_FN_D29, GPIO_FN_ED29,
GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
GPIO_FN_D30, GPIO_FN_ED30,
GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
GPIO_FN_D31, GPIO_FN_ED31,
GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
/* 49-5 (FN) */
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
GPIO_FN_MSIOF1_SS2,
GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
/* 49-6 (FN) */
GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
GPIO_FN_SDHICMD2,
GPIO_FN_RESETOUTS,
GPIO_FN_DIVLOCK,
};
#endif /* __ASM_SH7367_H__ */
arch/arm/mach-shmobile/include/mach/sh7372.h
View file @ ab3ff12a
......@@ -452,6 +452,10 @@ enum {
SHDMA_SLAVE_SCIF5_RX,
SHDMA_SLAVE_SCIF6_TX,
SHDMA_SLAVE_SCIF6_RX,
SHDMA_SLAVE_FLCTL0_TX,
SHDMA_SLAVE_FLCTL0_RX,
SHDMA_SLAVE_FLCTL1_TX,
SHDMA_SLAVE_FLCTL1_RX,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI1_RX,
......@@ -475,8 +479,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
extern struct clk sh7372_pllc2_clk;
extern struct clk sh7372_fsiack_clk;
extern struct clk sh7372_fsibck_clk;
extern struct clk sh7372_fsidiva_clk;
extern struct clk sh7372_fsidivb_clk;
extern void sh7372_intcs_suspend(void);
extern void sh7372_intcs_resume(void);
......
arch/arm/mach-shmobile/include/mach/sh7377.h deleted 100644 → 0
View file @ 631a7b5d
#ifndef __ASM_SH7377_H__
#define __ASM_SH7377_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* 55-1 -> 55-5 (GPIO) */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
/* Special Pull-up / Pull-down Functions */
GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU,
GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU,
GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU,
GPIO_FN_PORT72_KEYIN6_PU,
/* 55-1 (FN) */
GPIO_FN_VBUS_0,
GPIO_FN_CPORT0,
GPIO_FN_CPORT1,
GPIO_FN_CPORT2,
GPIO_FN_CPORT3,
GPIO_FN_CPORT4,
GPIO_FN_CPORT5,
GPIO_FN_CPORT6,
GPIO_FN_CPORT7,
GPIO_FN_CPORT8,
GPIO_FN_CPORT9,
GPIO_FN_CPORT10,
GPIO_FN_CPORT11, GPIO_FN_SIN2,
GPIO_FN_CPORT12, GPIO_FN_XCTS2,
GPIO_FN_CPORT13, GPIO_FN_RFSPO4,
GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2,
GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3,
GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2,
GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_CPORT19_MPORT1,
GPIO_FN_CPORT20, GPIO_FN_RFSPO6,
GPIO_FN_CPORT21, GPIO_FN_STATUS0,
GPIO_FN_CPORT22, GPIO_FN_STATUS1,
GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
GPIO_FN_B_SYNLD1,
GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK,
GPIO_FN_XMAINPS,
GPIO_FN_XDIVPS,
GPIO_FN_XIDRST,
GPIO_FN_IDCLK, GPIO_FN_IC_DP,
GPIO_FN_IDIO, GPIO_FN_IC_DM,
GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT,
GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
GPIO_FN_PCMCLKO,
GPIO_FN_SYNC8KO,
/* 55-2 (FN) */
GPIO_FN_DNPCM_A,
GPIO_FN_UPPCM_A,
GPIO_FN_VACK,
GPIO_FN_XTALB1L,
GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS,
GPIO_FN_GPS_IM,
GPIO_FN_GPS_IS,
GPIO_FN_GPS_QM,
GPIO_FN_GPS_QS,
GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3,
GPIO_FN_FMSIOLR,
GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1,
GPIO_FN_FMSIOBT,
GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2,
GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
GPIO_FN_OPORT3, GPIO_FN_FMSIILR,
GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
GPIO_FN_FMSIIBT,
GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0,
GPIO_FN_A0_EA0, GPIO_FN_BS,
GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2,
GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2,
GPIO_FN_TPU0TO1,
GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5,
GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4,
GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1,
GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD,
GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6,
GPIO_FN_D0_ED0_NAF0,
GPIO_FN_D1_ED1_NAF1,
GPIO_FN_D2_ED2_NAF2,
GPIO_FN_D3_ED3_NAF3,
GPIO_FN_D4_ED4_NAF4,
GPIO_FN_D5_ED5_NAF5,
GPIO_FN_D6_ED6_NAF6,
GPIO_FN_D7_ED7_NAF7,
GPIO_FN_D8_ED8_NAF8,
GPIO_FN_D9_ED9_NAF9,
GPIO_FN_D10_ED10_NAF10,
GPIO_FN_D11_ED11_NAF11,
GPIO_FN_D12_ED12_NAF12,
GPIO_FN_D13_ED13_NAF13,
GPIO_FN_D14_ED14_NAF14,
GPIO_FN_D15_ED15_NAF15,
GPIO_FN_CS4,
GPIO_FN_CS5A, GPIO_FN_FMSICK,
GPIO_FN_CS5B, GPIO_FN_FCE1,
/* 55-3 (FN) */
GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0,
GPIO_FN_FCE0,
GPIO_FN_WAIT, GPIO_FN_DREQ0,
GPIO_FN_RD_XRD,
GPIO_FN_WE0_XWR0_FWE,
GPIO_FN_WE1_XWR1,
GPIO_FN_FRB,
GPIO_FN_CKO,
GPIO_FN_NBRSTOUT,
GPIO_FN_NBRST,
GPIO_FN_GPS_EPPSIN,
GPIO_FN_LATCHPULSE,
GPIO_FN_LTESIGNAL,
GPIO_FN_LEGACYSTATE,
GPIO_FN_TCKON,
GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0,
GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1,
GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD,
GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1,
GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2,
GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC,
GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD,
GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK,
GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2,
GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3,
GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC,
GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR,
GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2,
GPIO_FN_PORT140_FSIAOBT,
GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3,
GPIO_FN_PORT141_FSIAOSLD,
GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK,
GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR,
GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT,
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD,
GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2,
GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5,
GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6,
GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2,
GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD,
/* 55-4 (FN) */
GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0,
GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0,
GPIO_FN_MFG3_IN2,
GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0,
GPIO_FN_MFG3_IN1,
GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0,
GPIO_FN_MFG3_OUT1,
GPIO_FN_TPU3TO0,
GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI,
GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS,
GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS,
GPIO_FN_BBIF2_TSCK1,
GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD,
GPIO_FN_BBIF2_TXD1,
GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD,
GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK,
GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1,
GPIO_FN_LCDD6, GPIO_FN_XWR2,
GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16,
GPIO_FN_ED16,
GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17,
GPIO_FN_ED17,
GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18,
GPIO_FN_ED18,
GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19,
GPIO_FN_ED19,
GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20,
GPIO_FN_ED20,
GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21,
GPIO_FN_ED21,
GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22,
GPIO_FN_ED22,
GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0,
GPIO_FN_VIO_DR7,
GPIO_FN_D23, GPIO_FN_ED23,
GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1,
GPIO_FN_VIO_VDR,
GPIO_FN_D24, GPIO_FN_ED24,
GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25,
GPIO_FN_ED25,
GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
GPIO_FN_ED26,
GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27,
GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
GPIO_FN_ED28,
GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
GPIO_FN_ED29,
GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
GPIO_FN_ED30,
GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
GPIO_FN_ED31,
GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3,
GPIO_FN_VIO_CLKR,
GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC,
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4,
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK,
GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5,
GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD,
GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN,
GPIO_FN_MSIOF0L_TXD,
GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM,
GPIO_FN_PORT226_VIO_CKO2,
GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN,
GPIO_FN_SCIFA1_RXD,
GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC,
GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR,
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT,
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG,
GPIO_FN_PORT233_FSIACK,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2,
GPIO_FN_PORT235_FSIAILR,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT,
GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD,
GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
/* 55-5 (FN) */
GPIO_FN_MSIOF1_SS2,
GPIO_FN_SCIFA6_TXD,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1,
GPIO_FN_TPU4TO0,
GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS,
GPIO_FN_PORT244_MSIOF2_RXD,
GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS,
GPIO_FN_PORT245_MSIOF2_TXD,
GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1,
GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2,
GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1,
GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0,
GPIO_FN_PORT248_MSIOF2_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC,
GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0,
GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0,
GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0,
GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1,
GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2,
GPIO_FN_TMS3_SWDIO_MC1,
GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2,
GPIO_FN_TDO3_SWO0_MC1,
GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2,
GPIO_FN_RTCK3_SWO1_MC1,
GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
GPIO_FN_RESETOUTS,
};
#endif /* __ASM_SH7377_H__ */
arch/arm/mach-shmobile/intc-sh7367.c deleted 100644 → 0
View file @ 631a7b5d
/*
* sh7367 processor support - INTC hardware block
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include <mach/intc.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
enum {
UNUSED_INTCA = 0,
ENABLED,
DISABLED,
/* interrupt sources INTCA */
DIRC,
CRYPT1_ERR, CRYPT2_STD,
IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
ETM11_ACQCMP, ETM11_FULL,
MFI_MFIM, MFI_MFIS,
BBIF1, BBIF2,
USBDMAC_USHDMI,
USBHS_USHI0, USBHS_USHI1,
CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
KEYSC_KEY,
SCIFA0, SCIFA1, SCIFA2, SCIFA3,
MSIOF2, MSIOF1,
SCIFA4, SCIFA5, SCIFB,
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
SDHI0,
SDHI1,
MSU_MSU, MSU_MSU2,
IREM,
SIU,
SPU,
IRDA,
TPU0, TPU1, TPU2, TPU3, TPU4,
LCRC,
PINT1, PINT2,
TTI20,
MISTY,
DDM,
SDHI2,
RWDT0, RWDT1,
DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
/* interrupt groups INTCA */
DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
ETM11, ARM11, USBHS, FLCTL, IIC1
};
static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(DIRC, 0x0560),
INTC_VECT(CRYPT1_ERR, 0x05e0),
INTC_VECT(CRYPT2_STD, 0x0700),
INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
INTC_VECT(ARM11_COMMRX, 0x0860),
INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
INTC_VECT(USBDMAC_USHDMI, 0x0a00),
INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
INTC_VECT(KEYSC_KEY, 0x0be0),
INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
INTC_VECT(SCIFB, 0x0d60),
INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
INTC_VECT(IREM, 0x0f60),
INTC_VECT(SIU, 0x0fa0),
INTC_VECT(SPU, 0x0fc0),
INTC_VECT(IRDA, 0x0480),
INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
INTC_VECT(TPU4, 0x0520),
INTC_VECT(LCRC, 0x0540),
INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
INTC_VECT(TTI20, 0x1100),
INTC_VECT(MISTY, 0x1120),
INTC_VECT(DDM, 0x1140),
INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
INTC_VECT(DMAC_2_DADERR, 0x20c0),
INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
INTC_VECT(DMAC2_2_DADERR, 0x21c0),
INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
INTC_VECT(DMAC3_2_DADERR, 0x22c0),
};
static struct intc_group intca_groups[] __initdata = {
INTC_GROUP(DMAC_1, DMAC_1_DEI0,
DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
INTC_GROUP(DMAC_2, DMAC_2_DEI4,
DMAC_2_DEI5, DMAC_2_DADERR),
INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
DMAC2_2_DEI5, DMAC2_2_DADERR),
INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
DMAC3_2_DEI5, DMAC3_2_DADERR),
INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
};
static struct intc_mask_reg intca_mask_registers[] __initdata = {
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
{ 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
{ CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
{ 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
{ PINT1, PINT2, 0, 0,
BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
{ 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
{ DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
{ 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
{ DDM, 0, 0, 0,
0, 0, ETM11_FULL, ETM11_ACQCMP } },
{ 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
{ KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
{ 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
0, 0, MSIOF2, 0 } },
{ 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
{ DISABLED, ENABLED, ENABLED, ENABLED,
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
{ 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
{ DISABLED, ENABLED, ENABLED, ENABLED,
TTI20, USBDMAC_USHDMI, SPU, SIU } },
{ 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
{ CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
{ 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
{ 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
0, 0, 0, 0 } },
{ 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
{ IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
LCRC, MSU_MSU2, IREM, MSU_MSU } },
{ 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
{ 0, 0, TPU0, TPU1,
TPU2, TPU3, TPU4, 0 } },
{ 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
{ DISABLED, ENABLED, ENABLED, ENABLED,
MISTY, CMT3, RWDT1, RWDT0 } },
};
static struct intc_prio_reg intca_prio_registers[] __initdata = {
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
CMT1_CMT11, ARM11 } },
{ 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
CMT1_CMT12, TPU4 } },
{ 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
MFI_MFIM, USBHS } },
{ 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
0, CMT1_CMT10 } },
{ 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
SCIFA2, SCIFA3 } },
{ 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
FLCTL, SDHI0 } },
{ 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
{ 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
{ 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
{ 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
{ 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
{ 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
{ 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
};
static struct intc_desc intca_desc __initdata = {
.name = "sh7367-intca",
.force_enable = ENABLED,
.force_disable = DISABLED,
.hw = INTC_HW_DESC(intca_vectors, intca_groups,
intca_mask_registers, intca_prio_registers,
NULL, NULL),
};
INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
INTC_VECT, "sh7367-intca-irq-pins");
enum {
UNUSED_INTCS = 0,
INTCS,
/* interrupt sources INTCS */
VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
VIO3_VOU,
RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
VPU,
SGX530,
_2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
IPMMU_IPMMUB, IPMMU_IPMMUS,
RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
MSIOF,
IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
CMT,
TSIF,
IPMMUI,
MVI3,
ICB,
PEP,
ASA,
BEM,
VE2HO,
HQE,
JPEG,
LCDC,
/* interrupt groups INTCS */
_2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
};
static struct intc_vect intcs_vectors[] = {
INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
INTCS_VECT(VIO3_VOU, 0x780),
INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
INTCS_VECT(VPU, 0x980),
INTCS_VECT(SGX530, 0x9e0),
INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
INTCS_VECT(MSIOF, 0xd20),
INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
INTCS_VECT(TMU_TUNI2, 0xec0),
INTCS_VECT(CMT, 0xf00),
INTCS_VECT(TSIF, 0xf20),
INTCS_VECT(IPMMUI, 0xf60),
INTCS_VECT(MVI3, 0x420),
INTCS_VECT(ICB, 0x480),
INTCS_VECT(PEP, 0x4a0),
INTCS_VECT(ASA, 0x4c0),
INTCS_VECT(BEM, 0x4e0),
INTCS_VECT(VE2HO, 0x520),
INTCS_VECT(HQE, 0x540),
INTCS_VECT(JPEG, 0x560),
INTCS_VECT(LCDC, 0x580),
INTC_VECT(INTCS, 0xf80),
};
static struct intc_group intcs_groups[] __initdata = {
INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
_2DDMAC_2DDM2, _2DDMAC_2DDM3),
INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
RTDMAC_1_DEI2, RTDMAC_1_DEI3),
INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
};
static struct intc_mask_reg intcs_mask_registers[] = {
{ 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
{ VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
{ 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
{ VIO3_VOU, 0, VE2HO, VPU,
0, 0, 0, 0 } },
{ 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
{ _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
BEM, ASA, PEP, ICB } },
{ 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
{ 0, 0, MVI3, 0,
JPEG, HQE, 0, LCDC } },
{ 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
{ 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
{ 0, 0, MSIOF, 0,
SGX530, 0, 0, 0 } },
{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
0, 0, 0, 0 } },
{ 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
{ 0, 0, 0, CMT,
IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
{ 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
{ IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
0, 0, 0, 0 } },
{ 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
0, 0, IPMMUI, TSIF } },
{ 0xffd20104, 0, 16, /* INTAMASK */
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, INTCS } },
};
/* Priority is needed for INTCA to receive the INTCS interrupt */
static struct intc_prio_reg intcs_prio_registers[] = {
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
{ 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
{ 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
TMU_TUNI2, 0 } },
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
{ 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
};
static struct resource intcs_resources[] __initdata = {
[0] = {
.start = 0xffd20000,
.end = 0xffd2ffff,
.flags = IORESOURCE_MEM,
}
};
static struct intc_desc intcs_desc __initdata = {
.name = "sh7367-intcs",
.resource = intcs_resources,
.num_resources = ARRAY_SIZE(intcs_resources),
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
intcs_prio_registers, NULL, NULL),
};
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
{
void __iomem *reg = (void *)irq_get_handler_data(irq);
unsigned int evtcodeas = ioread32(reg);
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
void __init sh7367_init_irq(void)
{
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
register_intc_controller(&intca_desc);
register_intc_controller(&intca_irq_pins_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
}
arch/arm/mach-shmobile/intc-sh7377.c deleted 100644 → 0
View file @ 631a7b5d
/*
* sh7377 processor support - INTC hardware block
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
#include <mach/intc.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
enum {
UNUSED_INTCA = 0,
ENABLED,
DISABLED,
/* interrupt sources INTCA */
DIRC,
_2DG,
CRYPT_STD,
IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
MFI_MFIM, MFI_MFIS,
BBIF1, BBIF2,
USBDMAC_USHDMI,
USBHS_USHI0, USBHS_USHI1,
_3DG_SGX540,
CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
KEYSC_KEY,
SCIFA0, SCIFA1, SCIFA2, SCIFA3,
MSIOF2, MSIOF1,
SCIFA4, SCIFA5, SCIFB,
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
SDHI0,
SDHI1,
MSU_MSU, MSU_MSU2,
IRREM,
MSUG,
IRDA,
TPU0, TPU1, TPU2, TPU3, TPU4,
LCRC,
PINTCA_PINT1, PINTCA_PINT2,
TTI20,
MISTY,
DDM,
RWDT0, RWDT1,
DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
ICUSB_ICUSB0, ICUSB_ICUSB1,
ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
SPU2_SPU0, SPU2_SPU1,
FSI,
FMSI,
SCUV,
IPMMU_IPMMUB,
AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
MFIS2,
CPORTR2S,
CMT14, CMT15,
SCIFA6,
/* interrupt groups INTCA */
DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
ICUSB, ICUDMC
};
static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(DIRC, 0x0560),
INTC_VECT(_2DG, 0x05e0),
INTC_VECT(CRYPT_STD, 0x0700),
INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
INTC_VECT(AP_ARM_COMMRX, 0x0860),
INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
INTC_VECT(USBDMAC_USHDMI, 0x0a00),
INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
INTC_VECT(_3DG_SGX540, 0x0a60),
INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
INTC_VECT(KEYSC_KEY, 0x0be0),
INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
INTC_VECT(SCIFB, 0x0d60),
INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
INTC_VECT(IRREM, 0x0f60),
INTC_VECT(MSUG, 0x0fa0),
INTC_VECT(IRDA, 0x0480),
INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
INTC_VECT(TPU4, 0x0520),
INTC_VECT(LCRC, 0x0540),
INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
INTC_VECT(TTI20, 0x1100),
INTC_VECT(MISTY, 0x1120),
INTC_VECT(DDM, 0x1140),
INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
INTC_VECT(DMAC_2_DADERR, 0x20c0),
INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
INTC_VECT(DMAC2_2_DADERR, 0x21c0),
INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
INTC_VECT(DMAC3_2_DADERR, 0x22c0),
INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
INTC_VECT(SHWYSTAT_COM, 0x1340),
INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
INTC_VECT(FSI, 0x1840),
INTC_VECT(FMSI, 0x1860),
INTC_VECT(SCUV, 0x1880),
INTC_VECT(IPMMU_IPMMUB, 0x1900),
INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
INTC_VECT(MFIS2, 0x1a00),
INTC_VECT(CPORTR2S, 0x1a20),
INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
INTC_VECT(SCIFA6, 0x1a80),
};
static struct intc_group intca_groups[] __initdata = {
INTC_GROUP(DMAC_1, DMAC_1_DEI0,
DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
INTC_GROUP(DMAC_2, DMAC_2_DEI4,
DMAC_2_DEI5, DMAC_2_DADERR),
INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
DMAC2_2_DEI5, DMAC2_2_DADERR),
INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
DMAC3_2_DEI5, DMAC3_2_DADERR),
INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
};
static struct intc_mask_reg intca_mask_registers[] __initdata = {
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
{ 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
{ _2DG, CRYPT_STD, DIRC, 0,
DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
{ 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
{ PINTCA_PINT1, PINTCA_PINT2, 0, 0,
BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
{ 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
{ DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
{ 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
{ DDM, 0, 0, 0,
0, 0, 0, 0 } },
{ 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
{ KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
{ 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
0, 0, MSIOF2, 0 } },
{ 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
{ DISABLED, ENABLED, ENABLED, ENABLED,
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
{ 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
{ DISABLED, ENABLED, ENABLED, ENABLED,
TTI20, USBDMAC_USHDMI, 0, MSUG } },
{ 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
{ CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
{ 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
{ 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
0, 0, 0, 0 } },
{ 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
{ IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
LCRC, MSU_MSU2, IRREM, MSU_MSU } },
{ 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
{ 0, 0, TPU0, TPU1,
TPU2, TPU3, TPU4, 0 } },
{ 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
{ 0, 0, 0, 0,
MISTY, CMT3, RWDT1, RWDT0 } },
{ 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
{ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
0, 0, 0, 0 } },
{ 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
{ ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
{ 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
{ SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
SCUV, 0, 0, 0 } },
{ 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
{ IPMMU_IPMMUB, 0, 0, 0,
AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
{ 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
{ MFIS2, CPORTR2S, CMT14, CMT15,
SCIFA6, 0, 0, 0 } },
};
static struct intc_prio_reg intca_prio_registers[] __initdata = {
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
CMT1_CMT11, AP_ARM1 } },
{ 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
CMT1_CMT12, TPU4 } },
{ 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
MFI_MFIM, USBHS } },
{ 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
_3DG_SGX540, CMT1_CMT10 } },
{ 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
SCIFA2, SCIFA3 } },
{ 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
FLCTL, SDHI0 } },
{ 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
{ 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
{ 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
{ 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
{ 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
{ 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
{ 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
{ 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
{ 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
{ 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
{ 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
{ 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
{ 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
{ 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
{ 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
CMT14, CMT15 } },
{ 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
};
static struct intc_desc intca_desc __initdata = {
.name = "sh7377-intca",
.force_enable = ENABLED,
.force_disable = DISABLED,
.hw = INTC_HW_DESC(intca_vectors, intca_groups,
intca_mask_registers, intca_prio_registers,
NULL, NULL),
};
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
INTC_VECT, "sh7377-intca-irq-pins");
/* this macro ignore entry which is also in INTCA */
#define __IGNORE(a...)
#define __IGNORE0(a...) 0
enum {
UNUSED_INTCS = 0,
INTCS,
/* interrupt sources INTCS */
VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
CEU,
BEU_BEU0, BEU_BEU1, BEU_BEU2,
__IGNORE(MFI)
__IGNORE(BBIF2)
VPU,
TSIF1,
__IGNORE(SGX540)
_2DDMAC,
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
IPMMU_IPMMUR, IPMMU_IPMMUR2,
RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
__IGNORE(KEYSC)
__IGNORE(TTI20)
__IGNORE(MSIOF)
IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
CMT0,
TSIF0,
__IGNORE(CMT2)
LMB,
__IGNORE(MSUG)
__IGNORE(MSU_MSU, MSU_MSU2)
__IGNORE(CTI)
MVI3,
__IGNORE(RWDT0)
__IGNORE(RWDT1)
ICB,
PEP,
ASA,
__IGNORE(_2DG)
HQE,
JPU,
LCDC0,
__IGNORE(LCRC)
RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
FRC,
LCDC1,
CSIRX,
DSITX_DSITX0, DSITX_DSITX1,
__IGNORE(SPU2_SPU0, SPU2_SPU1)
__IGNORE(FSI)
__IGNORE(FMSI)
__IGNORE(SCUV)
TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
TSIF2,
CMT4,
__IGNORE(MFIS2)
CPORTS2R,
/* interrupt groups INTCS */
RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
};
#define INTCS_INTVECT 0x0F80
static struct intc_vect intcs_vectors[] __initdata = {
INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
INTCS_VECT(CEU, 0x0880),
INTCS_VECT(BEU_BEU0, 0x08A0),
INTCS_VECT(BEU_BEU1, 0x08C0),
INTCS_VECT(BEU_BEU2, 0x08E0),
__IGNORE(INTCS_VECT(MFI, 0x0900))
__IGNORE(INTCS_VECT(BBIF2, 0x0960))
INTCS_VECT(VPU, 0x0980),
INTCS_VECT(TSIF1, 0x09A0),
__IGNORE(INTCS_VECT(SGX540, 0x09E0))
INTCS_VECT(_2DDMAC, 0x0A00),
INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
__IGNORE(INTCS_VECT(KEYSC 0x0BE0))
__IGNORE(INTCS_VECT(TTI20, 0x0C80))
__IGNORE(INTCS_VECT(MSIOF, 0x0D20))
INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
INTCS_VECT(TMU_TUNI0, 0x0E80),
INTCS_VECT(TMU_TUNI1, 0x0EA0),
INTCS_VECT(TMU_TUNI2, 0x0EC0),
INTCS_VECT(CMT0, 0x0F00),
INTCS_VECT(TSIF0, 0x0F20),
__IGNORE(INTCS_VECT(CMT2, 0x0F40))
INTCS_VECT(LMB, 0x0F60),
__IGNORE(INTCS_VECT(MSUG, 0x0F80))
__IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
__IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
__IGNORE(INTCS_VECT(CTI, 0x0400))
INTCS_VECT(MVI3, 0x0420),
__IGNORE(INTCS_VECT(RWDT0, 0x0440))
__IGNORE(INTCS_VECT(RWDT1, 0x0460))
INTCS_VECT(ICB, 0x0480),
INTCS_VECT(PEP, 0x04A0),
INTCS_VECT(ASA, 0x04C0),
__IGNORE(INTCS_VECT(_2DG, 0x04E0))
INTCS_VECT(HQE, 0x0540),
INTCS_VECT(JPU, 0x0560),
INTCS_VECT(LCDC0, 0x0580),
__IGNORE(INTCS_VECT(LCRC, 0x05A0))
INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
INTCS_VECT(FRC, 0x1700),
INTCS_VECT(LCDC1, 0x1780),
INTCS_VECT(CSIRX, 0x17A0),
INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
__IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
__IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
__IGNORE(INTCS_VECT(FSI, 0x1840))
__IGNORE(INTCS_VECT(FMSI, 0x1860))
__IGNORE(INTCS_VECT(SCUV, 0x1880))
INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
INTCS_VECT(TMU1_TUNI12, 0x1940),
INTCS_VECT(TSIF2, 0x1960),
INTCS_VECT(CMT4, 0x1980),
__IGNORE(INTCS_VECT(MFIS2, 0x1A00))
INTCS_VECT(CPORTS2R, 0x1A20),
INTC_VECT(INTCS, INTCS_INTVECT),
};
static struct intc_group intcs_groups[] __initdata = {
INTC_GROUP(RTDMAC1_1,
RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
INTC_GROUP(RTDMAC1_2,
RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
__IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
INTC_GROUP(RTDMAC2_1,
RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
__IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
};
static struct intc_mask_reg intcs_mask_registers[] __initdata = {
{ 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
{ BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
{ 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
{ 0, 0, 0, VPU,
__IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
{ 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
{ 0, 0, 0, _2DDMAC,
__IGNORE0(_2DG), ASA, PEP, ICB } },
{ 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
{ 0, 0, MVI3, __IGNORE0(CTI),
JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
{ 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
{ __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
__IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
{ 0, 0, MSIOF, 0,
SGX540, 0, TTI20, 0 } })
{ 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
0, 0, 0, 0 } },
__IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
{ 0, 0, 0, 0,
0, MSU_MSU, MSU_MSU2, MSUG } })
{ 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
{ __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
{ 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
{ 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
0, 0, 0, 0 } },
{ 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
{ IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
0, TSIF1, LMB, TSIF0 } },
{ 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
{ RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
{ 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
{ FRC, 0, 0, 0,
LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
__IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
{SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
SCUV, 0, 0, 0 } })
{ 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
{ TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
CMT4, 0, 0, 0 } },
{ 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
{ __IGNORE0(MFIS2), CPORTS2R, 0, 0,
0, 0, 0, 0 } },
{ 0xFFD20104, 0, 16, /* INTAMASK */
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, INTCS } }
};
static struct intc_prio_reg intcs_prio_registers[] __initdata = {
/* IPRAS */
{ 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
/* IPRBS */
{ 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
/* IPRCS */
__IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
/* IPRES */
{ 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
/* IPRFS */
{ 0xFFD20014, 0, 16, 4,
{ __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
/* IPRGS */
{ 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
/* IPRHS */
{ 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
/* IPRIS */
{ 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
/* IPRJS */
__IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
/* IPRKS */
{ 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
/* IPRLS */
{ 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
/* IPRMS */
{ 0xFFD20030, 0, 16, 4,
{ IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
/* IPRAS3 */
{ 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
/* IPRBS3 */
{ 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
/* IPRIS3 */
{ 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
/* IPRJS3 */
{ 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
/* IPRKS3 */
__IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
/* IPRLS3 */
__IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
/* IPRMS3 */
{ 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
/* IPRNS3 */
{ 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
/* IPROS3 */
{ 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
};
static struct resource intcs_resources[] __initdata = {
[0] = {
.start = 0xffd20000,
.end = 0xffd500ff,
.flags = IORESOURCE_MEM,
}
};
static struct intc_desc intcs_desc __initdata = {
.name = "sh7377-intcs",
.resource = intcs_resources,
.num_resources = ARRAY_SIZE(intcs_resources),
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
intcs_mask_registers, intcs_prio_registers,
NULL, NULL),
};
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
{
void __iomem *reg = (void *)irq_get_handler_data(irq);
unsigned int evtcodeas = ioread32(reg);
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
#define INTEVTSA 0xFFD20100
void __init sh7377_init_irq(void)
{
void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
register_intc_controller(&intca_desc);
register_intc_controller(&intca_irq_pins_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
}
arch/arm/mach-shmobile/pfc-r8a7779.c
View file @ ab3ff12a
......@@ -140,7 +140,7 @@ enum {
FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
/* GPSR5 */
......@@ -176,7 +176,7 @@ enum {
FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
FN_SCIF_CLK, FN_TCLK0_C,
/* IPSR1 */
......@@ -447,7 +447,7 @@ enum {
A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
SCIF_CLK_MARK, TCLK0_C_MARK,
EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
......@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(A18_MARK, FN_A18),
PINMUX_DATA(A19_MARK, FN_A19),
PINMUX_IPSR_DATA(IP0_2_0, PENC2),
PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
PINMUX_IPSR_DATA(IP0_2_0, PWM1),
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
......@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(A19),
/* IPSR0 */
GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
......@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_30_FN, FN_IP8_18,
GP_4_29_FN, FN_IP8_17_16,
GP_4_28_FN, FN_IP0_2_0,
GP_4_27_FN, FN_PENC1,
GP_4_26_FN, FN_PENC0,
GP_4_27_FN, FN_USB_PENC1,
GP_4_26_FN, FN_USB_PENC0,
GP_4_25_FN, FN_IP8_15_12,
GP_4_24_FN, FN_IP8_11_8,
GP_4_23_FN, FN_IP8_7_4,
......@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
/* IP0_2_0 [3] */
FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
......
arch/arm/mach-shmobile/pfc-sh7367.c deleted 100644 → 0
View file @ 631a7b5d
/*
* sh7367 processor support - PFC hardware block
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sh_pfc.h>
#include <mach/sh7367.h>
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
/* Special Pull-up / Pull-down Functions */
PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
PORT58_KEYIN6_PU_MARK,
/* 49-1 */
VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
XCTS1_MARK, SCIFA4_CTS_MARK,
/* 49-2 */
HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
HSU_SDI_MARK, PORT55_KEYIN3_MARK,
HSU_SCO_MARK, PORT56_KEYIN4_MARK,
HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
HSU_DACK_MARK, PORT58_KEYIN6_MARK,
HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
XTALB1L_MARK,
GPS_AGC1_MARK, SCIFA0_RTS_MARK,
GPS_AGC2_MARK, SCIFA0_SCK_MARK,
GPS_AGC3_MARK, SCIFA0_TXD_MARK,
GPS_AGC4_MARK, SCIFA0_RXD_MARK,
GPS_PWRD_MARK, SCIFA0_CTS_MARK,
GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
SIUBOMC_MARK, TPU2TO0_MARK,
SIUCKB_MARK, TPU2TO1_MARK,
SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
SIUBILR_MARK, TPU3TO1_MARK,
SIUBIBT_MARK, TPU3TO2_MARK,
SIUBISLD_MARK, TPU3TO3_MARK,
NMI_MARK, TPU4TO0_MARK,
DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
IRQ_TMPB_MARK,
PWEN_MARK, MFG1_OUT1_MARK,
OVCN_MARK, MFG1_IN1_MARK,
OVCN2_MARK, MFG1_IN2_MARK,
/* 49-3 */
RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
SCIFA5_CTS_MARK, MFG0_IN1_MARK,
SCIFA5_RTS_MARK, MFG0_IN2_MARK,
SCIFA5_RXD_MARK,
SCIFA5_TXD_MARK,
SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
A0_EA0_MARK, BS_MARK,
A14_EA14_MARK, PORT102_KEYOUT0_MARK,
A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
A16_EA16_MARK, PORT104_KEYOUT2_MARK,
DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
A17_EA17_MARK, PORT105_KEYOUT3_MARK,
DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
A18_EA18_MARK, PORT106_KEYOUT4_MARK,
DV_DL0_MARK, MSIOF0_TSCK_MARK,
A19_EA19_MARK, PORT107_KEYOUT5_MARK,
DV_DL1_MARK, MSIOF0_TXD_MARK,
A20_EA20_MARK, PORT108_KEYIN0_MARK,
DV_DL2_MARK, MSIOF0_RSCK_MARK,
A21_EA21_MARK, PORT109_KEYIN1_MARK,
DV_DL3_MARK, MSIOF0_RSYNC_MARK,
A22_EA22_MARK, PORT110_KEYIN2_MARK,
DV_DL4_MARK, MSIOF0_MCK0_MARK,
A23_EA23_MARK, PORT111_KEYIN3_MARK,
DV_DL5_MARK, MSIOF0_MCK1_MARK,
A24_EA24_MARK, PORT112_KEYIN4_MARK,
DV_DL6_MARK, MSIOF0_RXD_MARK,
A25_EA25_MARK, PORT113_KEYIN5_MARK,
DV_DL7_MARK, MSIOF0_SS2_MARK,
A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
NBRSTOUT_MARK, NBRST_MARK,
/* 49-4 */
RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
VIO_VD_MARK, VIO_HD_MARK,
VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
VIO_CKO_MARK,
MFG3_IN1_MARK, MFG3_IN2_MARK,
M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
SIUCKA_MARK, MFG0_OUT2_MARK,
LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
SIUAOBT_MARK, BBIF2_TSCK1_MARK,
LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
SIUAOSLD_MARK, BBIF2_TXD1_MARK,
LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
SIUAISPD_MARK, MFG1_OUT2_MARK,
LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
SIUAILR_MARK, MFG2_OUT2_MARK,
LCDD6_MARK, DV_D6_MARK,
SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
LCDD7_MARK, DV_D7_MARK,
SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
D26_MARK, ED26_MARK,
LCDD19_MARK, MSIOF0L_TSYNC_MARK,
D27_MARK, ED27_MARK,
LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
D28_MARK, ED28_MARK,
LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
D29_MARK, ED29_MARK,
LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
D30_MARK, ED30_MARK,
LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
D31_MARK, ED31_MARK,
LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
/* 49-5 */
LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
VIO_VDR_MARK, VIO_HDR_MARK,
VIO_CLKR_MARK, VIO_CKOR_MARK,
SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
MSIOF1_SS1_MARK, EDBGREQ3_MARK,
MSIOF1_SS2_MARK,
PORT236_IROUT_MARK, IRDA_OUT_MARK,
IRDA_IN_MARK, IRDA_FIRSEL_MARK,
TPU1TO0_MARK, TS_SPSYNC3_MARK,
TPU1TO1_MARK, TS_SDAT3_MARK,
TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
PORT245_IROUT_MARK, M15_RSW_MARK,
SOUT3_MARK, SCIFA2_TXD1_MARK,
SIN3_MARK, SCIFA2_RXD1_MARK,
XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
SDHICLK0_MARK, TCK2_MARK,
SDHICD0_MARK,
SDHID0_0_MARK, TMS2_MARK,
SDHID0_1_MARK, TDO2_MARK,
SDHID0_2_MARK, TDI2_MARK,
SDHID0_3_MARK, RTCK2_MARK,
/* 49-6 */
SDHICMD0_MARK, TRST2_MARK,
SDHIWP0_MARK, EDBGREQ2_MARK,
SDHICLK1_MARK, TCK3_MARK,
SDHID1_0_MARK, M11_SLCD_SO2_MARK,
TS_SPSYNC2_MARK, TMS3_MARK,
SDHID1_1_MARK, M9_SLCD_AO2_MARK,
TS_SDAT2_MARK, TDO3_MARK,
SDHID1_2_MARK, M10_SLCD_CK2_MARK,
TS_SDEN2_MARK, TDI3_MARK,
SDHID1_3_MARK, M12_SLCD_CE2_MARK,
TS_SCK2_MARK, RTCK3_MARK,
SDHICMD1_MARK, TRST3_MARK,
SDHICLK2_MARK, SCIFB_SCK_MARK,
SDHID2_0_MARK, SCIFB_TXD_MARK,
SDHID2_1_MARK, SCIFB_CTS_MARK,
SDHID2_2_MARK, SCIFB_RXD_MARK,
SDHID2_3_MARK, SCIFB_RTS_MARK,
SDHICMD2_MARK,
RESETOUTS_MARK,
DIVLOCK_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* 49-1 (GPIO) */
PORT_DATA_I_PD(0),
PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
PORT_DATA_I_PU(13),
PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
PORT_DATA_IO_PU(33),
PORT_DATA_O(34),
PORT_DATA_I_PU(35),
PORT_DATA_O(36),
PORT_DATA_I_PU_PD(37),
/* 49-2 (GPIO) */
PORT_DATA_IO_PU_PD(38),
PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
PORT_DATA_O(46), PORT_DATA_O(47),
PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
PORT_DATA_O(53),
PORT_DATA_IO_PD(54),
PORT_DATA_I_PU_PD(55),
PORT_DATA_IO_PU_PD(56),
PORT_DATA_I_PU_PD(57),
PORT_DATA_IO_PU_PD(58),
PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
PORT_DATA_O(63),
PORT_DATA_I_PU(64),
PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
PORT_DATA_I_PD(74),
PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
PORT_DATA_O(79),
PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
PORT_DATA_I_PD(87),
PORT_DATA_IO_PU_PD(88),
PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
/* 49-3 (GPIO) */
PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
PORT_DATA_I_PU_PD(95),
PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
PORT_DATA_IO_PD(107),
PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
PORT_DATA_IO_PU_PD(114),
PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
PORT_DATA_IO_PU(130),
PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
PORT_DATA_IO_PU(134),
PORT_DATA_O(135), PORT_DATA_O(136),
PORT_DATA_I_PU_PD(137),
PORT_DATA_IO(138),
PORT_DATA_IO_PU_PD(139),
PORT_DATA_IO(140), PORT_DATA_IO(141),
PORT_DATA_I_PU(142),
PORT_DATA_O(143), PORT_DATA_O(144),
PORT_DATA_I_PU(145),
/* 49-4 (GPIO) */
PORT_DATA_O(146),
PORT_DATA_I_PU_PD(147),
PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
PORT_DATA_IO_PU_PD(167),
PORT_DATA_O(168),
PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
PORT_DATA_O(171),
PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
PORT_DATA_O(174),
PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
PORT_DATA_O(199),
PORT_DATA_IO_PD(200),
/* 49-5 (GPIO) */
PORT_DATA_O(201),
PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
PORT_DATA_I(204),
PORT_DATA_O(205),
PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
PORT_DATA_O(217),
PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
PORT_DATA_I_PD(223),
PORT_DATA_I_PU_PD(224),
PORT_DATA_O(225),
PORT_DATA_IO_PD(226),
PORT_DATA_IO_PU_PD(227),
PORT_DATA_I_PD(228),
PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
PORT_DATA_I_PU_PD(235),
PORT_DATA_O(236),
PORT_DATA_I_PD(237),
PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
PORT_DATA_O(244),
PORT_DATA_IO_PU_PD(245),
PORT_DATA_O(246),
PORT_DATA_I_PD(247),
PORT_DATA_IO_PU_PD(248),
PORT_DATA_I_PU_PD(249),
PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
PORT_DATA_IO_PU_PD(256),
/* 49-6 (GPIO) */
PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
PORT_DATA_IO_PD(259),
PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
PORT_DATA_O(265),
PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
PORT_DATA_O(271),
PORT_DATA_I_PD(272),
/* Special Pull-up / Pull-down Functions */
PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
PORT48_FN2, PORT48_IN_PU),
PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
PORT49_FN2, PORT49_IN_PU),
PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
PORT50_FN2, PORT50_IN_PU),
PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
PORT55_FN2, PORT55_IN_PU),
PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
PORT56_FN2, PORT56_IN_PU),
PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
PORT57_FN2, PORT57_IN_PU),
PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
PORT58_FN2, PORT58_IN_PU),
/* 49-1 (FN) */
PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
PINMUX_DATA(SIN2_MARK, PORT12_FN2),
PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
PINMUX_DATA(IDIO_MARK, PORT33_FN1),
PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
PINMUX_DATA(SIN1_MARK, PORT35_FN1),
PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
PINMUX_DATA(XWUP_MARK, PORT35_FN3),
PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
/* 49-2 (FN) */
PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
PINMUX_DATA(NMI_MARK, PORT83_FN1),
PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
PINMUX_DATA(PWEN_MARK, PORT88_FN1),
PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
PINMUX_DATA(OVCN_MARK, PORT89_FN1),
PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
/* 49-3 (FN) */
PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
PINMUX_DATA(IDIN_MARK, PORT95_FN1),
PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
PINMUX_DATA(BS_MARK, PORT101_FN2),
PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
PINMUX_DATA(A26_MARK, PORT114_FN1),
PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
PINMUX_DATA(CS4_MARK, PORT131_FN1),
PINMUX_DATA(CS5A_MARK, PORT132_FN1),
PINMUX_DATA(CS5B_MARK, PORT133_FN1),
PINMUX_DATA(FCE1_MARK, PORT133_FN2),
PINMUX_DATA(CS6B_MARK, PORT134_FN1),
PINMUX_DATA(XCS2_MARK, PORT134_FN2),
PINMUX_DATA(FCE0_MARK, PORT135_FN1),
PINMUX_DATA(CS6A_MARK, PORT136_FN1),
PINMUX_DATA(DACK0_MARK, PORT136_FN2),
PINMUX_DATA(WAIT_MARK, PORT137_FN1),
PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
PINMUX_DATA(A27_MARK, PORT139_FN1),
PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
PINMUX_DATA(FRB_MARK, PORT142_FN1),
PINMUX_DATA(CKO_MARK, PORT143_FN1),
PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
PINMUX_DATA(NBRST_MARK, PORT145_FN1),
/* 49-4 (FN) */
PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
PINMUX_DATA(XWR2_MARK, PORT181_FN7),
PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
PINMUX_DATA(XWR3_MARK, PORT182_FN7),
PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
PINMUX_DATA(D16_MARK, PORT183_FN6),
PINMUX_DATA(ED16_MARK, PORT183_FN7),
PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
PINMUX_DATA(D17_MARK, PORT184_FN6),
PINMUX_DATA(ED17_MARK, PORT184_FN7),
PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
PINMUX_DATA(D18_MARK, PORT185_FN6),
PINMUX_DATA(ED18_MARK, PORT185_FN7),
PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
PINMUX_DATA(D19_MARK, PORT186_FN6),
PINMUX_DATA(ED19_MARK, PORT186_FN7),
PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
PINMUX_DATA(D20_MARK, PORT187_FN6),
PINMUX_DATA(ED20_MARK, PORT187_FN7),
PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
PINMUX_DATA(D21_MARK, PORT188_FN6),
PINMUX_DATA(ED21_MARK, PORT188_FN7),
PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
PINMUX_DATA(D22_MARK, PORT189_FN6),
PINMUX_DATA(ED22_MARK, PORT189_FN7),
PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
PINMUX_DATA(D23_MARK, PORT190_FN6),
PINMUX_DATA(ED23_MARK, PORT190_FN7),
PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
PINMUX_DATA(D24_MARK, PORT191_FN6),
PINMUX_DATA(ED24_MARK, PORT191_FN7),
PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
PINMUX_DATA(D25_MARK, PORT192_FN6),
PINMUX_DATA(ED25_MARK, PORT192_FN7),
PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
PINMUX_DATA(D26_MARK, PORT193_FN6),
PINMUX_DATA(ED26_MARK, PORT193_FN7),
PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
PINMUX_DATA(D27_MARK, PORT194_FN6),
PINMUX_DATA(ED27_MARK, PORT194_FN7),
PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
PINMUX_DATA(D28_MARK, PORT195_FN6),
PINMUX_DATA(ED28_MARK, PORT195_FN7),
PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
PINMUX_DATA(D29_MARK, PORT196_FN6),
PINMUX_DATA(ED29_MARK, PORT196_FN7),
PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
PINMUX_DATA(D30_MARK, PORT197_FN6),
PINMUX_DATA(ED30_MARK, PORT197_FN7),
PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
PINMUX_DATA(D31_MARK, PORT198_FN6),
PINMUX_DATA(ED31_MARK, PORT198_FN7),
PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
PINMUX_DATA(DACK2_MARK, PORT200_FN2),
PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
/* 49-5 (FN) */
PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
PINMUX_DATA(DACK3_MARK, PORT201_FN4),
PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
PINMUX_DATA(DACK1_MARK, PORT205_FN3),
PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
PINMUX_DATA(SIN3_MARK, PORT247_FN1),
PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
PINMUX_DATA(DINT_MARK, PORT250_FN1),
PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
PINMUX_DATA(TCK2_MARK, PORT251_FN2),
PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
PINMUX_DATA(TMS2_MARK, PORT253_FN2),
PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
PINMUX_DATA(TDO2_MARK, PORT254_FN2),
PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
PINMUX_DATA(TDI2_MARK, PORT255_FN2),
PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
/* 49-6 (FN) */
PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
PINMUX_DATA(TRST2_MARK, PORT257_FN2),
PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
PINMUX_DATA(TCK3_MARK, PORT259_FN4),
PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
PINMUX_DATA(TMS3_MARK, PORT260_FN4),
PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
PINMUX_DATA(TDO3_MARK, PORT261_FN4),
PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
PINMUX_DATA(TDI3_MARK, PORT262_FN4),
PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
PINMUX_DATA(TRST3_MARK, PORT264_FN4),
PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
};
static struct pinmux_gpio pinmux_gpios[] = {
/* 49-1 -> 49-6 (GPIO) */
GPIO_PORT_ALL(),
/* Special Pull-up / Pull-down Functions */
GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
GPIO_FN(PORT58_KEYIN6_PU),
/* 49-1 (FN) */
GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
/* 49-2 (FN) */
GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
GPIO_FN(XTALB1L),
GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
GPIO_FN(NMI), GPIO_FN(TPU4TO0),
GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
GPIO_FN(IRQ_TMPB),
GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
/* 49-3 (FN) */
GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
GPIO_FN(PORT93_VIO_CKO2),
GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
GPIO_FN(SCIFA5_RXD),
GPIO_FN(SCIFA5_TXD),
GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
GPIO_FN(A0_EA0), GPIO_FN(BS),
GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
/* 49-4 (FN) */
GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
GPIO_FN(VIO_CKO),
GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
GPIO_FN(LCDD6), GPIO_FN(DV_D6),
GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
GPIO_FN(LCDD7), GPIO_FN(DV_D7),
GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
GPIO_FN(D26), GPIO_FN(ED26),
GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
GPIO_FN(D27), GPIO_FN(ED27),
GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
GPIO_FN(D28), GPIO_FN(ED28),
GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
GPIO_FN(D29), GPIO_FN(ED29),
GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
GPIO_FN(D30), GPIO_FN(ED30),
GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
GPIO_FN(D31), GPIO_FN(ED31),
GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
/* 49-5 (FN) */
GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
GPIO_FN(MSIOF1_SS2),
GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
GPIO_FN(SDHICD0),
GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
/* 49-6 (FN) */
GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
GPIO_FN(SDHICMD2),
GPIO_FN(RESETOUTS),
GPIO_FN(DIVLOCK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
PORTCR(3, 0xe6050003), /* PORT3CR */
PORTCR(4, 0xe6050004), /* PORT4CR */
PORTCR(5, 0xe6050005), /* PORT5CR */
PORTCR(6, 0xe6050006), /* PORT6CR */
PORTCR(7, 0xe6050007), /* PORT7CR */
PORTCR(8, 0xe6050008), /* PORT8CR */
PORTCR(9, 0xe6050009), /* PORT9CR */
PORTCR(10, 0xe605000a), /* PORT10CR */
PORTCR(11, 0xe605000b), /* PORT11CR */
PORTCR(12, 0xe605000c), /* PORT12CR */
PORTCR(13, 0xe605000d), /* PORT13CR */
PORTCR(14, 0xe605000e), /* PORT14CR */
PORTCR(15, 0xe605000f), /* PORT15CR */
PORTCR(16, 0xe6050010), /* PORT16CR */
PORTCR(17, 0xe6050011), /* PORT17CR */
PORTCR(18, 0xe6050012), /* PORT18CR */
PORTCR(19, 0xe6050013), /* PORT19CR */
PORTCR(20, 0xe6050014), /* PORT20CR */
PORTCR(21, 0xe6050015), /* PORT21CR */
PORTCR(22, 0xe6050016), /* PORT22CR */
PORTCR(23, 0xe6050017), /* PORT23CR */
PORTCR(24, 0xe6050018), /* PORT24CR */
PORTCR(25, 0xe6050019), /* PORT25CR */
PORTCR(26, 0xe605001a), /* PORT26CR */
PORTCR(27, 0xe605001b), /* PORT27CR */
PORTCR(28, 0xe605001c), /* PORT28CR */
PORTCR(29, 0xe605001d), /* PORT29CR */
PORTCR(30, 0xe605001e), /* PORT30CR */
PORTCR(31, 0xe605001f), /* PORT31CR */
PORTCR(32, 0xe6050020), /* PORT32CR */
PORTCR(33, 0xe6050021), /* PORT33CR */
PORTCR(34, 0xe6050022), /* PORT34CR */
PORTCR(35, 0xe6050023), /* PORT35CR */
PORTCR(36, 0xe6050024), /* PORT36CR */
PORTCR(37, 0xe6050025), /* PORT37CR */
PORTCR(38, 0xe6050026), /* PORT38CR */
PORTCR(39, 0xe6050027), /* PORT39CR */
PORTCR(40, 0xe6050028), /* PORT40CR */
PORTCR(41, 0xe6050029), /* PORT41CR */
PORTCR(42, 0xe605002a), /* PORT42CR */
PORTCR(43, 0xe605002b), /* PORT43CR */
PORTCR(44, 0xe605002c), /* PORT44CR */
PORTCR(45, 0xe605002d), /* PORT45CR */
PORTCR(46, 0xe605002e), /* PORT46CR */
PORTCR(47, 0xe605002f), /* PORT47CR */
PORTCR(48, 0xe6050030), /* PORT48CR */
PORTCR(49, 0xe6050031), /* PORT49CR */
PORTCR(50, 0xe6050032), /* PORT50CR */
PORTCR(51, 0xe6050033), /* PORT51CR */
PORTCR(52, 0xe6050034), /* PORT52CR */
PORTCR(53, 0xe6050035), /* PORT53CR */
PORTCR(54, 0xe6050036), /* PORT54CR */
PORTCR(55, 0xe6050037), /* PORT55CR */
PORTCR(56, 0xe6050038), /* PORT56CR */
PORTCR(57, 0xe6050039), /* PORT57CR */
PORTCR(58, 0xe605003a), /* PORT58CR */
PORTCR(59, 0xe605003b), /* PORT59CR */
PORTCR(60, 0xe605003c), /* PORT60CR */
PORTCR(61, 0xe605003d), /* PORT61CR */
PORTCR(62, 0xe605003e), /* PORT62CR */
PORTCR(63, 0xe605003f), /* PORT63CR */
PORTCR(64, 0xe6050040), /* PORT64CR */
PORTCR(65, 0xe6050041), /* PORT65CR */
PORTCR(66, 0xe6050042), /* PORT66CR */
PORTCR(67, 0xe6050043), /* PORT67CR */
PORTCR(68, 0xe6050044), /* PORT68CR */
PORTCR(69, 0xe6050045), /* PORT69CR */
PORTCR(70, 0xe6050046), /* PORT70CR */
PORTCR(71, 0xe6050047), /* PORT71CR */
PORTCR(72, 0xe6050048), /* PORT72CR */
PORTCR(73, 0xe6050049), /* PORT73CR */
PORTCR(74, 0xe605004a), /* PORT74CR */
PORTCR(75, 0xe605004b), /* PORT75CR */
PORTCR(76, 0xe605004c), /* PORT76CR */
PORTCR(77, 0xe605004d), /* PORT77CR */
PORTCR(78, 0xe605004e), /* PORT78CR */
PORTCR(79, 0xe605004f), /* PORT79CR */
PORTCR(80, 0xe6050050), /* PORT80CR */
PORTCR(81, 0xe6050051), /* PORT81CR */
PORTCR(82, 0xe6050052), /* PORT82CR */
PORTCR(83, 0xe6050053), /* PORT83CR */
PORTCR(84, 0xe6050054), /* PORT84CR */
PORTCR(85, 0xe6050055), /* PORT85CR */
PORTCR(86, 0xe6050056), /* PORT86CR */
PORTCR(87, 0xe6050057), /* PORT87CR */
PORTCR(88, 0xe6051058), /* PORT88CR */
PORTCR(89, 0xe6051059), /* PORT89CR */
PORTCR(90, 0xe605105a), /* PORT90CR */
PORTCR(91, 0xe605105b), /* PORT91CR */
PORTCR(92, 0xe605105c), /* PORT92CR */
PORTCR(93, 0xe605105d), /* PORT93CR */
PORTCR(94, 0xe605105e), /* PORT94CR */
PORTCR(95, 0xe605105f), /* PORT95CR */
PORTCR(96, 0xe6051060), /* PORT96CR */
PORTCR(97, 0xe6051061), /* PORT97CR */
PORTCR(98, 0xe6051062), /* PORT98CR */
PORTCR(99, 0xe6051063), /* PORT99CR */
PORTCR(100, 0xe6051064), /* PORT100CR */
PORTCR(101, 0xe6051065), /* PORT101CR */
PORTCR(102, 0xe6051066), /* PORT102CR */
PORTCR(103, 0xe6051067), /* PORT103CR */
PORTCR(104, 0xe6051068), /* PORT104CR */
PORTCR(105, 0xe6051069), /* PORT105CR */
PORTCR(106, 0xe605106a), /* PORT106CR */
PORTCR(107, 0xe605106b), /* PORT107CR */
PORTCR(108, 0xe605106c), /* PORT108CR */
PORTCR(109, 0xe605106d), /* PORT109CR */
PORTCR(110, 0xe605106e), /* PORT110CR */
PORTCR(111, 0xe605106f), /* PORT111CR */
PORTCR(112, 0xe6051070), /* PORT112CR */
PORTCR(113, 0xe6051071), /* PORT113CR */
PORTCR(114, 0xe6051072), /* PORT114CR */
PORTCR(115, 0xe6051073), /* PORT115CR */
PORTCR(116, 0xe6051074), /* PORT116CR */
PORTCR(117, 0xe6051075), /* PORT117CR */
PORTCR(118, 0xe6051076), /* PORT118CR */
PORTCR(119, 0xe6051077), /* PORT119CR */
PORTCR(120, 0xe6051078), /* PORT120CR */
PORTCR(121, 0xe6051079), /* PORT121CR */
PORTCR(122, 0xe605107a), /* PORT122CR */
PORTCR(123, 0xe605107b), /* PORT123CR */
PORTCR(124, 0xe605107c), /* PORT124CR */
PORTCR(125, 0xe605107d), /* PORT125CR */
PORTCR(126, 0xe605107e), /* PORT126CR */
PORTCR(127, 0xe605107f), /* PORT127CR */
PORTCR(128, 0xe6051080), /* PORT128CR */
PORTCR(129, 0xe6051081), /* PORT129CR */
PORTCR(130, 0xe6051082), /* PORT130CR */
PORTCR(131, 0xe6051083), /* PORT131CR */
PORTCR(132, 0xe6051084), /* PORT132CR */
PORTCR(133, 0xe6051085), /* PORT133CR */
PORTCR(134, 0xe6051086), /* PORT134CR */
PORTCR(135, 0xe6051087), /* PORT135CR */
PORTCR(136, 0xe6051088), /* PORT136CR */
PORTCR(137, 0xe6051089), /* PORT137CR */
PORTCR(138, 0xe605108a), /* PORT138CR */
PORTCR(139, 0xe605108b), /* PORT139CR */
PORTCR(140, 0xe605108c), /* PORT140CR */
PORTCR(141, 0xe605108d), /* PORT141CR */
PORTCR(142, 0xe605108e), /* PORT142CR */
PORTCR(143, 0xe605108f), /* PORT143CR */
PORTCR(144, 0xe6051090), /* PORT144CR */
PORTCR(145, 0xe6051091), /* PORT145CR */
PORTCR(146, 0xe6051092), /* PORT146CR */
PORTCR(147, 0xe6051093), /* PORT147CR */
PORTCR(148, 0xe6051094), /* PORT148CR */
PORTCR(149, 0xe6051095), /* PORT149CR */
PORTCR(150, 0xe6051096), /* PORT150CR */
PORTCR(151, 0xe6051097), /* PORT151CR */
PORTCR(152, 0xe6051098), /* PORT152CR */
PORTCR(153, 0xe6051099), /* PORT153CR */
PORTCR(154, 0xe605109a), /* PORT154CR */
PORTCR(155, 0xe605109b), /* PORT155CR */
PORTCR(156, 0xe605109c), /* PORT156CR */
PORTCR(157, 0xe605109d), /* PORT157CR */
PORTCR(158, 0xe605109e), /* PORT158CR */
PORTCR(159, 0xe605109f), /* PORT159CR */
PORTCR(160, 0xe60510a0), /* PORT160CR */
PORTCR(161, 0xe60510a1), /* PORT161CR */
PORTCR(162, 0xe60510a2), /* PORT162CR */
PORTCR(163, 0xe60510a3), /* PORT163CR */
PORTCR(164, 0xe60510a4), /* PORT164CR */
PORTCR(165, 0xe60510a5), /* PORT165CR */
PORTCR(166, 0xe60510a6), /* PORT166CR */
PORTCR(167, 0xe60510a7), /* PORT167CR */
PORTCR(168, 0xe60510a8), /* PORT168CR */
PORTCR(169, 0xe60510a9), /* PORT169CR */
PORTCR(170, 0xe60510aa), /* PORT170CR */
PORTCR(171, 0xe60510ab), /* PORT171CR */
PORTCR(172, 0xe60510ac), /* PORT172CR */
PORTCR(173, 0xe60510ad), /* PORT173CR */
PORTCR(174, 0xe60510ae), /* PORT174CR */
PORTCR(175, 0xe60520af), /* PORT175CR */
PORTCR(176, 0xe60520b0), /* PORT176CR */
PORTCR(177, 0xe60520b1), /* PORT177CR */
PORTCR(178, 0xe60520b2), /* PORT178CR */
PORTCR(179, 0xe60520b3), /* PORT179CR */
PORTCR(180, 0xe60520b4), /* PORT180CR */
PORTCR(181, 0xe60520b5), /* PORT181CR */
PORTCR(182, 0xe60520b6), /* PORT182CR */
PORTCR(183, 0xe60520b7), /* PORT183CR */
PORTCR(184, 0xe60520b8), /* PORT184CR */
PORTCR(185, 0xe60520b9), /* PORT185CR */
PORTCR(186, 0xe60520ba), /* PORT186CR */
PORTCR(187, 0xe60520bb), /* PORT187CR */
PORTCR(188, 0xe60520bc), /* PORT188CR */
PORTCR(189, 0xe60520bd), /* PORT189CR */
PORTCR(190, 0xe60520be), /* PORT190CR */
PORTCR(191, 0xe60520bf), /* PORT191CR */
PORTCR(192, 0xe60520c0), /* PORT192CR */
PORTCR(193, 0xe60520c1), /* PORT193CR */
PORTCR(194, 0xe60520c2), /* PORT194CR */
PORTCR(195, 0xe60520c3), /* PORT195CR */
PORTCR(196, 0xe60520c4), /* PORT196CR */
PORTCR(197, 0xe60520c5), /* PORT197CR */
PORTCR(198, 0xe60520c6), /* PORT198CR */
PORTCR(199, 0xe60520c7), /* PORT199CR */
PORTCR(200, 0xe60520c8), /* PORT200CR */
PORTCR(201, 0xe60520c9), /* PORT201CR */
PORTCR(202, 0xe60520ca), /* PORT202CR */
PORTCR(203, 0xe60520cb), /* PORT203CR */
PORTCR(204, 0xe60520cc), /* PORT204CR */
PORTCR(205, 0xe60520cd), /* PORT205CR */
PORTCR(206, 0xe60520ce), /* PORT206CR */
PORTCR(207, 0xe60520cf), /* PORT207CR */
PORTCR(208, 0xe60520d0), /* PORT208CR */
PORTCR(209, 0xe60520d1), /* PORT209CR */
PORTCR(210, 0xe60520d2), /* PORT210CR */
PORTCR(211, 0xe60520d3), /* PORT211CR */
PORTCR(212, 0xe60520d4), /* PORT212CR */
PORTCR(213, 0xe60520d5), /* PORT213CR */
PORTCR(214, 0xe60520d6), /* PORT214CR */
PORTCR(215, 0xe60520d7), /* PORT215CR */
PORTCR(216, 0xe60520d8), /* PORT216CR */
PORTCR(217, 0xe60520d9), /* PORT217CR */
PORTCR(218, 0xe60520da), /* PORT218CR */
PORTCR(219, 0xe60520db), /* PORT219CR */
PORTCR(220, 0xe60520dc), /* PORT220CR */
PORTCR(221, 0xe60520dd), /* PORT221CR */
PORTCR(222, 0xe60520de), /* PORT222CR */
PORTCR(223, 0xe60520df), /* PORT223CR */
PORTCR(224, 0xe60520e0), /* PORT224CR */
PORTCR(225, 0xe60520e1), /* PORT225CR */
PORTCR(226, 0xe60520e2), /* PORT226CR */
PORTCR(227, 0xe60520e3), /* PORT227CR */
PORTCR(228, 0xe60520e4), /* PORT228CR */
PORTCR(229, 0xe60520e5), /* PORT229CR */
PORTCR(230, 0xe60520e6), /* PORT230CR */
PORTCR(231, 0xe60520e7), /* PORT231CR */
PORTCR(232, 0xe60520e8), /* PORT232CR */
PORTCR(233, 0xe60520e9), /* PORT233CR */
PORTCR(234, 0xe60520ea), /* PORT234CR */
PORTCR(235, 0xe60520eb), /* PORT235CR */
PORTCR(236, 0xe60530ec), /* PORT236CR */
PORTCR(237, 0xe60530ed), /* PORT237CR */
PORTCR(238, 0xe60530ee), /* PORT238CR */
PORTCR(239, 0xe60530ef), /* PORT239CR */
PORTCR(240, 0xe60530f0), /* PORT240CR */
PORTCR(241, 0xe60530f1), /* PORT241CR */
PORTCR(242, 0xe60530f2), /* PORT242CR */
PORTCR(243, 0xe60530f3), /* PORT243CR */
PORTCR(244, 0xe60530f4), /* PORT244CR */
PORTCR(245, 0xe60530f5), /* PORT245CR */
PORTCR(246, 0xe60530f6), /* PORT246CR */
PORTCR(247, 0xe60530f7), /* PORT247CR */
PORTCR(248, 0xe60530f8), /* PORT248CR */
PORTCR(249, 0xe60530f9), /* PORT249CR */
PORTCR(250, 0xe60530fa), /* PORT250CR */
PORTCR(251, 0xe60530fb), /* PORT251CR */
PORTCR(252, 0xe60530fc), /* PORT252CR */
PORTCR(253, 0xe60530fd), /* PORT253CR */
PORTCR(254, 0xe60530fe), /* PORT254CR */
PORTCR(255, 0xe60530ff), /* PORT255CR */
PORTCR(256, 0xe6053100), /* PORT256CR */
PORTCR(257, 0xe6053101), /* PORT257CR */
PORTCR(258, 0xe6053102), /* PORT258CR */
PORTCR(259, 0xe6053103), /* PORT259CR */
PORTCR(260, 0xe6053104), /* PORT260CR */
PORTCR(261, 0xe6053105), /* PORT261CR */
PORTCR(262, 0xe6053106), /* PORT262CR */
PORTCR(263, 0xe6053107), /* PORT263CR */
PORTCR(264, 0xe6053108), /* PORT264CR */
PORTCR(265, 0xe6053109), /* PORT265CR */
PORTCR(266, 0xe605310a), /* PORT266CR */
PORTCR(267, 0xe605310b), /* PORT267CR */
PORTCR(268, 0xe605310c), /* PORT268CR */
PORTCR(269, 0xe605310d), /* PORT269CR */
PORTCR(270, 0xe605310e), /* PORT270CR */
PORTCR(271, 0xe605310f), /* PORT271CR */
PORTCR(272, 0xe6053110), /* PORT272CR */
{ PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
0, 0,
0, 0 }
},
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
},
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
},
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
},
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
},
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT272_DATA,
PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
},
{ },
};
static struct pinmux_info sh7367_pinmux_info = {
.name = "sh7367_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PORT0,
.last_gpio = GPIO_FN_DIVLOCK,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
void sh7367_pinmux_init(void)
{
register_pinmux(&sh7367_pinmux_info);
}
arch/arm/mach-shmobile/pfc-sh7377.c deleted 100644 → 0
View file @ 631a7b5d
/*
* sh7377 processor support - PFC hardware block
*
* Copyright (C) 2010 NISHIMOTO Hiroki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sh_pfc.h>
#include <mach/sh7377.h>
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
PORT_1(fn, pfx##118, sfx), \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
PORT_10(fn, pfx##15, sfx), \
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
PORT_1(fn, pfx##164, sfx), \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx), \
PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx), \
PORT_1(fn, pfx##264, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
/* Special Pull-up / Pull-down Functions */
PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK,
PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK,
PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK,
PORT72_KEYIN6_PU_MARK,
/* 55-1 */
VBUS_0_MARK,
CPORT0_MARK,
CPORT1_MARK,
CPORT2_MARK,
CPORT3_MARK,
CPORT4_MARK,
CPORT5_MARK,
CPORT6_MARK,
CPORT7_MARK,
CPORT8_MARK,
CPORT9_MARK,
CPORT10_MARK,
CPORT11_MARK, SIN2_MARK,
CPORT12_MARK, XCTS2_MARK,
CPORT13_MARK, RFSPO4_MARK,
CPORT14_MARK, RFSPO5_MARK,
CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK,
CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK,
CPORT17_IC_OE_MARK, SOUT2_MARK,
CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK,
CPORT19_MPORT1_MARK,
CPORT20_MARK, RFSPO6_MARK,
CPORT21_MARK, STATUS0_MARK,
CPORT22_MARK, STATUS1_MARK,
CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
B_SYNLD1_MARK,
B_SYNLD2_MARK, SYSENMSK_MARK,
XMAINPS_MARK,
XDIVPS_MARK,
XIDRST_MARK,
IDCLK_MARK, IC_DP_MARK,
IDIO_MARK, IC_DM_MARK,
SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK,
SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
XCTS1_MARK, SCIFA4_CTS_MARK,
PCMCLKO_MARK,
SYNC8KO_MARK,
/* 55-2 */
DNPCM_A_MARK,
UPPCM_A_MARK,
VACK_MARK,
XTALB1L_MARK,
GPS_AGC1_MARK, SCIFA0_RTS_MARK,
GPS_AGC4_MARK, SCIFA0_RXD_MARK,
GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK,
GPS_IM_MARK,
GPS_IS_MARK,
GPS_QM_MARK,
GPS_QS_MARK,
FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK,
FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK,
FMSIOLR_MARK,
FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK,
FMSIOBT_MARK,
FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK,
FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK,
FMSIILR_MARK,
FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK,
FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK,
A0_EA0_MARK, BS_MARK,
A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK,
A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK,
A14_EA14_MARK, PORT60_KEYOUT5_MARK,
A15_EA15_MARK, PORT61_KEYOUT4_MARK,
A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK,
A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK,
A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK,
A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK,
A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK,
A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK,
A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK,
A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK,
A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK,
A26_MARK, PORT72_KEYIN6_MARK,
D0_ED0_NAF0_MARK,
D1_ED1_NAF1_MARK,
D2_ED2_NAF2_MARK,
D3_ED3_NAF3_MARK,
D4_ED4_NAF4_MARK,
D5_ED5_NAF5_MARK,
D6_ED6_NAF6_MARK,
D7_ED7_NAF7_MARK,
D8_ED8_NAF8_MARK,
D9_ED9_NAF9_MARK,
D10_ED10_NAF10_MARK,
D11_ED11_NAF11_MARK,
D12_ED12_NAF12_MARK,
D13_ED13_NAF13_MARK,
D14_ED14_NAF14_MARK,
D15_ED15_NAF15_MARK,
CS4_MARK,
CS5A_MARK, FMSICK_MARK,
CS5B_MARK, FCE1_MARK,
/* 55-3 */
CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK,
FCE0_MARK,
WAIT_MARK, DREQ0_MARK,
RD_XRD_MARK,
WE0_XWR0_FWE_MARK,
WE1_XWR1_MARK,
FRB_MARK,
CKO_MARK,
NBRSTOUT_MARK,
NBRST_MARK,
GPS_EPPSIN_MARK,
LATCHPULSE_MARK,
LTESIGNAL_MARK,
LEGACYSTATE_MARK,
TCKON_MARK,
VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK,
VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK,
VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK,
VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK,
VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK,
VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK,
VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK,
VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK,
VIO_D6_MARK, PORT136_KEYIN2_MARK,
VIO_D7_MARK, PORT137_KEYIN3_MARK,
VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK,
VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK,
VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK,
VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK,
VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK,
VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK,
VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK,
VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK,
VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK,
VIO_FIELD_MARK, PORT147_KEYIN5_MARK,
VIO_CKO_MARK, PORT148_KEYIN6_MARK,
A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK,
MFG0_IN2_MARK,
TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK,
XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK,
/* 55-4 */
DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK,
PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK,
MFG3_IN2_MARK,
PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK,
MFG3_IN1_MARK,
PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK,
MFG3_OUT1_MARK, TPU3TO0_MARK,
LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK,
LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK,
BBIF2_TSYNC1_MARK,
LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK,
BBIF2_TSCK1_MARK,
LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK,
BBIF2_TXD1_MARK,
LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK,
LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK,
MFG2_OUT2_MARK,
TPU2TO1_MARK,
LCDD6_MARK, XWR2_MARK,
LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK,
LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK,
LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK,
LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK,
LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK,
LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK,
LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK,
LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK,
LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK,
VIO_DR7_MARK, D23_MARK, ED23_MARK,
LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK,
VIO_VDR_MARK, D24_MARK, ED24_MARK,
LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK,
LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK,
LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK,
LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK,
LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK,
LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK,
LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK,
LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK,
LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK,
LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK,
LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK,
LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK,
LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK,
LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK,
SCIFA1_TXD_MARK, OVCN2_MARK,
EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK,
SCIFA1_RTS_MARK, IDIN_MARK,
SCIFA1_RXD_MARK,
SCIFA1_CTS_MARK, MFG1_IN1_MARK,
MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK,
MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK,
MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK,
MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK,
PORT233_FSIACK_MARK,
MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK,
MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK,
MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK,
MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK,
MSIOF1_SS1_MARK, EDBGREQ3_MARK,
/* 55-5 */
MSIOF1_SS2_MARK,
SCIFA6_TXD_MARK,
PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK,
TPU4TO0_MARK,
PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK,
PORT244_MSIOF2_RXD_MARK,
PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK,
PORT245_MSIOF2_TXD_MARK,
PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK,
TPU1TO0_MARK,
PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK,
TPU3TO1_MARK,
PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK,
TPU2TO0_MARK,
PORT248_MSIOF2_TSCK_MARK,
PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK,
SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK,
SDHICD0_MARK,
SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK,
SDHID0_1_MARK, TDO2_SWO0_MC0_MARK,
SDHID0_2_MARK, TDI2_MARK,
SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK,
SDHICMD0_MARK, TRST2_MARK,
SDHIWP0_MARK, EDBGREQ2_MARK,
SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK,
SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK,
TMS3_SWDIO_MC1_MARK,
SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK,
SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK,
SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK,
SDHICMD1_MARK, TRST3_MARK,
RESETOUTS_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* 55-1 (GPIO) */
PORT_DATA_I_PD(0), PORT_DATA_I_PU(1),
PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
PORT_DATA_I_PU(4), PORT_DATA_I_PU(5),
PORT_DATA_I_PU(6), PORT_DATA_I_PU(7),
PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
PORT_DATA_I_PU(10), PORT_DATA_I_PU(11),
PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13),
PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
PORT_DATA_O(16), PORT_DATA_IO(17),
PORT_DATA_O(18), PORT_DATA_O(19),
PORT_DATA_O(20), PORT_DATA_O(21),
PORT_DATA_O(22), PORT_DATA_O(23),
PORT_DATA_O(24), PORT_DATA_I_PD(25),
PORT_DATA_I_PD(26), PORT_DATA_O(27),
PORT_DATA_O(28), PORT_DATA_O(29),
PORT_DATA_IO(30), PORT_DATA_IO_PU(31),
PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33),
PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35),
PORT_DATA_O(36), PORT_DATA_IO(37),
/* 55-2 (GPIO) */
PORT_DATA_O(38), PORT_DATA_I_PU(39),
PORT_DATA_I_PU_PD(40), PORT_DATA_O(41),
PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43),
PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45),
PORT_DATA_I_PD(46), PORT_DATA_I_PD(47),
PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49),
PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51),
PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53),
PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55),
PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57),
PORT_DATA_IO(58), PORT_DATA_IO(59),
PORT_DATA_IO(60), PORT_DATA_IO(61),
PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73),
PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75),
PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77),
PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79),
PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81),
PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83),
PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85),
PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87),
PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89),
PORT_DATA_O(90), PORT_DATA_IO_PU(91),
PORT_DATA_O(92),
/* 55-3 (GPIO) */
PORT_DATA_IO_PU(93),
PORT_DATA_O(94),
PORT_DATA_I_PU_PD(95),
PORT_DATA_IO(96), PORT_DATA_IO(97),
PORT_DATA_IO(98), PORT_DATA_I_PU(99),
PORT_DATA_O(100), PORT_DATA_O(101),
PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103),
PORT_DATA_I_PD(104), PORT_DATA_I_PD(105),
PORT_DATA_I_PD(106), PORT_DATA_I_PD(107),
PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109),
PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111),
PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115),
PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117),
PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128),
PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130),
PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132),
PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134),
PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136),
PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138),
PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140),
PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142),
PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144),
PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146),
PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148),
PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150),
PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152),
PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154),
PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156),
PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158),
/* 55-4 (GPIO) */
PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160),
PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162),
PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164),
PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193),
PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197),
PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199),
PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207),
PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209),
PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213),
PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215),
PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217),
PORT_DATA_O(218), PORT_DATA_IO_PD(219),
PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221),
PORT_DATA_IO_PU_PD(222),
PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224),
PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226),
PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228),
PORT_DATA_I_PD(229), PORT_DATA_IO(230),
PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232),
PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234),
PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236),
PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238),
/* 55-5 (GPIO) */
PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240),
PORT_DATA_O(241), PORT_DATA_I_PD(242),
PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244),
PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246),
PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248),
PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250),
PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252),
PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254),
PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256),
PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258),
PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260),
PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262),
PORT_DATA_IO_PU_PD(263),
/* Special Pull-up / Pull-down Functions */
PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT66_FN2, PORT66_IN_PU),
PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT67_FN2, PORT67_IN_PU),
PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT68_FN2, PORT68_IN_PU),
PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT69_FN2, PORT69_IN_PU),
PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT70_FN2, PORT70_IN_PU),
PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT71_FN2, PORT71_IN_PU),
PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
PORT72_FN2, PORT72_IN_PU),
/* 55-1 (FN) */
PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
PINMUX_DATA(SIN2_MARK, PORT12_FN2),
PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2),
PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3),
PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3),
PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1),
PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
PINMUX_DATA(XRTS2_MARK, PORT19_FN2),
PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1),
PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1),
PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1),
PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2),
PINMUX_DATA(XMAINPS_MARK, PORT27_FN1),
PINMUX_DATA(XDIVPS_MARK, PORT28_FN1),
PINMUX_DATA(XIDRST_MARK, PORT29_FN1),
PINMUX_DATA(IDCLK_MARK, PORT30_FN1),
PINMUX_DATA(IC_DP_MARK, PORT30_FN2),
PINMUX_DATA(IDIO_MARK, PORT31_FN1),
PINMUX_DATA(IC_DM_MARK, PORT31_FN2),
PINMUX_DATA(SOUT1_MARK, PORT32_FN1),
PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3),
PINMUX_DATA(SIN1_MARK, PORT33_FN1),
PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2),
PINMUX_DATA(XWUP_MARK, PORT33_FN3),
PINMUX_DATA(XRTS1_MARK, PORT34_FN1),
PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2),
PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3),
PINMUX_DATA(XCTS1_MARK, PORT35_FN1),
PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2),
PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1),
PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1),
/* 55-2 (FN) */
PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1),
PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1),
PINMUX_DATA(VACK_MARK, PORT40_FN1),
PINMUX_DATA(XTALB1L_MARK, PORT41_FN1),
PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1),
PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2),
PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1),
PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1),
PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2),
PINMUX_DATA(GPS_IM_MARK, PORT45_FN1),
PINMUX_DATA(GPS_IS_MARK, PORT46_FN1),
PINMUX_DATA(GPS_QM_MARK, PORT47_FN1),
PINMUX_DATA(GPS_QS_MARK, PORT48_FN1),
PINMUX_DATA(FMSOCK_MARK, PORT49_FN1),
PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2),
PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3),
PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1),
PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2),
PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3),
PINMUX_DATA(IPORT3_MARK, PORT50_FN4),
PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5),
PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1),
PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2),
PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3),
PINMUX_DATA(OPORT1_MARK, PORT51_FN4),
PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5),
PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1),
PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
PINMUX_DATA(OPORT2_MARK, PORT52_FN3),
PINMUX_DATA(FMSOILR_MARK, PORT53_FN1),
PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2),
PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3),
PINMUX_DATA(OPORT3_MARK, PORT53_FN4),
PINMUX_DATA(FMSIILR_MARK, PORT53_FN5),
PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1),
PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2),
PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3),
PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4),
PINMUX_DATA(FMSISLD_MARK, PORT55_FN1),
PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2),
PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
PINMUX_DATA(A0_EA0_MARK, PORT57_FN1),
PINMUX_DATA(BS_MARK, PORT57_FN2),
PINMUX_DATA(A12_EA12_MARK, PORT58_FN1),
PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2),
PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3),
PINMUX_DATA(A13_EA13_MARK, PORT59_FN1),
PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2),
PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3),
PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
PINMUX_DATA(A14_EA14_MARK, PORT60_FN1),
PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2),
PINMUX_DATA(A15_EA15_MARK, PORT61_FN1),
PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2),
PINMUX_DATA(A16_EA16_MARK, PORT62_FN1),
PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2),
PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3),
PINMUX_DATA(A17_EA17_MARK, PORT63_FN1),
PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2),
PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3),
PINMUX_DATA(A18_EA18_MARK, PORT64_FN1),
PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2),
PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3),
PINMUX_DATA(A19_EA19_MARK, PORT65_FN1),
PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2),
PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3),
PINMUX_DATA(A20_EA20_MARK, PORT66_FN1),
PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2),
PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3),
PINMUX_DATA(A21_EA21_MARK, PORT67_FN1),
PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2),
PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3),
PINMUX_DATA(A22_EA22_MARK, PORT68_FN1),
PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2),
PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3),
PINMUX_DATA(A23_EA23_MARK, PORT69_FN1),
PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2),
PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3),
PINMUX_DATA(A24_EA24_MARK, PORT70_FN1),
PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2),
PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3),
PINMUX_DATA(A25_EA25_MARK, PORT71_FN1),
PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2),
PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3),
PINMUX_DATA(A26_MARK, PORT72_FN1),
PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2),
PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1),
PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1),
PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1),
PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1),
PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1),
PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1),
PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1),
PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1),
PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1),
PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1),
PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1),
PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1),
PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1),
PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1),
PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1),
PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1),
PINMUX_DATA(CS4_MARK, PORT90_FN1),
PINMUX_DATA(CS5A_MARK, PORT91_FN1),
PINMUX_DATA(FMSICK_MARK, PORT91_FN2),
PINMUX_DATA(CS5B_MARK, PORT92_FN1),
PINMUX_DATA(FCE1_MARK, PORT92_FN2),
/* 55-3 (FN) */
PINMUX_DATA(CS6B_MARK, PORT93_FN1),
PINMUX_DATA(XCS2_MARK, PORT93_FN2),
PINMUX_DATA(CS6A_MARK, PORT93_FN3),
PINMUX_DATA(DACK0_MARK, PORT93_FN4),
PINMUX_DATA(FCE0_MARK, PORT94_FN1),
PINMUX_DATA(WAIT_MARK, PORT95_FN1),
PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
PINMUX_DATA(RD_XRD_MARK, PORT96_FN1),
PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1),
PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1),
PINMUX_DATA(FRB_MARK, PORT99_FN1),
PINMUX_DATA(CKO_MARK, PORT100_FN1),
PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1),
PINMUX_DATA(NBRST_MARK, PORT102_FN1),
PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1),
PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1),
PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1),
PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1),
PINMUX_DATA(TCKON_MARK, PORT118_FN1),
PINMUX_DATA(VIO_VD_MARK, PORT128_FN1),
PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2),
PINMUX_DATA(IPORT0_MARK, PORT128_FN3),
PINMUX_DATA(VIO_HD_MARK, PORT129_FN1),
PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2),
PINMUX_DATA(IPORT1_MARK, PORT129_FN3),
PINMUX_DATA(VIO_D0_MARK, PORT130_FN1),
PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2),
PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3),
PINMUX_DATA(VIO_D1_MARK, PORT131_FN1),
PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2),
PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3),
PINMUX_DATA(VIO_D2_MARK, PORT132_FN1),
PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2),
PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3),
PINMUX_DATA(VIO_D3_MARK, PORT133_FN1),
PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2),
PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3),
PINMUX_DATA(VIO_D4_MARK, PORT134_FN1),
PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2),
PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3),
PINMUX_DATA(VIO_D5_MARK, PORT135_FN1),
PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2),
PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3),
PINMUX_DATA(VIO_D6_MARK, PORT136_FN1),
PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2),
PINMUX_DATA(VIO_D7_MARK, PORT137_FN1),
PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2),
PINMUX_DATA(VIO_D8_MARK, PORT138_FN1),
PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2),
PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3),
PINMUX_DATA(VIO_D9_MARK, PORT139_FN1),
PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2),
PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3),
PINMUX_DATA(VIO_D10_MARK, PORT140_FN1),
PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2),
PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3),
PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4),
PINMUX_DATA(VIO_D11_MARK, PORT141_FN1),
PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2),
PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3),
PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4),
PINMUX_DATA(VIO_D12_MARK, PORT142_FN1),
PINMUX_DATA(M13_BSW_MARK, PORT142_FN2),
PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3),
PINMUX_DATA(VIO_D13_MARK, PORT143_FN1),
PINMUX_DATA(M14_GSW_MARK, PORT143_FN2),
PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3),
PINMUX_DATA(VIO_D14_MARK, PORT144_FN1),
PINMUX_DATA(M15_RSW_MARK, PORT144_FN2),
PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3),
PINMUX_DATA(VIO_D15_MARK, PORT145_FN1),
PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2),
PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3),
PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1),
PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2),
PINMUX_DATA(IPORT2_MARK, PORT146_FN3),
PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1),
PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2),
PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2),
PINMUX_DATA(A27_MARK, PORT149_FN1),
PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2),
PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3),
PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1),
PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1),
PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2),
PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1),
PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2),
PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1),
PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2),
PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3),
PINMUX_DATA(SOUT3_MARK, PORT154_FN1),
PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2),
PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3),
PINMUX_DATA(SIN3_MARK, PORT155_FN1),
PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2),
PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3),
PINMUX_DATA(XRTS3_MARK, PORT156_FN1),
PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2),
PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3),
PINMUX_DATA(XCTS3_MARK, PORT157_FN1),
PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2),
PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3),
/* 55-4 (FN) */
PINMUX_DATA(DINT_MARK, PORT158_FN1),
PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2),
PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3),
PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1),
PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2),
PINMUX_DATA(NMI_MARK, PORT159_FN3),
PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1),
PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2),
PINMUX_DATA(SOUT0_MARK, PORT160_FN3),
PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1),
PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2),
PINMUX_DATA(XCTS0_MARK, PORT161_FN3),
PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4),
PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1),
PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2),
PINMUX_DATA(SIN0_MARK, PORT162_FN3),
PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4),
PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1),
PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2),
PINMUX_DATA(XRTS0_MARK, PORT163_FN3),
PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4),
PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2),
PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3),
PINMUX_DATA(LCDD1_MARK, PORT193_FN1),
PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2),
PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3),
PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4),
PINMUX_DATA(LCDD2_MARK, PORT194_FN1),
PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2),
PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3),
PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4),
PINMUX_DATA(LCDD3_MARK, PORT195_FN1),
PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2),
PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3),
PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4),
PINMUX_DATA(LCDD4_MARK, PORT196_FN1),
PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2),
PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3),
PINMUX_DATA(LCDD5_MARK, PORT197_FN1),
PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2),
PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3),
PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4),
PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
PINMUX_DATA(LCDD7_MARK, PORT199_FN1),
PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2),
PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3),
PINMUX_DATA(LCDD8_MARK, PORT200_FN1),
PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2),
PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3),
PINMUX_DATA(D16_MARK, PORT200_FN4),
PINMUX_DATA(LCDD9_MARK, PORT201_FN1),
PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2),
PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3),
PINMUX_DATA(D17_MARK, PORT201_FN4),
PINMUX_DATA(LCDD10_MARK, PORT202_FN1),
PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2),
PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3),
PINMUX_DATA(D18_MARK, PORT202_FN4),
PINMUX_DATA(LCDD11_MARK, PORT203_FN1),
PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2),
PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3),
PINMUX_DATA(D19_MARK, PORT203_FN4),
PINMUX_DATA(LCDD12_MARK, PORT204_FN1),
PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2),
PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3),
PINMUX_DATA(D20_MARK, PORT204_FN4),
PINMUX_DATA(LCDD13_MARK, PORT205_FN1),
PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2),
PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3),
PINMUX_DATA(D21_MARK, PORT205_FN4),
PINMUX_DATA(LCDD14_MARK, PORT206_FN1),
PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2),
PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3),
PINMUX_DATA(D22_MARK, PORT206_FN4),
PINMUX_DATA(LCDD15_MARK, PORT207_FN1),
PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2),
PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3),
PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4),
PINMUX_DATA(D23_MARK, PORT207_FN5),
PINMUX_DATA(LCDD16_MARK, PORT208_FN1),
PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2),
PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3),
PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4),
PINMUX_DATA(D24_MARK, PORT208_FN5),
PINMUX_DATA(LCDD17_MARK, PORT209_FN1),
PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2),
PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3),
PINMUX_DATA(D25_MARK, PORT209_FN4),
PINMUX_DATA(LCDD18_MARK, PORT210_FN1),
PINMUX_DATA(DREQ2_MARK, PORT210_FN2),
PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3),
PINMUX_DATA(D26_MARK, PORT210_FN4),
PINMUX_DATA(LCDD19_MARK, PORT211_FN1),
PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2),
PINMUX_DATA(D27_MARK, PORT211_FN3),
PINMUX_DATA(LCDD20_MARK, PORT212_FN1),
PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2),
PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3),
PINMUX_DATA(D28_MARK, PORT212_FN4),
PINMUX_DATA(LCDD21_MARK, PORT213_FN1),
PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2),
PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3),
PINMUX_DATA(D29_MARK, PORT213_FN4),
PINMUX_DATA(LCDD22_MARK, PORT214_FN1),
PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2),
PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3),
PINMUX_DATA(D30_MARK, PORT214_FN4),
PINMUX_DATA(LCDD23_MARK, PORT215_FN1),
PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2),
PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3),
PINMUX_DATA(D31_MARK, PORT215_FN4),
PINMUX_DATA(LCDDCK_MARK, PORT216_FN1),
PINMUX_DATA(LCDWR_MARK, PORT216_FN2),
PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3),
PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4),
PINMUX_DATA(LCDRD_MARK, PORT217_FN1),
PINMUX_DATA(DACK2_MARK, PORT217_FN2),
PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3),
PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1),
PINMUX_DATA(LCDCS_MARK, PORT218_FN2),
PINMUX_DATA(LCDCS2_MARK, PORT218_FN3),
PINMUX_DATA(DACK3_MARK, PORT218_FN4),
PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6),
PINMUX_DATA(LCDDISP_MARK, PORT219_FN1),
PINMUX_DATA(LCDRS_MARK, PORT219_FN2),
PINMUX_DATA(DREQ3_MARK, PORT219_FN3),
PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4),
PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1),
PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3),
PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1),
PINMUX_DATA(DREQ1_MARK, PORT221_FN2),
PINMUX_DATA(PWEN_MARK, PORT221_FN3),
PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4),
PINMUX_DATA(LCDDON_MARK, PORT222_FN1),
PINMUX_DATA(LCDDON2_MARK, PORT222_FN2),
PINMUX_DATA(DACK1_MARK, PORT222_FN3),
PINMUX_DATA(OVCN_MARK, PORT222_FN4),
PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5),
PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1),
PINMUX_DATA(OVCN2_MARK, PORT225_FN2),
PINMUX_DATA(EXTLP_MARK, PORT226_FN1),
PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2),
PINMUX_DATA(USBTERM_MARK, PORT226_FN3),
PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4),
PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1),
PINMUX_DATA(IDIN_MARK, PORT227_FN2),
PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1),
PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1),
PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2),
PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1),
PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2),
PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3),
PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1),
PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2),
PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3),
PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1),
PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2),
PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3),
PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1),
PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2),
PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3),
PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4),
PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1),
PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2),
PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3),
PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1),
PINMUX_DATA(OPORT0_MARK, PORT235_FN2),
PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3),
PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4),
PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1),
PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2),
PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3),
PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1),
PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2),
PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3),
PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1),
PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2),
/* 55-5 (FN) */
PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1),
PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1),
PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2),
PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3),
PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1),
PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2),
PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1),
PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1),
PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2),
PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3),
PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1),
PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2),
PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3),
PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1),
PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2),
PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3),
PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1),
PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2),
PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3),
PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1),
PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2),
PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3),
PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4),
PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1),
PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2),
PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2),
PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2),
PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2),
PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
PINMUX_DATA(TDI2_MARK, PORT254_FN2),
PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2),
PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
PINMUX_DATA(TRST2_MARK, PORT256_FN2),
PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2),
PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2),
PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1),
PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2),
PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4),
PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1),
PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2),
PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4),
PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1),
PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2),
PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
PINMUX_DATA(TDI3_MARK, PORT261_FN4),
PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1),
PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2),
PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4),
PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
PINMUX_DATA(TRST3_MARK, PORT263_FN2),
PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
};
static struct pinmux_gpio pinmux_gpios[] = {
/* 55-1 -> 55-5 (GPIO) */
GPIO_PORT_ALL(),
/* Special Pull-up / Pull-down Functions */
GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU),
GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU),
GPIO_FN(PORT72_KEYIN6_PU),
/* 55-1 (FN) */
GPIO_FN(VBUS_0),
GPIO_FN(CPORT0),
GPIO_FN(CPORT1),
GPIO_FN(CPORT2),
GPIO_FN(CPORT3),
GPIO_FN(CPORT4),
GPIO_FN(CPORT5),
GPIO_FN(CPORT6),
GPIO_FN(CPORT7),
GPIO_FN(CPORT8),
GPIO_FN(CPORT9),
GPIO_FN(CPORT10),
GPIO_FN(CPORT11), GPIO_FN(SIN2),
GPIO_FN(CPORT12), GPIO_FN(XCTS2),
GPIO_FN(CPORT13), GPIO_FN(RFSPO4),
GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2),
GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3),
GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2),
GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2),
GPIO_FN(CPORT19_MPORT1),
GPIO_FN(CPORT20), GPIO_FN(RFSPO6),
GPIO_FN(CPORT21), GPIO_FN(STATUS0),
GPIO_FN(CPORT22), GPIO_FN(STATUS1),
GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
GPIO_FN(B_SYNLD1),
GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK),
GPIO_FN(XMAINPS),
GPIO_FN(XDIVPS),
GPIO_FN(XIDRST),
GPIO_FN(IDCLK), GPIO_FN(IC_DP),
GPIO_FN(IDIO), GPIO_FN(IC_DM),
GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT),
GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
GPIO_FN(PCMCLKO),
GPIO_FN(SYNC8KO),
/* 55-2 (FN) */
GPIO_FN(DNPCM_A),
GPIO_FN(UPPCM_A),
GPIO_FN(VACK),
GPIO_FN(XTALB1L),
GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS),
GPIO_FN(GPS_IM),
GPIO_FN(GPS_IS),
GPIO_FN(GPS_QM),
GPIO_FN(GPS_QS),
GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT),
GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2),
GPIO_FN(IPORT3), GPIO_FN(FMSIOLR),
GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3),
GPIO_FN(OPORT1), GPIO_FN(FMSIOBT),
GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2),
GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3),
GPIO_FN(OPORT3), GPIO_FN(FMSIILR),
GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2),
GPIO_FN(FMSIIBT),
GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0),
GPIO_FN(A0_EA0), GPIO_FN(BS),
GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2),
GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2),
GPIO_FN(TPU0TO1),
GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5),
GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4),
GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1),
GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC),
GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK),
GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD),
GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK),
GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC),
GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0),
GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1),
GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD),
GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2),
GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6),
GPIO_FN(D0_ED0_NAF0),
GPIO_FN(D1_ED1_NAF1),
GPIO_FN(D2_ED2_NAF2),
GPIO_FN(D3_ED3_NAF3),
GPIO_FN(D4_ED4_NAF4),
GPIO_FN(D5_ED5_NAF5),
GPIO_FN(D6_ED6_NAF6),
GPIO_FN(D7_ED7_NAF7),
GPIO_FN(D8_ED8_NAF8),
GPIO_FN(D9_ED9_NAF9),
GPIO_FN(D10_ED10_NAF10),
GPIO_FN(D11_ED11_NAF11),
GPIO_FN(D12_ED12_NAF12),
GPIO_FN(D13_ED13_NAF13),
GPIO_FN(D14_ED14_NAF14),
GPIO_FN(D15_ED15_NAF15),
GPIO_FN(CS4),
GPIO_FN(CS5A), GPIO_FN(FMSICK),
/* 55-3 (FN) */
GPIO_FN(CS5B), GPIO_FN(FCE1),
GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0),
GPIO_FN(FCE0),
GPIO_FN(WAIT), GPIO_FN(DREQ0),
GPIO_FN(RD_XRD),
GPIO_FN(WE0_XWR0_FWE),
GPIO_FN(WE1_XWR1),
GPIO_FN(FRB),
GPIO_FN(CKO),
GPIO_FN(NBRSTOUT),
GPIO_FN(NBRST),
GPIO_FN(GPS_EPPSIN),
GPIO_FN(LATCHPULSE),
GPIO_FN(LTESIGNAL),
GPIO_FN(LEGACYSTATE),
GPIO_FN(TCKON),
GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0),
GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1),
GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD),
GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1),
GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2),
GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5),
GPIO_FN(PORT133_MSIOF2_TSYNC),
GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD),
GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK),
GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2),
GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3),
GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC),
GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR),
GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2),
GPIO_FN(PORT140_FSIAOBT),
GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3),
GPIO_FN(PORT141_FSIAOSLD),
GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK),
GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR),
GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT),
GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD),
GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2),
GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5),
GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6),
GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1),
GPIO_FN(MFG0_IN2),
GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK),
GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC),
GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1),
GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0),
GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1),
GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2),
GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD),
/* 55-4 (FN) */
GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI),
GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0),
GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0),
GPIO_FN(MFG3_IN2),
GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0),
GPIO_FN(MFG3_IN1),
GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0),
GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0),
GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI),
GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS),
GPIO_FN(BBIF2_TSYNC1),
GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS),
GPIO_FN(BBIF2_TSCK1),
GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD),
GPIO_FN(BBIF2_TXD1),
GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD),
GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK),
GPIO_FN(MFG2_OUT2),
GPIO_FN(LCDD6),
GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2),
GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0),
GPIO_FN(D16),
GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1),
GPIO_FN(D17),
GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2),
GPIO_FN(D18),
GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3),
GPIO_FN(D19),
GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4),
GPIO_FN(D20),
GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5),
GPIO_FN(D21),
GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6),
GPIO_FN(D22),
GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0),
GPIO_FN(VIO_DR7), GPIO_FN(D23),
GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1),
GPIO_FN(VIO_VDR), GPIO_FN(D24),
GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR),
GPIO_FN(D25),
GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1),
GPIO_FN(D26),
GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27),
GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
GPIO_FN(D28),
GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
GPIO_FN(D29),
GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK),
GPIO_FN(D30),
GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC),
GPIO_FN(D31),
GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3),
GPIO_FN(VIO_CLKR),
GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC),
GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4),
GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK),
GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5),
GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD),
GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN),
GPIO_FN(MSIOF0L_TXD),
GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2),
GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM),
GPIO_FN(PORT226_VIO_CKO2),
GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN),
GPIO_FN(SCIFA1_RXD),
GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1),
GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC),
GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR),
GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT),
GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG),
GPIO_FN(PORT233_FSIACK),
GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD),
GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2),
GPIO_FN(PORT235_FSIAILR),
GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT),
GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD),
GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
/* 55-5 (FN) */
GPIO_FN(MSIOF1_SS2),
GPIO_FN(SCIFA6_TXD),
GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1),
GPIO_FN(TPU4TO0),
GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2),
GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2),
GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1),
GPIO_FN(PORT244_SCIFB_CTS),
GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2),
GPIO_FN(PORT245_SCIFB_RTS),
GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1),
GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0),
GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2),
GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1),
GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1),
GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0),
GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1),
GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0),
GPIO_FN(SDHICD0),
GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0),
GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0),
GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0),
GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1),
GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2),
GPIO_FN(TMS3_SWDIO_MC1),
GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2),
GPIO_FN(TDO3_SWO0_MC1),
GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2),
GPIO_FN(TDI3),
GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2),
GPIO_FN(RTCK3_SWO1_MC1),
GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
GPIO_FN(RESETOUTS),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
PORTCR(3, 0xe6050003), /* PORT3CR */
PORTCR(4, 0xe6050004), /* PORT4CR */
PORTCR(5, 0xe6050005), /* PORT5CR */
PORTCR(6, 0xe6050006), /* PORT6CR */
PORTCR(7, 0xe6050007), /* PORT7CR */
PORTCR(8, 0xe6050008), /* PORT8CR */
PORTCR(9, 0xe6050009), /* PORT9CR */
PORTCR(10, 0xe605000a), /* PORT10CR */
PORTCR(11, 0xe605000b), /* PORT11CR */
PORTCR(12, 0xe605000c), /* PORT12CR */
PORTCR(13, 0xe605000d), /* PORT13CR */
PORTCR(14, 0xe605000e), /* PORT14CR */
PORTCR(15, 0xe605000f), /* PORT15CR */
PORTCR(16, 0xe6050010), /* PORT16CR */
PORTCR(17, 0xe6050011), /* PORT17CR */
PORTCR(18, 0xe6050012), /* PORT18CR */
PORTCR(19, 0xe6050013), /* PORT19CR */
PORTCR(20, 0xe6050014), /* PORT20CR */
PORTCR(21, 0xe6050015), /* PORT21CR */
PORTCR(22, 0xe6050016), /* PORT22CR */
PORTCR(23, 0xe6050017), /* PORT23CR */
PORTCR(24, 0xe6050018), /* PORT24CR */
PORTCR(25, 0xe6050019), /* PORT25CR */
PORTCR(26, 0xe605001a), /* PORT26CR */
PORTCR(27, 0xe605001b), /* PORT27CR */
PORTCR(28, 0xe605001c), /* PORT28CR */
PORTCR(29, 0xe605001d), /* PORT29CR */
PORTCR(30, 0xe605001e), /* PORT30CR */
PORTCR(31, 0xe605001f), /* PORT31CR */
PORTCR(32, 0xe6050020), /* PORT32CR */
PORTCR(33, 0xe6050021), /* PORT33CR */
PORTCR(34, 0xe6050022), /* PORT34CR */
PORTCR(35, 0xe6050023), /* PORT35CR */
PORTCR(36, 0xe6050024), /* PORT36CR */
PORTCR(37, 0xe6050025), /* PORT37CR */
PORTCR(38, 0xe6050026), /* PORT38CR */
PORTCR(39, 0xe6050027), /* PORT39CR */
PORTCR(40, 0xe6050028), /* PORT40CR */
PORTCR(41, 0xe6050029), /* PORT41CR */
PORTCR(42, 0xe605002a), /* PORT42CR */
PORTCR(43, 0xe605002b), /* PORT43CR */
PORTCR(44, 0xe605002c), /* PORT44CR */
PORTCR(45, 0xe605002d), /* PORT45CR */
PORTCR(46, 0xe605002e), /* PORT46CR */
PORTCR(47, 0xe605002f), /* PORT47CR */
PORTCR(48, 0xe6050030), /* PORT48CR */
PORTCR(49, 0xe6050031), /* PORT49CR */
PORTCR(50, 0xe6050032), /* PORT50CR */
PORTCR(51, 0xe6050033), /* PORT51CR */
PORTCR(52, 0xe6050034), /* PORT52CR */
PORTCR(53, 0xe6050035), /* PORT53CR */
PORTCR(54, 0xe6050036), /* PORT54CR */
PORTCR(55, 0xe6050037), /* PORT55CR */
PORTCR(56, 0xe6050038), /* PORT56CR */
PORTCR(57, 0xe6050039), /* PORT57CR */
PORTCR(58, 0xe605003a), /* PORT58CR */
PORTCR(59, 0xe605003b), /* PORT59CR */
PORTCR(60, 0xe605003c), /* PORT60CR */
PORTCR(61, 0xe605003d), /* PORT61CR */
PORTCR(62, 0xe605003e), /* PORT62CR */
PORTCR(63, 0xe605003f), /* PORT63CR */
PORTCR(64, 0xe6050040), /* PORT64CR */
PORTCR(65, 0xe6050041), /* PORT65CR */
PORTCR(66, 0xe6050042), /* PORT66CR */
PORTCR(67, 0xe6050043), /* PORT67CR */
PORTCR(68, 0xe6050044), /* PORT68CR */
PORTCR(69, 0xe6050045), /* PORT69CR */
PORTCR(70, 0xe6050046), /* PORT70CR */
PORTCR(71, 0xe6050047), /* PORT71CR */
PORTCR(72, 0xe6050048), /* PORT72CR */
PORTCR(73, 0xe6050049), /* PORT73CR */
PORTCR(74, 0xe605004a), /* PORT74CR */
PORTCR(75, 0xe605004b), /* PORT75CR */
PORTCR(76, 0xe605004c), /* PORT76CR */
PORTCR(77, 0xe605004d), /* PORT77CR */
PORTCR(78, 0xe605004e), /* PORT78CR */
PORTCR(79, 0xe605004f), /* PORT79CR */
PORTCR(80, 0xe6050050), /* PORT80CR */
PORTCR(81, 0xe6050051), /* PORT81CR */
PORTCR(82, 0xe6050052), /* PORT82CR */
PORTCR(83, 0xe6050053), /* PORT83CR */
PORTCR(84, 0xe6050054), /* PORT84CR */
PORTCR(85, 0xe6050055), /* PORT85CR */
PORTCR(86, 0xe6050056), /* PORT86CR */
PORTCR(87, 0xe6050057), /* PORT87CR */
PORTCR(88, 0xe6050058), /* PORT88CR */
PORTCR(89, 0xe6050059), /* PORT89CR */
PORTCR(90, 0xe605005a), /* PORT90CR */
PORTCR(91, 0xe605005b), /* PORT91CR */
PORTCR(92, 0xe605005c), /* PORT92CR */
PORTCR(93, 0xe605005d), /* PORT93CR */
PORTCR(94, 0xe605005e), /* PORT94CR */
PORTCR(95, 0xe605005f), /* PORT95CR */
PORTCR(96, 0xe6050060), /* PORT96CR */
PORTCR(97, 0xe6050061), /* PORT97CR */
PORTCR(98, 0xe6050062), /* PORT98CR */
PORTCR(99, 0xe6050063), /* PORT99CR */
PORTCR(100, 0xe6050064), /* PORT100CR */
PORTCR(101, 0xe6050065), /* PORT101CR */
PORTCR(102, 0xe6050066), /* PORT102CR */
PORTCR(103, 0xe6050067), /* PORT103CR */
PORTCR(104, 0xe6050068), /* PORT104CR */
PORTCR(105, 0xe6050069), /* PORT105CR */
PORTCR(106, 0xe605006a), /* PORT106CR */
PORTCR(107, 0xe605006b), /* PORT107CR */
PORTCR(108, 0xe605006c), /* PORT108CR */
PORTCR(109, 0xe605006d), /* PORT109CR */
PORTCR(110, 0xe605006e), /* PORT110CR */
PORTCR(111, 0xe605006f), /* PORT111CR */
PORTCR(112, 0xe6050070), /* PORT112CR */
PORTCR(113, 0xe6050071), /* PORT113CR */
PORTCR(114, 0xe6050072), /* PORT114CR */
PORTCR(115, 0xe6050073), /* PORT115CR */
PORTCR(116, 0xe6050074), /* PORT116CR */
PORTCR(117, 0xe6050075), /* PORT117CR */
PORTCR(118, 0xe6050076), /* PORT118CR */
PORTCR(128, 0xe6051080), /* PORT128CR */
PORTCR(129, 0xe6051081), /* PORT129CR */
PORTCR(130, 0xe6051082), /* PORT130CR */
PORTCR(131, 0xe6051083), /* PORT131CR */
PORTCR(132, 0xe6051084), /* PORT132CR */
PORTCR(133, 0xe6051085), /* PORT133CR */
PORTCR(134, 0xe6051086), /* PORT134CR */
PORTCR(135, 0xe6051087), /* PORT135CR */
PORTCR(136, 0xe6051088), /* PORT136CR */
PORTCR(137, 0xe6051089), /* PORT137CR */
PORTCR(138, 0xe605108a), /* PORT138CR */
PORTCR(139, 0xe605108b), /* PORT139CR */
PORTCR(140, 0xe605108c), /* PORT140CR */
PORTCR(141, 0xe605108d), /* PORT141CR */
PORTCR(142, 0xe605108e), /* PORT142CR */
PORTCR(143, 0xe605108f), /* PORT143CR */
PORTCR(144, 0xe6051090), /* PORT144CR */
PORTCR(145, 0xe6051091), /* PORT145CR */
PORTCR(146, 0xe6051092), /* PORT146CR */
PORTCR(147, 0xe6051093), /* PORT147CR */
PORTCR(148, 0xe6051094), /* PORT148CR */
PORTCR(149, 0xe6051095), /* PORT149CR */
PORTCR(150, 0xe6051096), /* PORT150CR */
PORTCR(151, 0xe6051097), /* PORT151CR */
PORTCR(152, 0xe6051098), /* PORT152CR */
PORTCR(153, 0xe6051099), /* PORT153CR */
PORTCR(154, 0xe605109a), /* PORT154CR */
PORTCR(155, 0xe605109b), /* PORT155CR */
PORTCR(156, 0xe605109c), /* PORT156CR */
PORTCR(157, 0xe605109d), /* PORT157CR */
PORTCR(158, 0xe605109e), /* PORT158CR */
PORTCR(159, 0xe605109f), /* PORT159CR */
PORTCR(160, 0xe60510a0), /* PORT160CR */
PORTCR(161, 0xe60510a1), /* PORT161CR */
PORTCR(162, 0xe60510a2), /* PORT162CR */
PORTCR(163, 0xe60510a3), /* PORT163CR */
PORTCR(164, 0xe60510a4), /* PORT164CR */
PORTCR(192, 0xe60520c0), /* PORT192CR */
PORTCR(193, 0xe60520c1), /* PORT193CR */
PORTCR(194, 0xe60520c2), /* PORT194CR */
PORTCR(195, 0xe60520c3), /* PORT195CR */
PORTCR(196, 0xe60520c4), /* PORT196CR */
PORTCR(197, 0xe60520c5), /* PORT197CR */
PORTCR(198, 0xe60520c6), /* PORT198CR */
PORTCR(199, 0xe60520c7), /* PORT199CR */
PORTCR(200, 0xe60520c8), /* PORT200CR */
PORTCR(201, 0xe60520c9), /* PORT201CR */
PORTCR(202, 0xe60520ca), /* PORT202CR */
PORTCR(203, 0xe60520cb), /* PORT203CR */
PORTCR(204, 0xe60520cc), /* PORT204CR */
PORTCR(205, 0xe60520cd), /* PORT205CR */
PORTCR(206, 0xe60520ce), /* PORT206CR */
PORTCR(207, 0xe60520cf), /* PORT207CR */
PORTCR(208, 0xe60520d0), /* PORT208CR */
PORTCR(209, 0xe60520d1), /* PORT209CR */
PORTCR(210, 0xe60520d2), /* PORT210CR */
PORTCR(211, 0xe60520d3), /* PORT211CR */
PORTCR(212, 0xe60520d4), /* PORT212CR */
PORTCR(213, 0xe60520d5), /* PORT213CR */
PORTCR(214, 0xe60520d6), /* PORT214CR */
PORTCR(215, 0xe60520d7), /* PORT215CR */
PORTCR(216, 0xe60520d8), /* PORT216CR */
PORTCR(217, 0xe60520d9), /* PORT217CR */
PORTCR(218, 0xe60520da), /* PORT218CR */
PORTCR(219, 0xe60520db), /* PORT219CR */
PORTCR(220, 0xe60520dc), /* PORT220CR */
PORTCR(221, 0xe60520dd), /* PORT221CR */
PORTCR(222, 0xe60520de), /* PORT222CR */
PORTCR(223, 0xe60520df), /* PORT223CR */
PORTCR(224, 0xe60520e0), /* PORT224CR */
PORTCR(225, 0xe60520e1), /* PORT225CR */
PORTCR(226, 0xe60520e2), /* PORT226CR */
PORTCR(227, 0xe60520e3), /* PORT227CR */
PORTCR(228, 0xe60520e4), /* PORT228CR */
PORTCR(229, 0xe60520e5), /* PORT229CR */
PORTCR(230, 0xe60520e6), /* PORT230CR */
PORTCR(231, 0xe60520e7), /* PORT231CR */
PORTCR(232, 0xe60520e8), /* PORT232CR */
PORTCR(233, 0xe60520e9), /* PORT233CR */
PORTCR(234, 0xe60520ea), /* PORT234CR */
PORTCR(235, 0xe60520eb), /* PORT235CR */
PORTCR(236, 0xe60520ec), /* PORT236CR */
PORTCR(237, 0xe60520ed), /* PORT237CR */
PORTCR(238, 0xe60520ee), /* PORT238CR */
PORTCR(239, 0xe60520ef), /* PORT239CR */
PORTCR(240, 0xe60520f0), /* PORT240CR */
PORTCR(241, 0xe60520f1), /* PORT241CR */
PORTCR(242, 0xe60520f2), /* PORT242CR */
PORTCR(243, 0xe60520f3), /* PORT243CR */
PORTCR(244, 0xe60520f4), /* PORT244CR */
PORTCR(245, 0xe60520f5), /* PORT245CR */
PORTCR(246, 0xe60520f6), /* PORT246CR */
PORTCR(247, 0xe60520f7), /* PORT247CR */
PORTCR(248, 0xe60520f8), /* PORT248CR */
PORTCR(249, 0xe60520f9), /* PORT249CR */
PORTCR(250, 0xe60520fa), /* PORT250CR */
PORTCR(251, 0xe60520fb), /* PORT251CR */
PORTCR(252, 0xe60520fc), /* PORT252CR */
PORTCR(253, 0xe60520fd), /* PORT253CR */
PORTCR(254, 0xe60520fe), /* PORT254CR */
PORTCR(255, 0xe60520ff), /* PORT255CR */
PORTCR(256, 0xe6052100), /* PORT256CR */
PORTCR(257, 0xe6052101), /* PORT257CR */
PORTCR(258, 0xe6052102), /* PORT258CR */
PORTCR(259, 0xe6052103), /* PORT259CR */
PORTCR(260, 0xe6052104), /* PORT260CR */
PORTCR(261, 0xe6052105), /* PORT261CR */
PORTCR(262, 0xe6052106), /* PORT262CR */
PORTCR(263, 0xe6052107), /* PORT263CR */
PORTCR(264, 0xe6052108), /* PORT264CR */
{ PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
MSELBCR_MSEL17_0, MSELBCR_MSEL17_1,
MSELBCR_MSEL16_0, MSELBCR_MSEL16_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
},
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
},
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) {
0, 0, 0, 0,
0, 0, 0, 0,
0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
},
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) {
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) {
PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
},
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) {
PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
},
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT264_DATA,
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
},
{ },
};
static struct pinmux_info sh7377_pinmux_info = {
.name = "sh7377_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PORT0,
.last_gpio = GPIO_FN_RESETOUTS,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
void sh7377_pinmux_init(void)
{
register_pinmux(&sh7377_pinmux_info);
}
arch/arm/mach-shmobile/setup-r8a7740.c
View file @ ab3ff12a
......@@ -590,6 +590,21 @@ static struct platform_device i2c1_device = {
.num_resources = ARRAY_SIZE(i2c1_resources),
};
static struct resource pmu_resources[] = {
[0] = {
.start = evt2irq(0x19a0),
.end = evt2irq(0x19a0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pmu_device = {
.name = "arm-pmu",
.id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
static struct platform_device *r8a7740_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
......@@ -597,6 +612,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
&dma1_device,
&dma2_device,
&usb_dma_device,
&pmu_device,
};
/*
......@@ -747,7 +763,7 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
NULL,
};
DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
.map_io = r8a7740_map_io,
.init_early = r8a7740_add_early_devices_dt,
.init_irq = r8a7740_init_irq,
......
arch/arm/mach-shmobile/setup-r8a7779.c
View file @ ab3ff12a
......@@ -229,6 +229,79 @@ static struct platform_device tmu01_device = {
.num_resources = ARRAY_SIZE(tmu01_resources),
};
/* I2C */
static struct resource rcar_i2c0_res[] = {
{
.start = 0xffc70000,
.end = 0xffc70fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(79),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c0_device = {
.name = "i2c-rcar",
.id = 0,
.resource = rcar_i2c0_res,
.num_resources = ARRAY_SIZE(rcar_i2c0_res),
};
static struct resource rcar_i2c1_res[] = {
{
.start = 0xffc71000,
.end = 0xffc71fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(82),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c1_device = {
.name = "i2c-rcar",
.id = 1,
.resource = rcar_i2c1_res,
.num_resources = ARRAY_SIZE(rcar_i2c1_res),
};
static struct resource rcar_i2c2_res[] = {
{
.start = 0xffc72000,
.end = 0xffc72fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(80),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c2_device = {
.name = "i2c-rcar",
.id = 2,
.resource = rcar_i2c2_res,
.num_resources = ARRAY_SIZE(rcar_i2c2_res),
};
static struct resource rcar_i2c3_res[] = {
{
.start = 0xffc73000,
.end = 0xffc73fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(81),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c3_device = {
.name = "i2c-rcar",
.id = 3,
.resource = rcar_i2c3_res,
.num_resources = ARRAY_SIZE(rcar_i2c3_res),
};
static struct platform_device *r8a7779_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
......@@ -238,6 +311,10 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
&scif5_device,
&tmu00_device,
&tmu01_device,
&i2c0_device,
&i2c1_device,
&i2c2_device,
&i2c3_device,
};
static struct platform_device *r8a7779_late_devices[] __initdata = {
......
arch/arm/mach-shmobile/setup-sh7367.c deleted 100644 → 0
View file @ 631a7b5d
/*
* sh7367 processor support
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2008 Yoshihiro Shimoda
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/uio_driver.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
static struct map_desc sh7367_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
void __init sh7367_map_io(void)
{
iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc00), evt2irq(0xc00),
evt2irq(0xc00), evt2irq(0xc00) },
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc20), evt2irq(0xc20),
evt2irq(0xc20), evt2irq(0xc20) },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc40), evt2irq(0xc40),
evt2irq(0xc40), evt2irq(0xc40) },
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc60), evt2irq(0xc60),
evt2irq(0xc60), evt2irq(0xc60) },
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xd20), evt2irq(0xd20),
evt2irq(0xd20), evt2irq(0xd20) },
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xd40), evt2irq(0xd40),
evt2irq(0xd40), evt2irq(0xd40) },
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
/* SCIFB */
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = { evt2irq(0xd60), evt2irq(0xd60),
evt2irq(0xd60), evt2irq(0xd60) },
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
static struct sh_timer_config cmt10_platform_data = {
.name = "CMT10",
.channel_offset = 0x10,
.timer_bit = 0,
.clockevent_rating = 125,
.clocksource_rating = 125,
};
static struct resource cmt10_resources[] = {
[0] = {
.name = "CMT10",
.start = 0xe6138010,
.end = 0xe613801b,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xb00), /* CMT1_CMT10 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cmt10_device = {
.name = "sh_cmt",
.id = 10,
.dev = {
.platform_data = &cmt10_platform_data,
},
.resource = cmt10_resources,
.num_resources = ARRAY_SIZE(cmt10_resources),
};
/* VPU */
static struct uio_info vpu_platform_data = {
.name = "VPU5",
.version = "0",
.irq = intcs_evt2irq(0x980),
};
static struct resource vpu_resources[] = {
[0] = {
.name = "VPU",
.start = 0xfe900000,
.end = 0xfe902807,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device vpu_device = {
.name = "uio_pdrv_genirq",
.id = 0,
.dev = {
.platform_data = &vpu_platform_data,
},
.resource = vpu_resources,
.num_resources = ARRAY_SIZE(vpu_resources),
};
/* VEU0 */
static struct uio_info veu0_platform_data = {
.name = "VEU0",
.version = "0",
.irq = intcs_evt2irq(0x700),
};
static struct resource veu0_resources[] = {
[0] = {
.name = "VEU0",
.start = 0xfe920000,
.end = 0xfe9200b7,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu0_device = {
.name = "uio_pdrv_genirq",
.id = 1,
.dev = {
.platform_data = &veu0_platform_data,
},
.resource = veu0_resources,
.num_resources = ARRAY_SIZE(veu0_resources),
};
/* VEU1 */
static struct uio_info veu1_platform_data = {
.name = "VEU1",
.version = "0",
.irq = intcs_evt2irq(0x720),
};
static struct resource veu1_resources[] = {
[0] = {
.name = "VEU1",
.start = 0xfe924000,
.end = 0xfe9240b7,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu1_device = {
.name = "uio_pdrv_genirq",
.id = 2,
.dev = {
.platform_data = &veu1_platform_data,
},
.resource = veu1_resources,
.num_resources = ARRAY_SIZE(veu1_resources),
};
/* VEU2 */
static struct uio_info veu2_platform_data = {
.name = "VEU2",
.version = "0",
.irq = intcs_evt2irq(0x740),
};
static struct resource veu2_resources[] = {
[0] = {
.name = "VEU2",
.start = 0xfe928000,
.end = 0xfe9280b7,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu2_device = {
.name = "uio_pdrv_genirq",
.id = 3,
.dev = {
.platform_data = &veu2_platform_data,
},
.resource = veu2_resources,
.num_resources = ARRAY_SIZE(veu2_resources),
};
/* VEU3 */
static struct uio_info veu3_platform_data = {
.name = "VEU3",
.version = "0",
.irq = intcs_evt2irq(0x760),
};
static struct resource veu3_resources[] = {
[0] = {
.name = "VEU3",
.start = 0xfe92c000,
.end = 0xfe92c0b7,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu3_device = {
.name = "uio_pdrv_genirq",
.id = 4,
.dev = {
.platform_data = &veu3_platform_data,
},
.resource = veu3_resources,
.num_resources = ARRAY_SIZE(veu3_resources),
};
/* VEU2H */
static struct uio_info veu2h_platform_data = {
.name = "VEU2H",
.version = "0",
.irq = intcs_evt2irq(0x520),
};
static struct resource veu2h_resources[] = {
[0] = {
.name = "VEU2H",
.start = 0xfe93c000,
.end = 0xfe93c27b,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu2h_device = {
.name = "uio_pdrv_genirq",
.id = 5,
.dev = {
.platform_data = &veu2h_platform_data,
},
.resource = veu2h_resources,
.num_resources = ARRAY_SIZE(veu2h_resources),
};
/* JPU */
static struct uio_info jpu_platform_data = {
.name = "JPU",
.version = "0",
.irq = intcs_evt2irq(0x560),
};
static struct resource jpu_resources[] = {
[0] = {
.name = "JPU",
.start = 0xfe980000,
.end = 0xfe9902d3,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device jpu_device = {
.name = "uio_pdrv_genirq",
.id = 6,
.dev = {
.platform_data = &jpu_platform_data,
},
.resource = jpu_resources,
.num_resources = ARRAY_SIZE(jpu_resources),
};
/* SPU1 */
static struct uio_info spu1_platform_data = {
.name = "SPU1",
.version = "0",
.irq = evt2irq(0xfc0),
};
static struct resource spu1_resources[] = {
[0] = {
.name = "SPU1",
.start = 0xfe300000,
.end = 0xfe3fffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device spu1_device = {
.name = "uio_pdrv_genirq",
.id = 7,
.dev = {
.platform_data = &spu1_platform_data,
},
.resource = spu1_resources,
.num_resources = ARRAY_SIZE(spu1_resources),
};
static struct platform_device *sh7367_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
&scif3_device,
&scif4_device,
&scif5_device,
&scif6_device,
&cmt10_device,
};
static struct platform_device *sh7367_devices[] __initdata = {
&vpu_device,
&veu0_device,
&veu1_device,
&veu2_device,
&veu3_device,
&veu2h_device,
&jpu_device,
&spu1_device,
};
void __init sh7367_add_standard_devices(void)
{
platform_add_devices(sh7367_early_devices,
ARRAY_SIZE(sh7367_early_devices));
platform_add_devices(sh7367_devices,
ARRAY_SIZE(sh7367_devices));
}
static void __init sh7367_earlytimer_init(void)
{
sh7367_clock_init();
shmobile_earlytimer_init();
}
#define SYMSTPCR2 IOMEM(0xe6158048)
#define SYMSTPCR2_CMT1 (1 << 29)
void __init sh7367_add_early_devices(void)
{
/* enable clock to CMT1 */
__raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
early_platform_add_devices(sh7367_early_devices,
ARRAY_SIZE(sh7367_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = sh7367_earlytimer_init;
}
arch/arm/mach-shmobile/setup-sh7372.c
View file @ ab3ff12a
......@@ -407,6 +407,26 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
.addr = 0xe6c30060,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3e,
}, {
.slave_id = SHDMA_SLAVE_FLCTL0_TX,
.addr = 0xe6a30050,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0x83,
}, {
.slave_id = SHDMA_SLAVE_FLCTL0_RX,
.addr = 0xe6a30050,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x83,
}, {
.slave_id = SHDMA_SLAVE_FLCTL1_TX,
.addr = 0xe6a30060,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0x87,
}, {
.slave_id = SHDMA_SLAVE_FLCTL1_RX,
.addr = 0xe6a30060,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x87,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030,
......
arch/arm/mach-shmobile/setup-sh7377.c deleted 100644 → 0
View file @ 631a7b5d
/*
* sh7377 processor support
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2008 Yoshihiro Shimoda
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/uio_driver.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
static struct map_desc sh7377_io_desc[] __initdata = {
/* create a 1:1 entity map for 0xe6xxxxxx
* used by CPGA, INTC and PFC.
*/
{
.virtual = 0xe6000000,
.pfn = __phys_to_pfn(0xe6000000),
.length = 256 << 20,
.type = MT_DEVICE_NONSHARED
},
};
void __init sh7377_map_io(void)
{
iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc00), evt2irq(0xc00),
evt2irq(0xc00), evt2irq(0xc00) },
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc20), evt2irq(0xc20),
evt2irq(0xc20), evt2irq(0xc20) },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc40), evt2irq(0xc40),
evt2irq(0xc40), evt2irq(0xc40) },
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xc60), evt2irq(0xc60),
evt2irq(0xc60), evt2irq(0xc60) },
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xd20), evt2irq(0xd20),
evt2irq(0xd20), evt2irq(0xd20) },
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0xd40), evt2irq(0xd40),
evt2irq(0xd40), evt2irq(0xd40) },
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
/* SCIFA6 */
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6cc0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
/* SCIFB */
static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = { evt2irq(0xd60), evt2irq(0xd60),
evt2irq(0xd60), evt2irq(0xd60) },
};
static struct platform_device scif7_device = {
.name = "sh-sci",
.id = 7,
.dev = {
.platform_data = &scif7_platform_data,
},
};
static struct sh_timer_config cmt10_platform_data = {
.name = "CMT10",
.channel_offset = 0x10,
.timer_bit = 0,
.clockevent_rating = 125,
.clocksource_rating = 125,
};
static struct resource cmt10_resources[] = {
[0] = {
.name = "CMT10",
.start = 0xe6138010,
.end = 0xe613801b,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xb00), /* CMT1_CMT10 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cmt10_device = {
.name = "sh_cmt",
.id = 10,
.dev = {
.platform_data = &cmt10_platform_data,
},
.resource = cmt10_resources,
.num_resources = ARRAY_SIZE(cmt10_resources),
};
/* VPU */
static struct uio_info vpu_platform_data = {
.name = "VPU5HG",
.version = "0",
.irq = intcs_evt2irq(0x980),
};
static struct resource vpu_resources[] = {
[0] = {
.name = "VPU",
.start = 0xfe900000,
.end = 0xfe900157,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device vpu_device = {
.name = "uio_pdrv_genirq",
.id = 0,
.dev = {
.platform_data = &vpu_platform_data,
},
.resource = vpu_resources,
.num_resources = ARRAY_SIZE(vpu_resources),
};
/* VEU0 */
static struct uio_info veu0_platform_data = {
.name = "VEU0",
.version = "0",
.irq = intcs_evt2irq(0x700),
};
static struct resource veu0_resources[] = {
[0] = {
.name = "VEU0",
.start = 0xfe920000,
.end = 0xfe9200cb,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu0_device = {
.name = "uio_pdrv_genirq",
.id = 1,
.dev = {
.platform_data = &veu0_platform_data,
},
.resource = veu0_resources,
.num_resources = ARRAY_SIZE(veu0_resources),
};
/* VEU1 */
static struct uio_info veu1_platform_data = {
.name = "VEU1",
.version = "0",
.irq = intcs_evt2irq(0x720),
};
static struct resource veu1_resources[] = {
[0] = {
.name = "VEU1",
.start = 0xfe924000,
.end = 0xfe9240cb,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu1_device = {
.name = "uio_pdrv_genirq",
.id = 2,
.dev = {
.platform_data = &veu1_platform_data,
},
.resource = veu1_resources,
.num_resources = ARRAY_SIZE(veu1_resources),
};
/* VEU2 */
static struct uio_info veu2_platform_data = {
.name = "VEU2",
.version = "0",
.irq = intcs_evt2irq(0x740),
};
static struct resource veu2_resources[] = {
[0] = {
.name = "VEU2",
.start = 0xfe928000,
.end = 0xfe928307,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu2_device = {
.name = "uio_pdrv_genirq",
.id = 3,
.dev = {
.platform_data = &veu2_platform_data,
},
.resource = veu2_resources,
.num_resources = ARRAY_SIZE(veu2_resources),
};
/* VEU3 */
static struct uio_info veu3_platform_data = {
.name = "VEU3",
.version = "0",
.irq = intcs_evt2irq(0x760),
};
static struct resource veu3_resources[] = {
[0] = {
.name = "VEU3",
.start = 0xfe92c000,
.end = 0xfe92c307,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device veu3_device = {
.name = "uio_pdrv_genirq",
.id = 4,
.dev = {
.platform_data = &veu3_platform_data,
},
.resource = veu3_resources,
.num_resources = ARRAY_SIZE(veu3_resources),
};
/* JPU */
static struct uio_info jpu_platform_data = {
.name = "JPU",
.version = "0",
.irq = intcs_evt2irq(0x560),
};
static struct resource jpu_resources[] = {
[0] = {
.name = "JPU",
.start = 0xfe980000,
.end = 0xfe9902d3,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device jpu_device = {
.name = "uio_pdrv_genirq",
.id = 5,
.dev = {
.platform_data = &jpu_platform_data,
},
.resource = jpu_resources,
.num_resources = ARRAY_SIZE(jpu_resources),
};
/* SPU2DSP0 */
static struct uio_info spu0_platform_data = {
.name = "SPU2DSP0",
.version = "0",
.irq = evt2irq(0x1800),
};
static struct resource spu0_resources[] = {
[0] = {
.name = "SPU2DSP0",
.start = 0xfe200000,
.end = 0xfe2fffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device spu0_device = {
.name = "uio_pdrv_genirq",
.id = 6,
.dev = {
.platform_data = &spu0_platform_data,
},
.resource = spu0_resources,
.num_resources = ARRAY_SIZE(spu0_resources),
};
/* SPU2DSP1 */
static struct uio_info spu1_platform_data = {
.name = "SPU2DSP1",
.version = "0",
.irq = evt2irq(0x1820),
};
static struct resource spu1_resources[] = {
[0] = {
.name = "SPU2DSP1",
.start = 0xfe300000,
.end = 0xfe3fffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device spu1_device = {
.name = "uio_pdrv_genirq",
.id = 7,
.dev = {
.platform_data = &spu1_platform_data,
},
.resource = spu1_resources,
.num_resources = ARRAY_SIZE(spu1_resources),
};
static struct platform_device *sh7377_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
&scif3_device,
&scif4_device,
&scif5_device,
&scif6_device,
&scif7_device,
&cmt10_device,
};
static struct platform_device *sh7377_devices[] __initdata = {
&vpu_device,
&veu0_device,
&veu1_device,
&veu2_device,
&veu3_device,
&jpu_device,
&spu0_device,
&spu1_device,
};
void __init sh7377_add_standard_devices(void)
{
platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
platform_add_devices(sh7377_devices,
ARRAY_SIZE(sh7377_devices));
}
static void __init sh7377_earlytimer_init(void)
{
sh7377_clock_init();
shmobile_earlytimer_init();
}
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR3_CMT1 (1 << 29)
void __init sh7377_add_early_devices(void)
{
/* enable clock to CMT1 */
__raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
early_platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
/* setup early console here as well */
shmobile_setup_console();
/* override timer setup with soc-specific code */
shmobile_timer.init = sh7377_earlytimer_init;
}
#ifdef CONFIG_USE_OF
void __init sh7377_add_early_devices_dt(void)
{
shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
early_platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
/* setup early console here as well */
shmobile_setup_console();
}
static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
{ }
};
void __init sh7377_add_standard_devices_dt(void)
{
/* clocks are setup late during boot in the case of DT */
sh7377_clock_init();
platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
of_platform_populate(NULL, of_default_bus_match_table,
sh7377_auxdata_lookup, NULL);
}
static const char *sh7377_boards_compat_dt[] __initdata = {
"renesas,sh7377",
NULL,
};
DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
.map_io = sh7377_map_io,
.init_early = sh7377_add_early_devices_dt,
.init_irq = sh7377_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7377_add_standard_devices_dt,
.timer = &shmobile_timer,
.dt_compat = sh7377_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
arch/arm/mach-shmobile/smp-emev2.c
View file @ ab3ff12a
......@@ -32,24 +32,8 @@
#define EMEV2_SCU_BASE 0x1e000000
static DEFINE_SPINLOCK(scu_lock);
static void __iomem *scu_base;
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
{
unsigned long tmp;
/* we assume this code is running on a different cpu
* than the one that is changing coherency setting */
spin_lock(&scu_lock);
tmp = readl(scu_base + 8);
tmp &= ~clr;
tmp |= set;
writel(tmp, scu_base + 8);
spin_unlock(&scu_lock);
}
static unsigned int __init emev2_get_core_count(void)
{
if (!scu_base) {
......@@ -95,7 +79,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
scu_power_mode(scu_base, 0);
/* Tell ROM loader about our vector (in headsmp.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
......@@ -106,12 +90,10 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
{
int cpu = cpu_logical_map(0);
scu_enable(scu_base);
/* enable cache coherency on CPU0 */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
scu_power_mode(scu_base, 0);
}
static void __init emev2_smp_init_cpus(void)
......
arch/arm/mach-shmobile/smp-r8a7779.c
View file @ ab3ff12a
......@@ -61,9 +61,6 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
static DEFINE_SPINLOCK(scu_lock);
static unsigned long tmp;
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
......@@ -73,20 +70,6 @@ void __init r8a7779_register_twd(void)
}
#endif
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
{
void __iomem *scu_base = scu_base_addr();
spin_lock(&scu_lock);
tmp = __raw_readl(scu_base + 8);
tmp &= ~clr;
tmp |= set;
spin_unlock(&scu_lock);
/* disable cache coherency after releasing the lock */
__raw_writel(tmp, scu_base + 8);
}
static unsigned int __init r8a7779_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
......@@ -102,7 +85,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
cpu = cpu_logical_map(cpu);
/* disable cache coherency */
modify_scu_cpu_psr(3 << (cpu * 8), 0);
scu_power_mode(scu_base_addr(), 3);
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
......@@ -145,7 +128,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
scu_power_mode(scu_base_addr(), 0);
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
......@@ -158,15 +141,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
{
int cpu = cpu_logical_map(0);
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
__raw_writel(__pa(shmobile_secondary_vector), AVECR);
/* enable cache coherency on CPU0 */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
scu_power_mode(scu_base_addr(), 0);
r8a7779_pm_init();
......
arch/arm/mach-shmobile/smp-sh73a0.c
View file @ ab3ff12a
......@@ -41,9 +41,6 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
static DEFINE_SPINLOCK(scu_lock);
static unsigned long tmp;
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
void __init sh73a0_register_twd(void)
......@@ -52,20 +49,6 @@ void __init sh73a0_register_twd(void)
}
#endif
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
{
void __iomem *scu_base = scu_base_addr();
spin_lock(&scu_lock);
tmp = __raw_readl(scu_base + 8);
tmp &= ~clr;
tmp |= set;
spin_unlock(&scu_lock);
/* disable cache coherency after releasing the lock */
__raw_writel(tmp, scu_base + 8);
}
static unsigned int __init sh73a0_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
......@@ -83,7 +66,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
scu_power_mode(scu_base_addr(), 0);
if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
__raw_writel(1 << cpu, WUPCR); /* wake up */
......@@ -95,8 +78,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
{
int cpu = cpu_logical_map(0);
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
......@@ -104,7 +85,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
__raw_writel(__pa(shmobile_secondary_vector), SBAR);
/* enable cache coherency on CPU0 */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
scu_power_mode(scu_base_addr(), 0);
}
static void __init sh73a0_smp_init_cpus(void)
......
drivers/sh/clk/cpg.c
View file @ ab3ff12a
......@@ -361,3 +361,89 @@ int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
return sh_clk_div_register_ops(clks, nr, table,
&sh_clk_div4_reparent_clk_ops);
}
/* FSI-DIV */
static unsigned long fsidiv_recalc(struct clk *clk)
{
u32 value;
value = __raw_readl(clk->mapping->base);
value >>= 16;
if (value < 2)
return clk->parent->rate;
return clk->parent->rate / value;
}
static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_div_range_round(clk, 1, 0xffff, rate);
}
static void fsidiv_disable(struct clk *clk)
{
__raw_writel(0, clk->mapping->base);
}
static int fsidiv_enable(struct clk *clk)
{
u32 value;
value = __raw_readl(clk->mapping->base) >> 16;
if (value < 2)
return 0;
__raw_writel((value << 16) | 0x3, clk->mapping->base);
return 0;
}
static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
{
u32 val;
int idx;
idx = (clk->parent->rate / rate) & 0xffff;
if (idx < 2)
__raw_writel(0, clk->mapping->base);
else
__raw_writel(idx << 16, clk->mapping->base);
return 0;
}
static struct sh_clk_ops fsidiv_clk_ops = {
.recalc = fsidiv_recalc,
.round_rate = fsidiv_round_rate,
.set_rate = fsidiv_set_rate,
.enable = fsidiv_enable,
.disable = fsidiv_disable,
};
int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
{
struct clk_mapping *map;
int i;
for (i = 0; i < nr; i++) {
map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
if (!map) {
pr_err("%s: unable to alloc memory\n", __func__);
return -ENOMEM;
}
/* clks[i].enable_reg came from SH_CLK_FSIDIV() */
map->phys = (phys_addr_t)clks[i].enable_reg;
map->len = 8;
clks[i].enable_reg = 0; /* remove .enable_reg */
clks[i].ops = &fsidiv_clk_ops;
clks[i].mapping = map;
clk_register(&clks[i]);
}
return 0;
}
include/linux/sh_clk.h
View file @ ab3ff12a
......@@ -199,4 +199,13 @@ int sh_clk_div6_reparent_register(struct clk *clks, int nr);
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
#define SH_CLK_FSIDIV(_reg, _parent) \
{ \
.enable_reg = (void __iomem *)_reg, \
.parent = _parent, \
}
int sh_clk_fsidiv_register(struct clk *clks, int nr);
#endif /* __SH_CLOCK_H */
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