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Commit abf2ba15 authored by Arnd Bergmann's avatar Arnd Bergmann
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ARM: iop13xx: use __iomem pointers for MMIO 

ARM is moving to stricter checks on readl/write functions,
so we need to use the correct types everywhere.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent b7a3f8db
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Inline Side-by-side
Showing with 36 additions and 40 deletions
arch/arm/mach-iop13xx/include/mach/iop13xx.h
View file @ abf2ba15
...@@ -148,18 +148,16 @@ extern unsigned long get_iop_tick_rate(void); ...@@ -148,18 +148,16 @@ extern unsigned long get_iop_tick_rate(void);
* IOP13XX chipset registers * IOP13XX chipset registers
*/ */
#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ #define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
(IOP13XX_PMMR_PHYS_MEM_BASE\ + IOP13XX_PMMR_PHYS_MEM_BASE)
- IOP13XX_PMMR_VIRT_MEM_BASE)) #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + IOP13XX_PMMR_VIRT_MEM_BASE)
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
...@@ -169,10 +167,10 @@ extern unsigned long get_iop_tick_rate(void); ...@@ -169,10 +167,10 @@ extern unsigned long get_iop_tick_rate(void);
#define IOP13XX_PMMR_SIZE 0x00080000 #define IOP13XX_PMMR_SIZE 0x00080000
/*=================== Defines for Platform Devices =====================*/ /*=================== Defines for Platform Devices =====================*/
#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
......
arch/arm/mach-iop13xx/include/mach/memory.h
View file @ abf2ba15
...@@ -16,12 +16,12 @@ ...@@ -16,12 +16,12 @@
#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
static inline dma_addr_t __virt_to_lbus(unsigned long x) static inline dma_addr_t __virt_to_lbus(void __iomem *x)
{ {
return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
} }
static inline unsigned long __lbus_to_virt(dma_addr_t x) static inline void __iomem *__lbus_to_virt(dma_addr_t x)
{ {
return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
} }
...@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) ...@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
#define __arch_dma_to_virt(dev, addr) \ #define __arch_dma_to_virt(dev, addr) \
({ \ ({ \
unsigned long __virt; \ void * __virt; \
dma_addr_t __dma = addr; \ dma_addr_t __dma = addr; \
if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
__virt = __lbus_to_virt(__dma); \ __virt = __lbus_to_virt(__dma); \
else \ else \
__virt = __phys_to_virt(__dma); \ __virt = (void *)__phys_to_virt(__dma); \
(void *)__virt; \ __virt; \
}) })
#define __arch_virt_to_dma(dev, addr) \ #define __arch_virt_to_dma(dev, addr) \
({ \ ({ \
unsigned long __virt = (unsigned long)addr; \ void * __virt = addr; \
dma_addr_t __dma; \ dma_addr_t __dma; \
if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
__dma = __virt_to_lbus(__virt); \ __dma = __virt_to_lbus(__virt); \
else \ else \
__dma = __virt_to_phys(__virt); \ __dma = __virt_to_phys((unsigned long)__virt); \
__dma; \ __dma; \
}) })
......
arch/arm/mach-iop13xx/io.c
View file @ abf2ba15
...@@ -52,14 +52,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, ...@@ -52,14 +52,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
if (unlikely(!iop13xx_atux_mem_base)) if (unlikely(!iop13xx_atux_mem_base))
retval = NULL; retval = NULL;
else else
retval = (void *)(iop13xx_atux_mem_base + retval = (iop13xx_atux_mem_base +
(cookie - IOP13XX_PCIX_LOWER_MEM_RA)); (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
break; break;
case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
if (unlikely(!iop13xx_atue_mem_base)) if (unlikely(!iop13xx_atue_mem_base))
retval = NULL; retval = NULL;
else else
retval = (void *)(iop13xx_atue_mem_base + retval = (iop13xx_atue_mem_base +
(cookie - IOP13XX_PCIE_LOWER_MEM_RA)); (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
break; break;
case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
...@@ -74,7 +74,7 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, ...@@ -74,7 +74,7 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
break; break;
case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
break; break;
default: default:
retval = __arm_ioremap_caller(cookie, size, mtype, retval = __arm_ioremap_caller(cookie, size, mtype,
...@@ -99,9 +99,9 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) ...@@ -99,9 +99,9 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
goto skip; goto skip;
switch ((u32) addr) { switch ((u32) addr) {
case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: case (u32)IOP13XX_PCIE_LOWER_IO_VA ... (u32)IOP13XX_PCIE_UPPER_IO_VA:
case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: case (u32)IOP13XX_PCIX_LOWER_IO_VA ... (u32)IOP13XX_PCIX_UPPER_IO_VA:
case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
goto skip; goto skip;
} }
__iounmap(addr); __iounmap(addr);
......
arch/arm/mach-iop13xx/pci.c
View file @ abf2ba15
...@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ ...@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
static struct pci_bus *pci_bus_atux = 0; static struct pci_bus *pci_bus_atux = 0;
static struct pci_bus *pci_bus_atue = 0; static struct pci_bus *pci_bus_atue = 0;
u32 iop13xx_atue_mem_base; void __iomem *iop13xx_atue_mem_base;
u32 iop13xx_atux_mem_base; void __iomem *iop13xx_atux_mem_base;
size_t iop13xx_atue_mem_size; size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size; size_t iop13xx_atux_mem_size;
...@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void) ...@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
} }
if (end) { if (end) {
iop13xx_atux_mem_base = iop13xx_atux_mem_base = __arm_ioremap_pfn(
(u32) __arm_ioremap_pfn(
__phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
, 0, iop13xx_atux_mem_size, MT_DEVICE); , 0, iop13xx_atux_mem_size, MT_DEVICE);
if (!iop13xx_atux_mem_base) { if (!iop13xx_atux_mem_base) {
...@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void) ...@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
} }
} else } else
iop13xx_atux_mem_size = 0; iop13xx_atux_mem_size = 0;
PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
__func__, atu, iop13xx_atux_mem_size, __func__, atu, iop13xx_atux_mem_size,
iop13xx_atux_mem_base); iop13xx_atux_mem_base);
break; break;
...@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void) ...@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
} }
if (end) { if (end) {
iop13xx_atue_mem_base = iop13xx_atue_mem_base = __arm_ioremap_pfn(
(u32) __arm_ioremap_pfn(
__phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
, 0, iop13xx_atue_mem_size, MT_DEVICE); , 0, iop13xx_atue_mem_size, MT_DEVICE);
if (!iop13xx_atue_mem_base) { if (!iop13xx_atue_mem_base) {
...@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void) ...@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
} }
} else } else
iop13xx_atue_mem_size = 0; iop13xx_atue_mem_size = 0;
PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
__func__, atu, iop13xx_atue_mem_size, __func__, atu, iop13xx_atue_mem_size,
iop13xx_atue_mem_base); iop13xx_atue_mem_base);
break; break;
} }
printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
atu ? "ATUE" : "ATUX", atu ? "ATUE" : "ATUX",
(atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
SZ_1M, SZ_1M,
......
arch/arm/mach-iop13xx/pci.h
View file @ abf2ba15
#include <linux/types.h> #include <linux/types.h>
extern u32 iop13xx_atue_mem_base; extern void __iomem *iop13xx_atue_mem_base;
extern u32 iop13xx_atux_mem_base; extern void __iomem *iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size; extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size; extern size_t iop13xx_atux_mem_size;
arch/arm/mach-iop13xx/setup.c
View file @ abf2ba15
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
*/ */
static struct map_desc iop13xx_std_desc[] __initdata = { static struct map_desc iop13xx_std_desc[] __initdata = {
{ /* mem mapped registers */ { /* mem mapped registers */
.virtual = IOP13XX_PMMR_VIRT_MEM_BASE, .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
.length = IOP13XX_PMMR_SIZE, .length = IOP13XX_PMMR_SIZE,
.type = MT_DEVICE, .type = MT_DEVICE,
...@@ -81,8 +81,8 @@ static struct resource iop13xx_uart1_resources[] = { ...@@ -81,8 +81,8 @@ static struct resource iop13xx_uart1_resources[] = {
static struct plat_serial8250_port iop13xx_uart0_data[] = { static struct plat_serial8250_port iop13xx_uart0_data[] = {
{ {
.membase = (char*)(IOP13XX_UART0_VIRT), .membase = IOP13XX_UART0_VIRT,
.mapbase = (IOP13XX_UART0_PHYS), .mapbase = IOP13XX_UART0_PHYS,
.irq = IRQ_IOP13XX_UART0, .irq = IRQ_IOP13XX_UART0,
.uartclk = IOP13XX_UART_XTAL, .uartclk = IOP13XX_UART_XTAL,
.regshift = 2, .regshift = 2,
...@@ -94,8 +94,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = { ...@@ -94,8 +94,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
static struct plat_serial8250_port iop13xx_uart1_data[] = { static struct plat_serial8250_port iop13xx_uart1_data[] = {
{ {
.membase = (char*)(IOP13XX_UART1_VIRT), .membase = IOP13XX_UART1_VIRT,
.mapbase = (IOP13XX_UART1_PHYS), .mapbase = IOP13XX_UART1_PHYS,
.irq = IRQ_IOP13XX_UART1, .irq = IRQ_IOP13XX_UART1,
.uartclk = IOP13XX_UART_XTAL, .uartclk = IOP13XX_UART_XTAL,
.regshift = 2, .regshift = 2,
......
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