Commit add6ab5b authored by Tom Rini's avatar Tom Rini Committed by Linus Torvalds

[PATCH] ppc32: MPC8xx TLB Miss vs TLB Error fix

There is a problem in the TLB Miss (and Error, as they jump to the Miss
handler) handlers.  The problem is that when an app spans more than one L1
entry, we don't have all of the correct information, and do_page_fault()
things a protection fault happened, when it didn't really.  The fix for this
is to modify the handlers slightly to force a TLB Error in this case.

Lots of suggestions from: Joakim Tjernlund <joakim.tjernlund@lumentis.se>
Signed-off-by: default avatarTom Rini <trini@kernel.crashing.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent bc9bec3c
...@@ -343,7 +343,7 @@ InstructionTLBMiss: ...@@ -343,7 +343,7 @@ InstructionTLBMiss:
* set. All other Linux PTE bits control the behavior * set. All other Linux PTE bits control the behavior
* of the MMU. * of the MMU.
*/ */
li r11, 0x00f0 2: li r11, 0x00f0
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x2d80, r3) DO_8xx_CPU6(0x2d80, r3)
mtspr MI_RPN, r10 /* Update TLB entry */ mtspr MI_RPN, r10 /* Update TLB entry */
...@@ -357,15 +357,6 @@ InstructionTLBMiss: ...@@ -357,15 +357,6 @@ InstructionTLBMiss:
#endif #endif
rfi rfi
2: mfspr r10, M_TW /* Restore registers */
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
b InstructionAccess
. = 0x1200 . = 0x1200
DataStoreTLBMiss: DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
...@@ -419,7 +410,7 @@ DataStoreTLBMiss: ...@@ -419,7 +410,7 @@ DataStoreTLBMiss:
* set. All other Linux PTE bits control the behavior * set. All other Linux PTE bits control the behavior
* of the MMU. * of the MMU.
*/ */
li r11, 0x00f0 2: li r11, 0x00f0
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3) DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r10 /* Update TLB entry */ mtspr MD_RPN, r10 /* Update TLB entry */
...@@ -433,15 +424,6 @@ DataStoreTLBMiss: ...@@ -433,15 +424,6 @@ DataStoreTLBMiss:
#endif #endif
rfi rfi
2: mfspr r10, M_TW /* Restore registers */
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
b DataAccess
/* This is an instruction TLB error on the MPC8xx. This could be due /* This is an instruction TLB error on the MPC8xx. This could be due
* to many reasons, such as executing guarded memory or illegal instruction * to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault. * addresses. There is nothing to do but handle a big time error fault.
......
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