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Commit add79d68 authored by Sam Ravnborg's avatar Sam Ravnborg Committed by David S. Miller
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sparc64: reorder functions in io_64.h 

Reorder functions so __raw_{read,write}* functions comes first,
followed by {read,write}*

Update comments for the two blocks of functions.
Signed-off-by: default avatarSam Ravnborg <sam@ravnborg.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent be80d844
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Showing with 120 additions and 114 deletions
arch/sparc/include/asm/io_64.h
View file @ add79d68
......@@ -12,117 +12,94 @@
/* BIO layer definitions. */
extern unsigned long kern_base, kern_size;
#define inb inb
static inline u8 inb(unsigned long addr)
/* __raw_{read,write}{b,w,l,q} uses direct access.
* Access the memory as big endian bypassing the cache
* by using ASI_PHYS_BYPASS_EC_E
*/
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
u8 ret;
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
return ret;
}
#define inw inw
static inline u16 inw(unsigned long addr)
#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
u16 ret;
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
return ret;
}
#define inl inl
static inline u32 inl(unsigned long addr)
#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
u32 ret;
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
return ret;
}
#define outb outb
static inline void outb(u8 b, unsigned long addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define outw outw
static inline void outw(u16 w, unsigned long addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define outl outl
static inline void outl(u32 l, unsigned long addr)
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define inb_p(__addr) inb(__addr)
#define outb_p(__b, __addr) outb(__b, __addr)
#define inw_p(__addr) inw(__addr)
#define outw_p(__w, __addr) outw(__w, __addr)
#define inl_p(__addr) inl(__addr)
#define outl_p(__l, __addr) outl(__l, __addr)
u64 ret;
void outsb(unsigned long, const void *, unsigned long);
void outsw(unsigned long, const void *, unsigned long);
void outsl(unsigned long, const void *, unsigned long);
void insb(unsigned long, void *, unsigned long);
void insw(unsigned long, void *, unsigned long);
void insl(unsigned long, void *, unsigned long);
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
{
insb((unsigned long __force)port, buf, count);
}
static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
{
insw((unsigned long __force)port, buf, count);
return ret;
}
static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
{
insl((unsigned long __force)port, buf, count);
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
#define __raw_writew __raw_writew
static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
{
outsb((unsigned long __force)port, buf, count);
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
#define __raw_writel __raw_writel
static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
{
outsw((unsigned long __force)port, buf, count);
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
{
outsl((unsigned long __force)port, buf, count);
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
: /* no outputs */
: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
/* Memory functions, same as I/O accesses on Ultra. */
/* Memory functions, same as I/O accesses on Ultra.
* Access memory as little endian bypassing
* the cache by using ASI_PHYS_BYPASS_EC_E_L
*/
#define readb readb
static inline u8 readb(const volatile void __iomem *addr)
{ u8 ret;
......@@ -206,92 +183,121 @@ static inline void writeq(u64 q, volatile void __iomem *addr)
: "memory");
}
#define readb_relaxed(__addr) readb(__addr)
#define readw_relaxed(__addr) readw(__addr)
#define readl_relaxed(__addr) readl(__addr)
#define readq_relaxed(__addr) readq(__addr)
/* Now versions without byte-swapping. */
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
#define inb inb
static inline u8 inb(unsigned long addr)
{
u8 ret;
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
#define inw inw
static inline u16 inw(unsigned long addr)
{
u16 ret;
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
#define inl inl
static inline u32 inl(unsigned long addr)
{
u32 ret;
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
return ret;
}
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
#define outb outb
static inline void outb(u8 b, unsigned long addr)
{
u64 ret;
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
: "=r" (ret)
: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
return ret;
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
#define outw outw
static inline void outw(u16 w, unsigned long addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define __raw_writew __raw_writew
static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
#define outl outl
static inline void outl(u32 l, unsigned long addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
: "memory");
}
#define __raw_writel __raw_writel
static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
#define inb_p(__addr) inb(__addr)
#define outb_p(__b, __addr) outb(__b, __addr)
#define inw_p(__addr) inw(__addr)
#define outw_p(__w, __addr) outw(__w, __addr)
#define inl_p(__addr) inl(__addr)
#define outl_p(__l, __addr) outl(__l, __addr)
void outsb(unsigned long, const void *, unsigned long);
void outsw(unsigned long, const void *, unsigned long);
void outsl(unsigned long, const void *, unsigned long);
void insb(unsigned long, void *, unsigned long);
void insw(unsigned long, void *, unsigned long);
void insl(unsigned long, void *, unsigned long);
static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
insb((unsigned long __force)port, buf, count);
}
static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
{
insw((unsigned long __force)port, buf, count);
}
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
: /* no outputs */
: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
insl((unsigned long __force)port, buf, count);
}
static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
{
outsb((unsigned long __force)port, buf, count);
}
static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
{
outsw((unsigned long __force)port, buf, count);
}
static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
{
outsl((unsigned long __force)port, buf, count);
}
#define readb_relaxed(__addr) readb(__addr)
#define readw_relaxed(__addr) readw(__addr)
#define readl_relaxed(__addr) readl(__addr)
#define readq_relaxed(__addr) readq(__addr)
/* Valid I/O Space regions are anywhere, because each PCI bus supported
* can live in an arbitrary area of the physical address range.
......
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