Commit af89fd81 authored by viresh kumar's avatar viresh kumar Committed by Russell King

ARM: 6703/1: SPEAr: update clk API support

- Add support for divisor per parent clock
- Add ENABLED_ON_INIT feature in clk
- Add clk_set_rate(), round_rate_index & clk_round_rate()
- Simplify clk_recalc functions
- Add/update clock definitions
Reviewed-by: default avatarStanley Miao <stanley.miao@windriver.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@st.com>
Signed-off-by: default avatarshiraz hashim <shiraz.hashim@st.com>
Signed-off-by: default avatarRajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent cf285434
This diff is collapsed.
...@@ -63,8 +63,8 @@ ...@@ -63,8 +63,8 @@
#define GPT1_CLK_SHIFT 11 #define GPT1_CLK_SHIFT 11
#define GPT2_CLK_SHIFT 12 #define GPT2_CLK_SHIFT 12
#define GPT_CLK_MASK 0x1 #define GPT_CLK_MASK 0x1
#define AUX_CLK_PLL3_MASK 0 #define AUX_CLK_PLL3_VAL 0
#define AUX_CLK_PLL1_MASK 1 #define AUX_CLK_PLL1_VAL 1
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) #define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
/* PERIP1_CLK_ENB register masks */ /* PERIP1_CLK_ENB register masks */
...@@ -113,6 +113,7 @@ ...@@ -113,6 +113,7 @@
#define RAS3_CLK_SYNT (MISC_BASE + 0x074) #define RAS3_CLK_SYNT (MISC_BASE + 0x074)
#define RAS4_CLK_SYNT (MISC_BASE + 0x078) #define RAS4_CLK_SYNT (MISC_BASE + 0x078)
/* aux clk synthesiser register masks for irda to ras4 */ /* aux clk synthesiser register masks for irda to ras4 */
#define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1 #define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0 #define AUX_EQ1_SEL 0
......
This diff is collapsed.
...@@ -66,8 +66,8 @@ ...@@ -66,8 +66,8 @@
#define GPT2_CLK_SHIFT 11 #define GPT2_CLK_SHIFT 11
#define GPT3_CLK_SHIFT 12 #define GPT3_CLK_SHIFT 12
#define GPT_CLK_MASK 0x1 #define GPT_CLK_MASK 0x1
#define AUX_CLK_PLL3_MASK 0 #define AUX_CLK_PLL3_VAL 0
#define AUX_CLK_PLL1_MASK 1 #define AUX_CLK_PLL1_VAL 1
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) #define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
/* PERIP1_CLK_ENB register masks */ /* PERIP1_CLK_ENB register masks */
...@@ -123,6 +123,7 @@ ...@@ -123,6 +123,7 @@
#define RAS3_CLK_SYNT (MISC_BASE + 0x074) #define RAS3_CLK_SYNT (MISC_BASE + 0x074)
#define RAS4_CLK_SYNT (MISC_BASE + 0x078) #define RAS4_CLK_SYNT (MISC_BASE + 0x078)
/* aux clk synthesiser register masks for irda to ras4 */ /* aux clk synthesiser register masks for irda to ras4 */
#define AUX_SYNT_ENB 31
#define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_SHIFT 30
#define AUX_EQ_SEL_MASK 1 #define AUX_EQ_SEL_MASK 1
#define AUX_EQ1_SEL 0 #define AUX_EQ1_SEL 0
......
This diff is collapsed.
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
/* clk structure flags */ /* clk structure flags */
#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ #define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ #define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
/** /**
* struct clkops - clock operations * struct clkops - clock operations
...@@ -35,13 +36,11 @@ struct clkops { ...@@ -35,13 +36,11 @@ struct clkops {
/** /**
* struct pclk_info - parents info * struct pclk_info - parents info
* @pclk: pointer to parent clk * @pclk: pointer to parent clk
* @pclk_mask: value to be written for selecting this parent * @pclk_val: value to be written for selecting this parent
* @scalable: Is parent scalable (1 - YES, 0 - NO)
*/ */
struct pclk_info { struct pclk_info {
struct clk *pclk; struct clk *pclk;
u8 pclk_mask; u8 pclk_val;
u8 scalable;
}; };
/** /**
...@@ -58,6 +57,18 @@ struct pclk_sel { ...@@ -58,6 +57,18 @@ struct pclk_sel {
unsigned int pclk_sel_mask; unsigned int pclk_sel_mask;
}; };
/**
* struct rate_config - clk rate configurations
* @tbls: array of device specific clk rate tables, in ascending order of rates
* @count: size of tbls array
* @default_index: default setting when originally disabled
*/
struct rate_config {
void *tbls;
u8 count;
u8 default_index;
};
/** /**
* struct clk - clock structure * struct clk - clock structure
* @usage_count: num of users who enabled this clock * @usage_count: num of users who enabled this clock
...@@ -67,7 +78,10 @@ struct pclk_sel { ...@@ -67,7 +78,10 @@ struct pclk_sel {
* @en_reg_bit: clk enable/disable bit * @en_reg_bit: clk enable/disable bit
* @ops: clk enable/disable ops - generic_clkops selected if NULL * @ops: clk enable/disable ops - generic_clkops selected if NULL
* @recalc: pointer to clock rate recalculate function * @recalc: pointer to clock rate recalculate function
* @div_factor: division factor to parent clock. Only for recalc = follow_parent * @set_rate: pointer to clock set rate function
* @calc_rate: pointer to clock get rate function for index
* @rate_config: rate configuration information, used by set_rate
* @div_factor: division factor to parent clock.
* @pclk: current parent clk * @pclk: current parent clk
* @pclk_sel: pointer to parent selection structure * @pclk_sel: pointer to parent selection structure
* @pclk_sel_shift: register shift for selecting parent of this clock * @pclk_sel_shift: register shift for selecting parent of this clock
...@@ -82,7 +96,10 @@ struct clk { ...@@ -82,7 +96,10 @@ struct clk {
void __iomem *en_reg; void __iomem *en_reg;
u8 en_reg_bit; u8 en_reg_bit;
const struct clkops *ops; const struct clkops *ops;
void (*recalc) (struct clk *); int (*recalc) (struct clk *);
int (*set_rate) (struct clk *, unsigned long rate);
unsigned long (*calc_rate)(struct clk *, int index);
struct rate_config rate_config;
unsigned int div_factor; unsigned int div_factor;
struct clk *pclk; struct clk *pclk;
...@@ -115,6 +132,14 @@ struct pll_clk_config { ...@@ -115,6 +132,14 @@ struct pll_clk_config {
struct pll_clk_masks *masks; struct pll_clk_masks *masks;
}; };
/* pll clk rate config structure */
struct pll_rate_tbl {
u8 mode;
u16 m;
u8 n;
u8 p;
};
/* ahb and apb bus configuration structure */ /* ahb and apb bus configuration structure */
struct bus_clk_masks { struct bus_clk_masks {
u32 mask; u32 mask;
...@@ -126,6 +151,11 @@ struct bus_clk_config { ...@@ -126,6 +151,11 @@ struct bus_clk_config {
struct bus_clk_masks *masks; struct bus_clk_masks *masks;
}; };
/* ahb and apb clk bus rate config structure */
struct bus_rate_tbl {
u8 div;
};
/* Aux clk configuration structure: applicable to UART and FIRDA */ /* Aux clk configuration structure: applicable to UART and FIRDA */
struct aux_clk_masks { struct aux_clk_masks {
u32 eq_sel_mask; u32 eq_sel_mask;
...@@ -143,6 +173,13 @@ struct aux_clk_config { ...@@ -143,6 +173,13 @@ struct aux_clk_config {
struct aux_clk_masks *masks; struct aux_clk_masks *masks;
}; };
/* aux clk rate config structure */
struct aux_rate_tbl {
u16 xscale;
u16 yscale;
u8 eq;
};
/* GPT clk configuration structure */ /* GPT clk configuration structure */
struct gpt_clk_masks { struct gpt_clk_masks {
u32 mscale_sel_mask; u32 mscale_sel_mask;
...@@ -156,15 +193,48 @@ struct gpt_clk_config { ...@@ -156,15 +193,48 @@ struct gpt_clk_config {
struct gpt_clk_masks *masks; struct gpt_clk_masks *masks;
}; };
/* gpt clk rate config structure */
struct gpt_rate_tbl {
u16 mscale;
u16 nscale;
};
/* clcd clk configuration structure */
struct clcd_synth_masks {
u32 div_factor_mask;
u32 div_factor_shift;
};
struct clcd_clk_config {
void __iomem *synth_reg;
struct clcd_synth_masks *masks;
};
/* clcd clk rate config structure */
struct clcd_rate_tbl {
u16 div;
};
/* platform specific clock functions */ /* platform specific clock functions */
void clk_register(struct clk_lookup *cl); void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void); void recalc_root_clocks(void);
/* clock recalc functions */ /* clock recalc & set rate functions */
void follow_parent(struct clk *clk); int follow_parent(struct clk *clk);
void pll_clk_recalc(struct clk *clk); unsigned long pll_calc_rate(struct clk *clk, int index);
void bus_clk_recalc(struct clk *clk); int pll_clk_recalc(struct clk *clk);
void gpt_clk_recalc(struct clk *clk); int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
void aux_clk_recalc(struct clk *clk); unsigned long bus_calc_rate(struct clk *clk, int index);
int bus_clk_recalc(struct clk *clk);
int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long gpt_calc_rate(struct clk *clk, int index);
int gpt_clk_recalc(struct clk *clk);
int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long aux_calc_rate(struct clk *clk, int index);
int aux_clk_recalc(struct clk *clk);
int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
unsigned long clcd_calc_rate(struct clk *clk, int index);
int clcd_clk_recalc(struct clk *clk);
int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
#endif /* __PLAT_CLOCK_H */ #endif /* __PLAT_CLOCK_H */
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