Commit afeae6ef authored by Dikshita Agarwal's avatar Dikshita Agarwal Committed by Mauro Carvalho Chehab

media: venus: firmware: enable no tz fw loading for sc7280

Enable no tz FW loading and add routine to reset XTSS.
Signed-off-by: default avatarDikshita Agarwal <dikshita@codeaurora.org>
Signed-off-by: default avatarStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent e48b839b
...@@ -27,7 +27,12 @@ ...@@ -27,7 +27,12 @@
static void venus_reset_cpu(struct venus_core *core) static void venus_reset_cpu(struct venus_core *core)
{ {
u32 fw_size = core->fw.mapped_mem_size; u32 fw_size = core->fw.mapped_mem_size;
void __iomem *wrapper_base = core->wrapper_base; void __iomem *wrapper_base;
if (IS_V6(core))
wrapper_base = core->wrapper_tz_base;
else
wrapper_base = core->wrapper_base;
writel(0, wrapper_base + WRAPPER_FW_START_ADDR); writel(0, wrapper_base + WRAPPER_FW_START_ADDR);
writel(fw_size, wrapper_base + WRAPPER_FW_END_ADDR); writel(fw_size, wrapper_base + WRAPPER_FW_END_ADDR);
...@@ -35,11 +40,17 @@ static void venus_reset_cpu(struct venus_core *core) ...@@ -35,11 +40,17 @@ static void venus_reset_cpu(struct venus_core *core)
writel(fw_size, wrapper_base + WRAPPER_CPA_END_ADDR); writel(fw_size, wrapper_base + WRAPPER_CPA_END_ADDR);
writel(fw_size, wrapper_base + WRAPPER_NONPIX_START_ADDR); writel(fw_size, wrapper_base + WRAPPER_NONPIX_START_ADDR);
writel(fw_size, wrapper_base + WRAPPER_NONPIX_END_ADDR); writel(fw_size, wrapper_base + WRAPPER_NONPIX_END_ADDR);
if (IS_V6(core)) {
/* Bring XTSS out of reset */
writel(0, wrapper_base + WRAPPER_TZ_XTSS_SW_RESET);
} else {
writel(0x0, wrapper_base + WRAPPER_CPU_CGC_DIS); writel(0x0, wrapper_base + WRAPPER_CPU_CGC_DIS);
writel(0x0, wrapper_base + WRAPPER_CPU_CLOCK_CONFIG); writel(0x0, wrapper_base + WRAPPER_CPU_CLOCK_CONFIG);
/* Bring ARM9 out of reset */ /* Bring ARM9 out of reset */
writel(0, wrapper_base + WRAPPER_A9SS_SW_RESET); writel(0, wrapper_base + WRAPPER_A9SS_SW_RESET);
}
} }
int venus_set_hw_state(struct venus_core *core, bool resume) int venus_set_hw_state(struct venus_core *core, bool resume)
...@@ -56,7 +67,9 @@ int venus_set_hw_state(struct venus_core *core, bool resume) ...@@ -56,7 +67,9 @@ int venus_set_hw_state(struct venus_core *core, bool resume)
if (resume) { if (resume) {
venus_reset_cpu(core); venus_reset_cpu(core);
} else { } else {
if (!IS_V6(core)) if (IS_V6(core))
writel(1, core->wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
else
writel(1, core->wrapper_base + WRAPPER_A9SS_SW_RESET); writel(1, core->wrapper_base + WRAPPER_A9SS_SW_RESET);
} }
...@@ -162,12 +175,19 @@ static int venus_shutdown_no_tz(struct venus_core *core) ...@@ -162,12 +175,19 @@ static int venus_shutdown_no_tz(struct venus_core *core)
u32 reg; u32 reg;
struct device *dev = core->fw.dev; struct device *dev = core->fw.dev;
void __iomem *wrapper_base = core->wrapper_base; void __iomem *wrapper_base = core->wrapper_base;
void __iomem *wrapper_tz_base = core->wrapper_tz_base;
if (IS_V6(core)) {
/* Assert the reset to XTSS */
reg = readl_relaxed(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
reg |= WRAPPER_XTSS_SW_RESET_BIT;
writel_relaxed(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
} else {
/* Assert the reset to ARM9 */ /* Assert the reset to ARM9 */
reg = readl_relaxed(wrapper_base + WRAPPER_A9SS_SW_RESET); reg = readl_relaxed(wrapper_base + WRAPPER_A9SS_SW_RESET);
reg |= WRAPPER_A9SS_SW_RESET_BIT; reg |= WRAPPER_A9SS_SW_RESET_BIT;
writel_relaxed(reg, wrapper_base + WRAPPER_A9SS_SW_RESET); writel_relaxed(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
}
/* Make sure reset is asserted before the mapping is removed */ /* Make sure reset is asserted before the mapping is removed */
mb(); mb();
......
...@@ -149,6 +149,8 @@ ...@@ -149,6 +149,8 @@
/* Wrapper TZ 6xx */ /* Wrapper TZ 6xx */
#define WRAPPER_TZ_BASE_V6 0x000c0000 #define WRAPPER_TZ_BASE_V6 0x000c0000
#define WRAPPER_TZ_CPU_STATUS_V6 0x10 #define WRAPPER_TZ_CPU_STATUS_V6 0x10
#define WRAPPER_TZ_XTSS_SW_RESET 0x1000
#define WRAPPER_XTSS_SW_RESET_BIT BIT(0)
/* Venus AON */ /* Venus AON */
#define AON_BASE_V6 0x000e0000 #define AON_BASE_V6 0x000e0000
......
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