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Commit b0516dbf authored by Adam Skladowski's avatar Adam Skladowski Committed by Bjorn Andersson
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arm64: dts: qcom: msm8976: Add MDSS nodes 

Add MDSS nodes to support displays on MSM8976 SoC.
Signed-off-by: default avatarAdam Skladowski <a39.skl@gmail.com>
Link: https://lore.kernel.org/r/20240508163455.8757-3-a39.skl@gmail.comSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 418c2ffd
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Showing with 276 additions and 4 deletions
arch/arm64/boot/dts/qcom/msm8976.dtsi
View file @ b0516dbf
......@@ -785,10 +785,10 @@ gcc: clock-controller@1800000 {
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<0>,
<0>,
<0>,
<0>;
<&mdss_dsi0_phy 1>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_dsi1_phy 0>;
clock-names = "xo",
"xo_a",
"dsi0pll",
......@@ -808,6 +808,278 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x30000>;
};
mdss: display-subsystem@1a00000 {
compatible = "qcom,mdss";
reg = <0x01a00000 0x1000>,
<0x01ab0000 0x3000>;
reg-names = "mdss_phys", "vbif_phys";
power-domains = <&gcc MDSS_GDSC>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>;
clock-names = "iface",
"bus",
"vsync",
"core";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdss_mdp: display-controller@1a01000 {
compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDP_TBU_CLK>,
<&gcc GCC_MDP_RT_TBU_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync",
"tbu",
"tbu_rt";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&gcc MDSS_GDSC>;
iommus = <&apps_iommu 22>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_mdp5_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
mdss_mdp5_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-177780000 {
opp-hz = /bits/ 64 <177780000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-320000000 {
opp-hz = /bits/ 64 <320000000>;
required-opps = <&rpmpd_opp_nom>;
};
opp-360000000 {
opp-hz = /bits/ 64 <360000000>;
required-opps = <&rpmpd_opp_turbo>;
};
};
};
mdss_dsi0: dsi@1a94000 {
compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x01a94000 0x300>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core";
assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
<&gcc GCC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
phys = <&mdss_dsi0_phy>;
operating-points-v2 = <&dsi0_opp_table>;
power-domains = <&gcc MDSS_GDSC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&mdss_mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
dsi0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-125000000 {
opp-hz = /bits/ 64 <125000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-161250000 {
opp-hz = /bits/ 64 <161250000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmpd_opp_nom>;
};
};
};
mdss_dsi1: dsi@1a96000 {
compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x01a96000 0x300>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE1_CLK>,
<&gcc GCC_MDSS_PCLK1_CLK>,
<&gcc GCC_MDSS_ESC1_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core";
assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
<&gcc GCC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>;
phys = <&mdss_dsi1_phy>;
operating-points-v2 = <&dsi0_opp_table>;
power-domains = <&gcc MDSS_GDSC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi1_in: endpoint {
remote-endpoint = <&mdss_mdp5_intf2_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi1_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@1a94a00 {
compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
reg = <0x01a94a00 0xd4>,
<0x01a94400 0x280>,
<0x01a94b80 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss_dsi1_phy: phy@1a96a00 {
compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
reg = <0x01a96a00 0xd4>,
<0x01a96400 0x280>,
<0x01a96b80 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
};
apps_iommu: iommu@1ee0000 {
compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
reg = <0x01ee0000 0x3000>;
......
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