Commit b0b6a28b authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.20 series:

  There were no significant changes to the core this time! Bur the new
  Qualcomm, Mediatek and Broadcom drivers are quite interesting as they
  will be used in a few million embedded devices the coming years as it
  seems.

  New drivers:

   - Broadcom Northstar pin control driver.

   - Mediatek MT8183 subdriver.

   - Mediatek MT7623 subdriver.

   - Mediatek MT6765 subdriver.

   - Meson g12a subdriver.

   - Nuvoton NPCM7xx pin control and GPIO driver.

   - Qualcomm QCS404 pin control and GPIO subdriver.

   - Qualcomm SDM660 pin control and GPIO subdriver.

   - Renesas R8A7744 PFC subdriver.

   - Renesas R8A774C0 PFC subdriver.

   - Renesas RZ/N1 pinctrl driver

  Major improvements:

   - Pulled the GPIO support for Ingenic over from the GPIO subsystem
     and consolidated it all in the Ingenic pin control driver.

   - Major cleanups and consolidation work in all Intel drivers.

   - Major cleanups and consolidation work in all Mediatek drivers.

   - Lots of incremental improvements to the Renesas PFC pin controller
     family.

   - All drivers doing GPIO now include <linux/gpio/driver.h> and
     nothing else"

* tag 'pinctrl-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits)
  pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'
  gpio: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
  pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>
  dt-bindings: pinctrl: bcm4708-pinmux: improve example binding
  pinctrl: geminilake: Sort register offsets by value
  pinctrl: geminilake: Get rid of unneeded ->probe() stub
  pinctrl: geminilake: Update pin list for B0 stepping
  pinctrl: renesas: Fix platform_no_drv_owner.cocci warnings
  pinctrl: mediatek: Make eint_m u16
  pinctrl: bcm: ns: Use uintptr_t for casting data
  pinctrl: madera: Fix uninitialized variable bug in madera_mux_set_mux
  pinctrl: gemini: Fix up TVC clock group
  pinctrl: gemini: Drop noisy debug prints
  pinctrl: gemini: Mask and set properly
  pinctrl: mediatek: select GPIOLIB
  pinctrl: rza1: don't manually release devm managed resources
  MAINTAINERS: update entry for Mediatek pin controller
  pinctrl: bcm: add Northstar driver
  dt-bindings: pinctrl: document Broadcom Northstar pin mux controller
  pinctrl: qcom: fix 'const' pointer handling
  ...
parents 1650ac53 a93a676b
Ingenic jz47xx GPIO controller
That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
driver node.
Required properties:
--------------------
- compatible: Must contain one of:
- "ingenic,jz4740-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
- reg: The GPIO bank number.
- interrupt-controller: Marks the device node as an interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- #interrupt-cells: Should be 2. Refer to
../interrupt-controller/interrupts.txt for more details.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
'gpio.txt' in this directory for more details.
Example:
--------
&pinctrl {
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4740-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <28>;
};
};
Broadcom Northstar pins mux controller
Some of Northstar SoCs's pins can be used for various purposes thanks to the mux
controller. This binding allows describing mux controller and listing available
functions. They can be referenced later by other bindings to let system
configure controller correctly.
A list of pins varies across chipsets so few bindings are available.
Required properties:
- compatible: must be one of:
"brcm,bcm4708-pinmux"
"brcm,bcm4709-pinmux"
"brcm,bcm53012-pinmux"
- reg: iomem address range of CRU (Central Resource Unit) pin registers
- reg-names: "cru_gpio_control" - the only needed & supported reg right now
Functions and their groups available for all chipsets:
- "spi": "spi_grp"
- "i2c": "i2c_grp"
- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
- "uart1": "uart1_grp"
Additionally available on BCM4709 and BCM53012:
- "mdio": "mdio_grp"
- "uart2": "uart2_grp"
- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
For documentation of subnodes see:
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Example:
dmu@1800c000 {
compatible = "simple-bus";
ranges = <0 0x1800c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
cru@100 {
compatible = "simple-bus";
reg = <0x100 0x1a4>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
pin-controller@1c0 {
compatible = "brcm,bcm4708-pinmux";
reg = <0x1c0 0x24>;
reg-names = "cru_gpio_control";
spi-pins {
function = "spi";
groups = "spi_grp";
};
};
};
};
...@@ -20,16 +20,30 @@ Required properties: ...@@ -20,16 +20,30 @@ Required properties:
- compatible: One of: - compatible: One of:
- "ingenic,jz4740-pinctrl" - "ingenic,jz4740-pinctrl"
- "ingenic,jz4725b-pinctrl"
- "ingenic,jz4770-pinctrl" - "ingenic,jz4770-pinctrl"
- "ingenic,jz4780-pinctrl" - "ingenic,jz4780-pinctrl"
- reg: Address range of the pinctrl registers. - reg: Address range of the pinctrl registers.
GPIO sub-nodes Required properties for sub-nodes (GPIO chips):
-------------- -----------------------------------------------
The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver; - compatible: Must contain one of:
please refer to ../gpio/ingenic,gpio.txt. - "ingenic,jz4740-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
- reg: The GPIO bank number.
- interrupt-controller: Marks the device node as an interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- #interrupt-cells: Should be 2. Refer to
../interrupt-controller/interrupts.txt for more details.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
../gpio/gpio.txt for more details.
Example: Example:
...@@ -38,4 +52,21 @@ Example: ...@@ -38,4 +52,21 @@ Example:
pinctrl: pin-controller@10010000 { pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4740-pinctrl"; compatible = "ingenic,jz4740-pinctrl";
reg = <0x10010000 0x400>; reg = <0x10010000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4740-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <28>;
};
}; };
...@@ -13,6 +13,8 @@ Required properties for the root node: ...@@ -13,6 +13,8 @@ Required properties for the root node:
"amlogic,meson-gxl-aobus-pinctrl" "amlogic,meson-gxl-aobus-pinctrl"
"amlogic,meson-axg-periphs-pinctrl" "amlogic,meson-axg-periphs-pinctrl"
"amlogic,meson-axg-aobus-pinctrl" "amlogic,meson-axg-aobus-pinctrl"
"amlogic,meson-g12a-periphs-pinctrl"
"amlogic,meson-g12a-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality - reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes === === GPIO sub-nodes ===
......
Nuvoton NPCM7XX Pin Controllers
The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
the multiplexing block, Each pin supports GPIO functionality (GPIOx)
and multiple functions that directly connect the pin to different
hardware blocks.
Required properties:
- #address-cells : should be 1.
- #size-cells : should be 1.
- compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
- ranges : defines mapping ranges between pin controller node (parent)
to GPIO bank node (children).
=== GPIO Bank Subnode ===
The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
Required GPIO Bank subnode-properties:
- reg : specifies physical base address and size of the GPIO
bank registers.
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Must be <2>. The first cell is the gpio pin number
and the second cell is used for optional parameters.
- interrupts : contain the GPIO bank interrupt with flags for falling edge.
- gpio-ranges : defines the range of pins managed by the GPIO bank controller.
For example, GPIO bank subnodes like the following:
gpio0: gpio@f0010000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x80>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 0 32>;
};
=== Pin Mux Subnode ===
- pin: A string containing the name of the pin
An array of strings, each string containing the name of a pin.
These pin are used for selecting pin configuration.
The following are the list of pins available:
"GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
"GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL", "GPIO6/IOX2CK/SMB2DSDA",
"GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2", "GPIO10/IOXHLD",
"GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
"GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
"GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA", "GPIO19/PSPI2CK/SMB4BSCL",
"GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL", "GPIO22/SMB4DSDA/SMB14SDA",
"GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI", "GPIO26/SMB5SDA",
"GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
"GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3", "GPIO37/SMB3CSDA",
"GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL", "GPIO41/BSPRXD",
"GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD", "GPIO44/nCTS1/JTDI2/BU1CTS",
"GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
"GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2", "GPO51/nRTS2/STRAP2",
"GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2", "GPIO55/nRI2",
"GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
"GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
"GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
"GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6", "GPIO71/FANIN7",
"GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
"GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
"GPIO80/PWM0", "GPIO81/PWM1", "GPIO82/PWM2", "GPIO83/PWM3", "GPIO84/R2TXD0",
"GPIO85/R2TXD1", "GPIO86/R2TXEN", "GPIO87/R2RXD0", "GPIO88/R2RXD1", "GPIO89/R2CRSDV",
"GPIO90/R2RXERR", "GPIO91/R2MDC", "GPIO92/R2MDIO", "GPIO93/GA20/SMB5DSCL",
"GPIO94/nKBRST/SMB5DSDA", "GPIO95/nLRESET/nESPIRST", "GPIO96/RG1TXD0",
"GPIO97/RG1TXD1", "GPIO98/RG1TXD2", "GPIO99/RG1TXD3","GPIO100/RG1TXC",
"GPIO101/RG1TXCTL", "GPIO102/RG1RXD0", "GPIO103/RG1RXD1", "GPIO104/RG1RXD2",
"GPIO105/RG1RXD3", "GPIO106/RG1RXC", "GPIO107/RG1RXCTL", "GPIO108/RG1MDC",
"GPIO109/RG1MDIO", "GPIO110/RG2TXD0/DDRV0", "GPIO111/RG2TXD1/DDRV1",
"GPIO112/RG2TXD2/DDRV2", "GPIO113/RG2TXD3/DDRV3", "GPIO114/SMB0SCL",
"GPIO115/SMB0SDA", "GPIO116/SMB1SCL", "GPIO117/SMB1SDA", "GPIO118/SMB2SCL",
"GPIO119/SMB2SDA", "GPIO120/SMB2CSDA", "GPIO121/SMB2CSCL", "GPIO122/SMB2BSDA",
"GPIO123/SMB2BSCL", "GPIO124/SMB1CSDA", "GPIO125/SMB1CSCL","GPIO126/SMB1BSDA",
"GPIO127/SMB1BSCL", "GPIO128/SMB8SCL", "GPIO129/SMB8SDA", "GPIO130/SMB9SCL",
"GPIO131/SMB9SDA", "GPIO132/SMB10SCL", "GPIO133/SMB10SDA","GPIO134/SMB11SCL",
"GPIO135/SMB11SDA", "GPIO136/SD1DT0", "GPIO137/SD1DT1", "GPIO138/SD1DT2",
"GPIO139/SD1DT3", "GPIO140/SD1CLK", "GPIO141/SD1WP", "GPIO142/SD1CMD",
"GPIO143/SD1CD/SD1PWR", "GPIO144/PWM4", "GPIO145/PWM5", "GPIO146/PWM6",
"GPIO147/PWM7", "GPIO148/MMCDT4", "GPIO149/MMCDT5", "GPIO150/MMCDT6",
"GPIO151/MMCDT7", "GPIO152/MMCCLK", "GPIO153/MMCWP", "GPIO154/MMCCMD",
"GPIO155/nMMCCD/nMMCRST", "GPIO156/MMCDT0", "GPIO157/MMCDT1", "GPIO158/MMCDT2",
"GPIO159/MMCDT3", "GPIO160/CLKOUT/RNGOSCOUT", "GPIO161/nLFRAME/nESPICS",
"GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0",
"GPIO165/LAD1/ESPI_IO1", "GPIO166/LAD2/ESPI_IO2", "GPIO167/LAD3/ESPI_IO3",
"GPIO168/nCLKRUN/nESPIALERT", "GPIO169/nSCIPME", "GPIO170/nSMI", "GPIO171/SMB6SCL",
"GPIO172/SMB6SDA", "GPIO173/SMB7SCL", "GPIO174/SMB7SDA", "GPIO175/PSPI1CK/FANIN19",
"GPIO176/PSPI1DO/FANIN18", "GPIO177/PSPI1DI/FANIN17", "GPIO178/R1TXD0",
"GPIO179/R1TXD1", "GPIO180/R1TXEN", "GPIO181/R1RXD0", "GPIO182/R1RXD1",
"GPIO183/SPI3CK", "GPO184/SPI3D0/STRAP9", "GPO185/SPI3D1/STRAP10",
"GPIO186/nSPI3CS0", "GPIO187/nSPI3CS1", "GPIO188/SPI3D2/nSPI3CS2",
"GPIO189/SPI3D3/nSPI3CS3", "GPIO190/nPRD_SMI", "GPIO191", "GPIO192", "GPIO193/R1CRSDV",
"GPIO194/SMB0BSCL", "GPIO195/SMB0BSDA", "GPIO196/SMB0CSCL", "GPIO197/SMB0DEN",
"GPIO198/SMB0DSDA", "GPIO199/SMB0DSCL", "GPIO200/R2CK", "GPIO201/R1CK",
"GPIO202/SMB0CSDA", "GPIO203/FANIN16", "GPIO204/DDC2SCL", "GPIO205/DDC2SDA",
"GPIO206/HSYNC2", "GPIO207/VSYNC2", "GPIO208/RG2TXC/DVCK", "GPIO209/RG2TXCTL/DDRV4",
"GPIO210/RG2RXD0/DDRV5", "GPIO211/RG2RXD1/DDRV6", "GPIO212/RG2RXD2/DDRV7",
"GPIO213/RG2RXD3/DDRV8", "GPIO214/RG2RXC/DDRV9", "GPIO215/RG2RXCTL/DDRV10",
"GPIO216/RG2MDC/DDRV11", "GPIO217/RG2MDIO/DVHSYNC", "GPIO218/nWDO1",
"GPIO219/nWDO2", "GPIO220/SMB12SCL", "GPIO221/SMB12SDA", "GPIO222/SMB13SCL",
"GPIO223/SMB13SDA", "GPIO224/SPIXCK", "GPO225/SPIXD0/STRAP12", "GPO226/SPIXD1/STRAP13",
"GPIO227/nSPIXCS0", "GPIO228/nSPIXCS1", "GPO229/SPIXD2/STRAP3", "GPIO230/SPIXD3",
"GPIO231/nCLKREQ", "GPI255/DACOSEL"
Optional Properties:
bias-disable, bias-pull-down, bias-pull-up, input-enable,
input-disable, output-high, output-low, drive-push-pull,
drive-open-drain, input-debounce, slew-rate, drive-strength
slew-rate valid arguments are:
<0> - slow
<1> - fast
drive-strength valid arguments are:
<2> - 2mA
<4> - 4mA
<8> - 8mA
<12> - 12mA
<16> - 16mA
<24> - 24mA
For example, pinctrl might have pinmux subnodes like the following:
gpio0_iox1d1_pin: gpio0-iox1d1-pin {
pins = "GPIO0/IOX1DI";
output-high;
};
gpio0_iox1ck_pin: gpio0-iox1ck-pin {
pins = "GPIO2/IOX1CK";
output_high;
};
=== Pin Group Subnode ===
Required pin group subnode-properties:
- groups : A string containing the name of the group to mux.
- function: A string containing the name of the function to mux to the
group.
The following are the list of the available groups and functions :
smb0, smb0b, smb0c, smb0d, smb0den, smb1, smb1b, smb1c, smb1d,
smb2, smb2b, smb2c, smb2d, smb3, smb3b, smb3c, smb3d, smb4, smb4b,
smb4c, smb4d, smb4den, smb5, smb5b, smb5c, smb5d, ga20kbc, smb6,
smb7, smb8, smb9, smb10, smb11, smb12, smb13, smb14, smb15, fanin0,
fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8,
fanin9, fanin10, fanin11 fanin12 fanin13, fanin14, fanin15, faninx,
pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, rg1, rg1mdio, rg2,
rg2mdio, ddr, uart1, uart2, bmcuart0a, bmcuart0b, bmcuart1, iox1,
iox2, ioxh, gspi, mmc, mmcwp, mmccd, mmcrst, mmc8, r1, r1err, r1md,
r2, r2err, r2md, sd1, sd1pwr, wdog1, wdog2, scipme, sci, serirq,
jtag2, spix, spixcs1, pspi1, pspi2, ddc, clkreq, clkout, spi3, spi3cs1,
spi3quad, spi3cs2, spi3cs3, spi0cs1, lpc, lpcclk, espi, lkgpo0, lkgpo1,
lkgpo2, nprd_smi
For example, pinctrl might have group subnodes like the following:
r1err_pins: r1err-pins {
groups = "r1err";
function = "r1err";
};
r1md_pins: r1md-pins {
groups = "r1md";
function = "r1md";
};
r1_pins: r1-pins {
groups = "r1";
function = "r1";
};
Examples
========
pinctrl: pinctrl@f0800000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nuvoton,npcm750-pinctrl";
ranges = <0 0xf0010000 0x8000>;
gpio0: gpio@f0010000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x80>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 0 32>;
};
....
gpio7: gpio@f0017000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x7000 0x80>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 224 32>;
};
gpio0_iox1d1_pin: gpio0-iox1d1-pin {
pins = "GPIO0/IOX1DI";
output-high;
};
iox1_pins: iox1-pins {
groups = "iox1";
function = "iox1";
};
iox2_pins: iox2-pins {
groups = "iox2";
function = "iox2";
};
....
clkreq_pins: clkreq-pins {
groups = "clkreq";
function = "clkreq";
};
};
\ No newline at end of file
...@@ -19,6 +19,7 @@ PMIC's from Qualcomm. ...@@ -19,6 +19,7 @@ PMIC's from Qualcomm.
"qcom,pm8998-gpio" "qcom,pm8998-gpio"
"qcom,pma8084-gpio" "qcom,pma8084-gpio"
"qcom,pmi8994-gpio" "qcom,pmi8994-gpio"
"qcom,pms405-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively if the device is on an spmi bus or an ssbi bus respectively
...@@ -91,6 +92,7 @@ to specify in a pin configuration subnode: ...@@ -91,6 +92,7 @@ to specify in a pin configuration subnode:
gpio1-gpio26 for pm8998 gpio1-gpio26 for pm8998
gpio1-gpio22 for pma8084 gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994 gpio1-gpio10 for pmi8994
gpio1-gpio11 for pms405
- function: - function:
Usage: required Usage: required
......
Qualcomm QCS404 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
QCS404 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,qcs404-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the north, south and east TLMM
tiles.
- reg-names:
Usage: required
Value type: <stringlist>
Defintiion: names for the cells of reg, must contain "north", "south"
and "east".
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio119
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data
Supports bias and drive-strength
ufs_reset
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
gpio, hdmi_tx, hdmi_ddc, blsp_uart_tx_a2, blsp_spi2, m_voc,
qdss_cti_trig_in_a0, blsp_uart_rx_a2, qdss_tracectl_a,
blsp_uart2, aud_cdc, blsp_i2c_sda_a2, qdss_tracedata_a,
blsp_i2c_scl_a2, qdss_tracectl_b, qdss_cti_trig_in_b0,
blsp_uart1, blsp_spi_mosi_a1, blsp_spi_miso_a1,
qdss_tracedata_b, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest,
blsp_spi_clk_a1, rgb_data0, blsp_uart5, blsp_spi5,
adsp_ext, rgb_data1, prng_rosc, rgb_data2, blsp_i2c5,
gcc_gp1_clk_b, rgb_data3, gcc_gp2_clk_b, blsp_spi0,
blsp_uart0, gcc_gp3_clk_b, blsp_i2c0, qdss_traceclk_b,
pcie_clk, nfc_irq, blsp_spi4, nfc_dwl, audio_ts, rgb_data4,
spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, rgb_data5,
blsp_uart_rx_b2, blsp_i2c_sda_b2, blsp_i2c_scl_b2,
pwm_led11, i2s_3_data0_a, ebi2_lcd, i2s_3_data1_a,
i2s_3_data2_a, atest_char, pwm_led3, i2s_3_data3_a,
pwm_led4, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, pwm_led6,
pwm_led7, pwm_led8, pwm_led24, spkr_dac0, blsp_i2c4,
pwm_led9, pwm_led10, spdifrx_opt, pwm_led12, pwm_led13,
pwm_led14, wlan1_adc1, rgb_data_b0, pwm_led15,
blsp_spi_mosi_b1, wlan1_adc0, rgb_data_b1, pwm_led16,
blsp_spi_miso_b1, qdss_cti_trig_out_b0, wlan2_adc1,
rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, wlan2_adc0,
rgb_data_b3, pwm_led18, blsp_spi_clk_b1, rgb_data_b4,
pwm_led19, ext_mclk1_b, qdss_traceclk_a, rgb_data_b5,
pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0,
rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, rgb_vsync,
i2s_3_data0_b, ldo_en, hdmi_dtest, rgb_de, i2s_3_data1_b,
hdmi_lbk9, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc,
hdmi_lbk8, rgb_mdp, atest_char0, i2s_3_data3_b, hdmi_lbk7,
rgb_data_b6, rgb_data_b7, hdmi_lbk6, rgmii_int, cri_trng1,
rgmii_wol, cri_trng0, gcc_tlmm, rgmii_ck, rgmii_tx,
hdmi_lbk5, hdmi_pixel, hdmi_rcv, hdmi_lbk4, rgmii_ctl,
ext_lpass, rgmii_rx, cri_trng, hdmi_lbk3, hdmi_lbk2,
qdss_cti_trig_out_b1, rgmii_mdio, hdmi_lbk1, rgmii_mdc,
hdmi_lbk0, ir_in, wsa_en, rgb_data6, rgb_data7,
atest_char2, ebi_ch0, blsp_uart3, blsp_spi3, sd_write,
blsp_i2c3, gcc_gp1_clk_a, qdss_cti_trig_in_b1,
gcc_gp2_clk_a, ext_mclk0, mclk_in1, i2s_1, dsd_clk_a,
qdss_cti_trig_in_a1, rgmi_dll1, pwm_led22, pwm_led23,
qdss_cti_trig_out_a0, rgmi_dll2, pwm_led1,
qdss_cti_trig_out_a1, pwm_led2, i2s_2, pll_bist,
ext_mclk1_a, mclk_in2, bimc_dte1, i2s_3_sck_a, i2s_3_ws_a
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,qcs404-pinctrl";
reg = <0x01000000 0x200000>,
<0x01300000 0x200000>,
<0x07b00000 0x200000>;
reg-names = "south", "north", "east";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 120>;
interrupt-controller;
#interrupt-cells = <2>;
};
Qualcomm Technologies, Inc. SDM660 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
SDM660 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,sdm660-pinctrl" or
"qcom,sdm630-pinctrl".
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the north, center and south
TLMM tiles.
- reg-names:
Usage: required
Value type: <stringlist>
Definition: names for the cells of reg, must contain "north", "center"
and "south".
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- gpio-ranges:
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies the mapping between gpio controller and
pin-controller pins.
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio113,
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk,
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
atest_usb11, atest_usb12, atest_usb13, atest_usb2,
atest_usb20, atest_usb21, atest_usb22, atest_usb23,
audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2,
blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
blsp_i2c8_a, blsp_i2c8_b, blsp_spi1, blsp_spi2, blsp_spi3,
blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi4, blsp_spi5,
blsp_spi6, blsp_spi7, blsp_spi8_a, blsp_spi8_b,
blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, blsp_uart2,
blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async,
cci_i2c, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
phase_flag1, phase_flag10, phase_flag11, phase_flag12,
phase_flag13, phase_flag14, phase_flag15, phase_flag16,
phase_flag17, phase_flag18, phase_flag19, phase_flag2,
phase_flag20, phase_flag21, phase_flag22, phase_flag23,
phase_flag24, phase_flag25, phase_flag26, phase_flag27,
phase_flag28, phase_flag29, phase_flag3, phase_flag30,
phase_flag31, phase_flag4, phase_flag5, phase_flag6,
phase_flag7, phase_flag8, phase_flag9, pll_bypassnl,
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto,
pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a,
qdss_cti1_b, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10,
qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request,
qspi_clk, qspi_cs, qspi_data0, qspi_data1, qspi_data2,
qspi_data3, qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data,
sp_cmu, ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2,
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
uim2_data, uim2_present, uim2_reset, uim_batt, vfr_1,
vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@3100000 {
compatible = "qcom,sdm660-pinctrl";
reg = <0x3100000 0x200000>,
<0x3500000 0x200000>,
<0x3900000 0x200000>;
reg-names = "south", "center", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 114>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...@@ -14,8 +14,11 @@ Required Properties: ...@@ -14,8 +14,11 @@ Required Properties:
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
......
Renesas RZ/N1 SoC Pinctrl node description.
Pin controller node
-------------------
Required properties:
- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
strings must be one of:
"renesas,r9a06g032-pinctrl" for RZ/N1D
"renesas,r9a06g033-pinctrl" for RZ/N1S
- reg: Address base and length of the memory area where the pin controller
hardware is mapped to.
- clocks: phandle for the clock, see the description of clock-names below.
- clock-names: Contains the name of the clock:
"bus", the bus clock, sometimes described as pclk, for register accesses.
Example:
pinctrl: pin-controller@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
node-3 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the latter two formats when pins part of the same logical group need to
have different generic pin configuration flags applied. Note that the generic
pinconfig in node-3 does not apply to the sub-nodes.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is
one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1 and
Level 2 numbers that are detailed in the hardware reference manual into a
single number. The identifiers for Level 2 are simply offset by 10.
Additional identifiers are provided to specify the MDIO source peripheral.
Optional generic pinconf properties:
- bias-disable - disable any pin bias
- bias-pull-up - pull up the pin with 50 KOhm
- bias-pull-down - pull down the pin with 50 KOhm
- bias-high-impedance - high impedance mode
- drive-strength - sink or source at most 4, 6, 8 or 12 mA
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
};
Example 2:
Here we set the pull up on the RXD pin of the UART.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */
bias-pull-up;
};
};
};
...@@ -11519,15 +11519,12 @@ S: Maintained ...@@ -11519,15 +11519,12 @@ S: Maintained
F: drivers/pinctrl/intel/ F: drivers/pinctrl/intel/
PIN CONTROLLER - MEDIATEK PIN CONTROLLER - MEDIATEK
M: Sean Wang <sean.wang@mediatek.com> M: Sean Wang <sean.wang@kernel.org>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
F: drivers/pinctrl/mediatek/mtk-eint.* F: drivers/pinctrl/mediatek/
F: drivers/pinctrl/mediatek/pinctrl-mtk-common.*
F: drivers/pinctrl/mediatek/pinctrl-mt2701.c
F: drivers/pinctrl/mediatek/pinctrl-mt7622.c
PIN CONTROLLER - QUALCOMM PIN CONTROLLER - QUALCOMM
M: Bjorn Andersson <bjorn.andersson@linaro.org> M: Bjorn Andersson <bjorn.andersson@linaro.org>
......
...@@ -267,17 +267,6 @@ config GPIO_ICH ...@@ -267,17 +267,6 @@ config GPIO_ICH
If unsure, say N. If unsure, say N.
config GPIO_INGENIC
tristate "Ingenic JZ47xx SoCs GPIO support"
depends on OF
depends on MACH_INGENIC || COMPILE_TEST
select GPIOLIB_IRQCHIP
help
Say yes here to support the GPIO functionality present on the
JZ4740 and JZ4780 SoCs from Ingenic.
If unsure, say N.
config GPIO_IOP config GPIO_IOP
tristate "Intel IOP GPIO" tristate "Intel IOP GPIO"
depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST
......
...@@ -57,7 +57,6 @@ obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o ...@@ -57,7 +57,6 @@ obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o
obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
obj-$(CONFIG_GPIO_ICH) += gpio-ich.o obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
obj-$(CONFIG_GPIO_INGENIC) += gpio-ingenic.o
obj-$(CONFIG_GPIO_IOP) += gpio-iop.o obj-$(CONFIG_GPIO_IOP) += gpio-iop.o
obj-$(CONFIG_GPIO_IT87) += gpio-it87.o obj-$(CONFIG_GPIO_IT87) += gpio-it87.o
obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
......
This diff is collapsed.
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <linux/bitops.h> #include <linux/bits.h>
#include <linux/gpio/driver.h> #include <linux/gpio/driver.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
......
...@@ -195,6 +195,16 @@ config PINCTRL_RZA1 ...@@ -195,6 +195,16 @@ config PINCTRL_RZA1
help help
This selects pinctrl driver for Renesas RZ/A1 platforms. This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
depends on ARCH_RZN1 || COMPILE_TEST
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/N1 devices.
config PINCTRL_SINGLE config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver" tristate "One-register-per-pin type device tree based pinctrl driver"
depends on OF depends on OF
...@@ -309,12 +319,14 @@ config PINCTRL_ZYNQ ...@@ -309,12 +319,14 @@ config PINCTRL_ZYNQ
config PINCTRL_INGENIC config PINCTRL_INGENIC
bool "Pinctrl driver for the Ingenic JZ47xx SoCs" bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
default y default MACH_INGENIC
depends on OF depends on OF
depends on MACH_INGENIC || COMPILE_TEST depends on MIPS || COMPILE_TEST
select GENERIC_PINCONF select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select GPIOLIB_IRQCHIP
select REGMAP_MMIO select REGMAP_MMIO
config PINCTRL_RK805 config PINCTRL_RK805
...@@ -346,6 +358,7 @@ source "drivers/pinctrl/freescale/Kconfig" ...@@ -346,6 +358,7 @@ source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/samsung/Kconfig"
......
...@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o ...@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
...@@ -51,6 +52,7 @@ obj-y += freescale/ ...@@ -51,6 +52,7 @@ obj-y += freescale/
obj-$(CONFIG_X86) += intel/ obj-$(CONFIG_X86) += intel/
obj-y += mvebu/ obj-y += mvebu/
obj-y += nomadik/ obj-y += nomadik/
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
......
...@@ -715,7 +715,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, ...@@ -715,7 +715,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg); pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg);
if (unlikely(WARN_ON(!pmap))) if (WARN_ON(!pmap))
return -EINVAL; return -EINVAL;
val = pmap->val << pconf->bit; val = pmap->val << pconf->bit;
......
...@@ -73,6 +73,19 @@ config PINCTRL_CYGNUS_MUX ...@@ -73,6 +73,19 @@ config PINCTRL_CYGNUS_MUX
configuration, with the exception that certain individual pins configuration, with the exception that certain individual pins
can be overridden to GPIO function can be overridden to GPIO function
config PINCTRL_NS
bool "Broadcom Northstar pins driver"
depends on OF && (ARCH_BCM_5301X || COMPILE_TEST)
select PINMUX
select GENERIC_PINCONF
default ARCH_BCM_5301X
help
Say yes here to enable the Broadcom NS SoC pins driver.
The Broadcom Northstar pins driver supports muxing multi-purpose pins
that can be used for various functions (e.g. SPI, I2C, UART) as well
as GPIOs.
config PINCTRL_NSP_GPIO config PINCTRL_NSP_GPIO
bool "Broadcom NSP GPIO (with PINCONF) driver" bool "Broadcom NSP GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST) depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
......
...@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o ...@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o
obj-$(CONFIG_PINCTRL_NS2_MUX) += pinctrl-ns2-mux.o obj-$(CONFIG_PINCTRL_NS2_MUX) += pinctrl-ns2-mux.o
obj-$(CONFIG_PINCTRL_NSP_MUX) += pinctrl-nsp-mux.o obj-$(CONFIG_PINCTRL_NSP_MUX) += pinctrl-nsp-mux.o
This diff is collapsed.
...@@ -64,16 +64,14 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev, ...@@ -64,16 +64,14 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
ret = of_property_read_string(node, "function", &function_name); ret = of_property_read_string(node, "function", &function_name);
if (ret) { if (ret) {
dev_err(pctrl->dev, dev_err(pctrl->dev,
"missing function property in node %s\n", "missing function property in node %pOFn\n", node);
node->name);
return -EINVAL; return -EINVAL;
} }
ngroups = of_property_count_strings(node, "groups"); ngroups = of_property_count_strings(node, "groups");
if (ngroups < 0) { if (ngroups < 0) {
dev_err(pctrl->dev, dev_err(pctrl->dev,
"missing groups property in node %s\n", "missing groups property in node %pOFn\n", node);
node->name);
return -EINVAL; return -EINVAL;
} }
......
...@@ -550,7 +550,7 @@ static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev, ...@@ -550,7 +550,7 @@ static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, " DRV=%umA", madera_pin_unmake_drv_str(priv, conf[1])); seq_printf(s, " DRV=%umA", madera_pin_unmake_drv_str(priv, conf[1]));
if (conf[0] & MADERA_GP1_IP_CFG_MASK) if (conf[0] & MADERA_GP1_IP_CFG_MASK)
seq_puts(s, "SCHMITT"); seq_puts(s, " SCHMITT");
} }
...@@ -608,7 +608,7 @@ static int madera_mux_set_mux(struct pinctrl_dev *pctldev, ...@@ -608,7 +608,7 @@ static int madera_mux_set_mux(struct pinctrl_dev *pctldev,
unsigned int n_chip_groups = priv->chip->n_pin_groups; unsigned int n_chip_groups = priv->chip->n_pin_groups;
const char *func_name = madera_mux_funcs[selector].name; const char *func_name = madera_mux_funcs[selector].name;
unsigned int reg; unsigned int reg;
int i, ret; int i, ret = 0;
dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n", dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n",
__func__, selector, func_name, group, __func__, selector, func_name, group,
...@@ -801,7 +801,7 @@ static int madera_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin, ...@@ -801,7 +801,7 @@ static int madera_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin,
result = 1; result = 1;
break; break;
default: default:
break; return -ENOTSUPP;
} }
*config = pinconf_to_config_packed(param, result); *config = pinconf_to_config_packed(param, result);
...@@ -905,7 +905,7 @@ static int madera_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin, ...@@ -905,7 +905,7 @@ static int madera_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin,
conf[1] &= ~MADERA_GP1_DIR; conf[1] &= ~MADERA_GP1_DIR;
break; break;
default: default:
break; return -ENOTSUPP;
} }
++configs; ++configs;
...@@ -971,10 +971,10 @@ static int madera_pin_conf_group_set(struct pinctrl_dev *pctldev, ...@@ -971,10 +971,10 @@ static int madera_pin_conf_group_set(struct pinctrl_dev *pctldev,
} }
static const struct pinconf_ops madera_pin_conf_ops = { static const struct pinconf_ops madera_pin_conf_ops = {
.is_generic = true,
.pin_config_get = madera_pin_conf_get, .pin_config_get = madera_pin_conf_get,
.pin_config_set = madera_pin_conf_set, .pin_config_set = madera_pin_conf_set,
.pin_config_group_set = madera_pin_conf_group_set, .pin_config_group_set = madera_pin_conf_group_set,
}; };
static struct pinctrl_desc madera_pin_desc = { static struct pinctrl_desc madera_pin_desc = {
......
...@@ -627,7 +627,7 @@ static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev, ...@@ -627,7 +627,7 @@ static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev,
while (selector < ngroups) { while (selector < ngroups) {
const char *gname = ops->get_group_name(pctldev, selector); const char *gname = ops->get_group_name(pctldev, selector);
if (!strcmp(function, gname)) if (gname && !strcmp(function, gname))
return selector; return selector;
selector++; selector++;
...@@ -743,7 +743,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, ...@@ -743,7 +743,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
while (group_selector < ngroups) { while (group_selector < ngroups) {
const char *gname = pctlops->get_group_name(pctldev, const char *gname = pctlops->get_group_name(pctldev,
group_selector); group_selector);
if (!strcmp(gname, pin_group)) { if (gname && !strcmp(gname, pin_group)) {
dev_dbg(pctldev->dev, dev_dbg(pctldev->dev,
"found group selector %u for %s\n", "found group selector %u for %s\n",
group_selector, group_selector,
......
...@@ -69,8 +69,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, ...@@ -69,8 +69,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
*/ */
grp = imx_pinctrl_find_group_by_name(pctldev, np->name); grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
if (!grp) { if (!grp) {
dev_err(ipctl->dev, "unable to find group for node %s\n", dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
np->name);
return -EINVAL; return -EINVAL;
} }
...@@ -434,7 +433,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, ...@@ -434,7 +433,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
int i; int i;
u32 config; u32 config;
dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name); dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
if (info->flags & SHARE_MUX_CONF_REG) if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE; pin_size = FSL_PIN_SHARE_SIZE;
...@@ -544,7 +543,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, ...@@ -544,7 +543,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
struct group_desc *grp; struct group_desc *grp;
u32 i = 0; u32 i = 0;
dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name); dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
func = pinmux_generic_get_function(pctl, index); func = pinmux_generic_get_function(pctl, index);
if (!func) if (!func)
......
...@@ -233,8 +233,8 @@ static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev, ...@@ -233,8 +233,8 @@ static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
*/ */
grp = imx1_pinctrl_find_group_by_name(info, np->name); grp = imx1_pinctrl_find_group_by_name(info, np->name);
if (!grp) { if (!grp) {
dev_err(info->dev, "unable to find group for node %s\n", dev_err(info->dev, "unable to find group for node %pOFn\n",
np->name); np);
return -EINVAL; return -EINVAL;
} }
...@@ -466,7 +466,7 @@ static int imx1_pinctrl_parse_groups(struct device_node *np, ...@@ -466,7 +466,7 @@ static int imx1_pinctrl_parse_groups(struct device_node *np,
const __be32 *list; const __be32 *list;
int i; int i;
dev_dbg(info->dev, "group(%d): %s\n", index, np->name); dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
/* Initialise group */ /* Initialise group */
grp->name = np->name; grp->name = np->name;
...@@ -477,8 +477,8 @@ static int imx1_pinctrl_parse_groups(struct device_node *np, ...@@ -477,8 +477,8 @@ static int imx1_pinctrl_parse_groups(struct device_node *np,
list = of_get_property(np, "fsl,pins", &size); list = of_get_property(np, "fsl,pins", &size);
/* we do not check return since it's safe node passed down */ /* we do not check return since it's safe node passed down */
if (!size || size % 12) { if (!size || size % 12) {
dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n", dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n",
np->name); np);
return -EINVAL; return -EINVAL;
} }
...@@ -513,7 +513,7 @@ static int imx1_pinctrl_parse_functions(struct device_node *np, ...@@ -513,7 +513,7 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
static u32 grp_index; static u32 grp_index;
u32 i = 0; u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
func = &info->functions[index]; func = &info->functions[index];
......
...@@ -556,4 +556,3 @@ int mxs_pinctrl_probe(struct platform_device *pdev, ...@@ -556,4 +556,3 @@ int mxs_pinctrl_probe(struct platform_device *pdev,
iounmap(d->base); iounmap(d->base);
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
...@@ -6,18 +6,19 @@ ...@@ -6,18 +6,19 @@
* Author: Mathias Nyman <mathias.nyman@linux.intel.com> * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
*/ */
#include <linux/kernel.h> #include <linux/acpi.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h> #include <linux/gpio/driver.h>
#include <linux/acpi.h> #include <linux/init.h>
#include <linux/platform_device.h> #include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf.h>
...@@ -682,7 +683,7 @@ static const struct pinctrl_pin_desc byt_ncore_pins[] = { ...@@ -682,7 +683,7 @@ static const struct pinctrl_pin_desc byt_ncore_pins[] = {
PINCTRL_PIN(27, "GPIO_NCORE27"), PINCTRL_PIN(27, "GPIO_NCORE27"),
}; };
static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = { static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
3, 6, 10, 13, 2, 5, 9, 7, 3, 6, 10, 13, 2, 5, 9, 7,
...@@ -926,7 +927,7 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, ...@@ -926,7 +927,7 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
return 0; return 0;
} }
static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
{ {
/* SCORE pin 92-93 */ /* SCORE pin 92-93 */
if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) && if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
...@@ -1310,7 +1311,7 @@ static const struct pinctrl_desc byt_pinctrl_desc = { ...@@ -1310,7 +1311,7 @@ static const struct pinctrl_desc byt_pinctrl_desc = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
}; };
static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
{ {
struct byt_gpio *vg = gpiochip_get_data(chip); struct byt_gpio *vg = gpiochip_get_data(chip);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
...@@ -1324,7 +1325,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) ...@@ -1324,7 +1325,7 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
return !!(val & BYT_LEVEL); return !!(val & BYT_LEVEL);
} }
static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{ {
struct byt_gpio *vg = gpiochip_get_data(chip); struct byt_gpio *vg = gpiochip_get_data(chip);
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
...@@ -1358,9 +1359,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) ...@@ -1358,9 +1359,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
raw_spin_unlock_irqrestore(&vg->lock, flags); raw_spin_unlock_irqrestore(&vg->lock, flags);
if (!(value & BYT_OUTPUT_EN)) if (!(value & BYT_OUTPUT_EN))
return GPIOF_DIR_OUT; return 0;
if (!(value & BYT_INPUT_EN)) if (!(value & BYT_INPUT_EN))
return GPIOF_DIR_IN; return 1;
return -EINVAL; return -EINVAL;
} }
...@@ -1495,7 +1496,7 @@ static void byt_irq_ack(struct irq_data *d) ...@@ -1495,7 +1496,7 @@ static void byt_irq_ack(struct irq_data *d)
{ {
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct byt_gpio *vg = gpiochip_get_data(gc); struct byt_gpio *vg = gpiochip_get_data(gc);
unsigned offset = irqd_to_hwirq(d); unsigned int offset = irqd_to_hwirq(d);
void __iomem *reg; void __iomem *reg;
reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
...@@ -1519,7 +1520,7 @@ static void byt_irq_unmask(struct irq_data *d) ...@@ -1519,7 +1520,7 @@ static void byt_irq_unmask(struct irq_data *d)
{ {
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct byt_gpio *vg = gpiochip_get_data(gc); struct byt_gpio *vg = gpiochip_get_data(gc);
unsigned offset = irqd_to_hwirq(d); unsigned int offset = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
void __iomem *reg; void __iomem *reg;
u32 value; u32 value;
...@@ -1775,13 +1776,11 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = { ...@@ -1775,13 +1776,11 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = {
{ "INT33FC", (kernel_ulong_t)byt_soc_data }, { "INT33FC", (kernel_ulong_t)byt_soc_data },
{ } { }
}; };
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
static int byt_pinctrl_probe(struct platform_device *pdev) static int byt_pinctrl_probe(struct platform_device *pdev)
{ {
const struct byt_pinctrl_soc_data *soc_data = NULL; const struct byt_pinctrl_soc_data *soc_data = NULL;
const struct byt_pinctrl_soc_data **soc_table; const struct byt_pinctrl_soc_data **soc_table;
const struct acpi_device_id *acpi_id;
struct acpi_device *acpi_dev; struct acpi_device *acpi_dev;
struct byt_gpio *vg; struct byt_gpio *vg;
int i, ret; int i, ret;
...@@ -1790,11 +1789,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) ...@@ -1790,11 +1789,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
if (!acpi_dev) if (!acpi_dev)
return -ENODEV; return -ENODEV;
acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev); soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
if (!acpi_id)
return -ENODEV;
soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
for (i = 0; soc_table[i]; i++) { for (i = 0; soc_table[i]; i++) {
if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
......
This diff is collapsed.
...@@ -7,10 +7,10 @@ ...@@ -7,10 +7,10 @@
* Mika Westerberg <mika.westerberg@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com>
*/ */
#include <linux/acpi.h> #include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
...@@ -835,21 +835,10 @@ MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match); ...@@ -835,21 +835,10 @@ MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
static int cnl_pinctrl_probe(struct platform_device *pdev) static int cnl_pinctrl_probe(struct platform_device *pdev)
{ {
const struct intel_pinctrl_soc_data *soc_data; return intel_pinctrl_probe_by_hid(pdev);
const struct acpi_device_id *id;
id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
if (!id || !id->driver_data)
return -ENODEV;
soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
return intel_pinctrl_probe(pdev, soc_data);
} }
static const struct dev_pm_ops cnl_pinctrl_pm_ops = { static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static struct platform_driver cnl_pinctrl_driver = { static struct platform_driver cnl_pinctrl_driver = {
.probe = cnl_pinctrl_probe, .probe = cnl_pinctrl_probe,
......
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include <linux/acpi.h> #include <linux/acpi.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
...@@ -335,10 +335,7 @@ static int cdf_pinctrl_probe(struct platform_device *pdev) ...@@ -335,10 +335,7 @@ static int cdf_pinctrl_probe(struct platform_device *pdev)
return intel_pinctrl_probe(pdev, &cdf_soc_data); return intel_pinctrl_probe(pdev, &cdf_soc_data);
} }
static const struct dev_pm_ops cdf_pinctrl_pm_ops = { static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id cdf_pinctrl_acpi_match[] = { static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
{ "INTC3001" }, { "INTC3001" },
......
This diff is collapsed.
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include <linux/acpi.h> #include <linux/acpi.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
...@@ -262,10 +262,7 @@ static int dnv_pinctrl_probe(struct platform_device *pdev) ...@@ -262,10 +262,7 @@ static int dnv_pinctrl_probe(struct platform_device *pdev)
return intel_pinctrl_probe(pdev, &dnv_soc_data); return intel_pinctrl_probe(pdev, &dnv_soc_data);
} }
static const struct dev_pm_ops dnv_pinctrl_pm_ops = { static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
{ "INTC3000" }, { "INTC3000" },
......
...@@ -6,17 +6,17 @@ ...@@ -6,17 +6,17 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com> * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/ */
#include <linux/acpi.h> #include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
#define GLK_PAD_OWN 0x020 #define GLK_PAD_OWN 0x020
#define GLK_HOSTSW_OWN 0x0b0
#define GLK_PADCFGLOCK 0x080 #define GLK_PADCFGLOCK 0x080
#define GLK_HOSTSW_OWN 0x0b0
#define GLK_GPI_IE 0x110 #define GLK_GPI_IE 0x110
#define GLK_COMMUNITY(s, e) \ #define GLK_COMMUNITY(s, e) \
...@@ -58,16 +58,16 @@ static const struct pinctrl_pin_desc glk_northwest_pins[] = { ...@@ -58,16 +58,16 @@ static const struct pinctrl_pin_desc glk_northwest_pins[] = {
PINCTRL_PIN(23, "GPIO_23"), PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"), PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"), PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"), PINCTRL_PIN(26, "ISH_GPIO_0"),
PINCTRL_PIN(27, "GPIO_27"), PINCTRL_PIN(27, "ISH_GPIO_1"),
PINCTRL_PIN(28, "GPIO_28"), PINCTRL_PIN(28, "ISH_GPIO_2"),
PINCTRL_PIN(29, "GPIO_29"), PINCTRL_PIN(29, "ISH_GPIO_3"),
PINCTRL_PIN(30, "GPIO_30"), PINCTRL_PIN(30, "ISH_GPIO_4"),
PINCTRL_PIN(31, "GPIO_31"), PINCTRL_PIN(31, "ISH_GPIO_5"),
PINCTRL_PIN(32, "GPIO_32"), PINCTRL_PIN(32, "ISH_GPIO_6"),
PINCTRL_PIN(33, "GPIO_33"), PINCTRL_PIN(33, "ISH_GPIO_7"),
PINCTRL_PIN(34, "GPIO_34"), PINCTRL_PIN(34, "ISH_GPIO_8"),
PINCTRL_PIN(35, "GPIO_35"), PINCTRL_PIN(35, "ISH_GPIO_9"),
PINCTRL_PIN(36, "GPIO_36"), PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"), PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"), PINCTRL_PIN(38, "GPIO_38"),
...@@ -195,12 +195,12 @@ static const struct pinctrl_pin_desc glk_north_pins[] = { ...@@ -195,12 +195,12 @@ static const struct pinctrl_pin_desc glk_north_pins[] = {
PINCTRL_PIN(5, "LPSS_SPI_0_FS1"), PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
PINCTRL_PIN(6, "LPSS_SPI_0_RXD"), PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
PINCTRL_PIN(7, "LPSS_SPI_0_TXD"), PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
PINCTRL_PIN(8, "LPSS_SPI_1_CLK"), PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
PINCTRL_PIN(9, "LPSS_SPI_1_FS0"), PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
PINCTRL_PIN(10, "LPSS_SPI_1_FS1"), PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
PINCTRL_PIN(11, "LPSS_SPI_1_FS2"), PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
PINCTRL_PIN(12, "LPSS_SPI_1_RXD"), PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
PINCTRL_PIN(13, "LPSS_SPI_1_TXD"), PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
PINCTRL_PIN(14, "FST_SPI_CS0_B"), PINCTRL_PIN(14, "FST_SPI_CS0_B"),
PINCTRL_PIN(15, "FST_SPI_CS1_B"), PINCTRL_PIN(15, "FST_SPI_CS1_B"),
PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"), PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
...@@ -215,8 +215,8 @@ static const struct pinctrl_pin_desc glk_north_pins[] = { ...@@ -215,8 +215,8 @@ static const struct pinctrl_pin_desc glk_north_pins[] = {
PINCTRL_PIN(25, "PMU_SLP_S3_B"), PINCTRL_PIN(25, "PMU_SLP_S3_B"),
PINCTRL_PIN(26, "PMU_SLP_S4_B"), PINCTRL_PIN(26, "PMU_SLP_S4_B"),
PINCTRL_PIN(27, "SUSPWRDNACK"), PINCTRL_PIN(27, "SUSPWRDNACK"),
PINCTRL_PIN(28, "EMMC_PWR_EN_B"), PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
PINCTRL_PIN(29, "PMU_AC_PRESENT"), PINCTRL_PIN(29, "GPIO_105"),
PINCTRL_PIN(30, "PMU_BATLOW_B"), PINCTRL_PIN(30, "PMU_BATLOW_B"),
PINCTRL_PIN(31, "PMU_RESETBUTTON_B"), PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
PINCTRL_PIN(32, "PMU_SUSCLK"), PINCTRL_PIN(32, "PMU_SUSCLK"),
...@@ -449,42 +449,15 @@ static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = { ...@@ -449,42 +449,15 @@ static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
}; };
static const struct acpi_device_id glk_pinctrl_acpi_match[] = { static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
{ "INT3453" }, { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
{ } { }
}; };
MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match); MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
static int glk_pinctrl_probe(struct platform_device *pdev) static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
{
const struct intel_pinctrl_soc_data *soc_data = NULL;
struct acpi_device *adev;
int i;
adev = ACPI_COMPANION(&pdev->dev);
if (!adev)
return -ENODEV;
for (i = 0; glk_pinctrl_soc_data[i]; i++) {
if (!strcmp(adev->pnp.unique_id,
glk_pinctrl_soc_data[i]->uid)) {
soc_data = glk_pinctrl_soc_data[i];
break;
}
}
if (!soc_data)
return -ENODEV;
return intel_pinctrl_probe(pdev, soc_data);
}
static const struct dev_pm_ops glk_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static struct platform_driver glk_pinctrl_driver = { static struct platform_driver glk_pinctrl_driver = {
.probe = glk_pinctrl_probe, .probe = intel_pinctrl_probe_by_uid,
.driver = { .driver = {
.name = "geminilake-pinctrl", .name = "geminilake-pinctrl",
.acpi_match_table = glk_pinctrl_acpi_match, .acpi_match_table = glk_pinctrl_acpi_match,
......
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#include <linux/acpi.h> #include <linux/acpi.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
...@@ -408,10 +408,7 @@ static int icl_pinctrl_probe(struct platform_device *pdev) ...@@ -408,10 +408,7 @@ static int icl_pinctrl_probe(struct platform_device *pdev)
return intel_pinctrl_probe(pdev, &icllp_soc_data); return intel_pinctrl_probe(pdev, &icllp_soc_data);
} }
static const struct dev_pm_ops icl_pinctrl_pm_ops = { static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id icl_pinctrl_acpi_match[] = { static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
{ "INT3455" }, { "INT3455" },
......
This diff is collapsed.
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#ifndef PINCTRL_INTEL_H #ifndef PINCTRL_INTEL_H
#define PINCTRL_INTEL_H #define PINCTRL_INTEL_H
#include <linux/pm.h>
struct pinctrl_pin_desc; struct pinctrl_pin_desc;
struct platform_device; struct platform_device;
struct device; struct device;
...@@ -25,10 +27,10 @@ struct device; ...@@ -25,10 +27,10 @@ struct device;
*/ */
struct intel_pingroup { struct intel_pingroup {
const char *name; const char *name;
const unsigned *pins; const unsigned int *pins;
size_t npins; size_t npins;
unsigned short mode; unsigned short mode;
const unsigned *modes; const unsigned int *modes;
}; };
/** /**
...@@ -56,11 +58,11 @@ struct intel_function { ...@@ -56,11 +58,11 @@ struct intel_function {
* to specify them. * to specify them.
*/ */
struct intel_padgroup { struct intel_padgroup {
unsigned reg_num; unsigned int reg_num;
unsigned base; unsigned int base;
unsigned size; unsigned int size;
int gpio_base; int gpio_base;
unsigned padown_num; unsigned int padown_num;
}; };
/** /**
...@@ -96,17 +98,17 @@ struct intel_padgroup { ...@@ -96,17 +98,17 @@ struct intel_padgroup {
* pass custom @gpps and @ngpps instead. * pass custom @gpps and @ngpps instead.
*/ */
struct intel_community { struct intel_community {
unsigned barno; unsigned int barno;
unsigned padown_offset; unsigned int padown_offset;
unsigned padcfglock_offset; unsigned int padcfglock_offset;
unsigned hostown_offset; unsigned int hostown_offset;
unsigned is_offset; unsigned int is_offset;
unsigned ie_offset; unsigned int ie_offset;
unsigned pin_base; unsigned int pin_base;
unsigned gpp_size; unsigned int gpp_size;
unsigned gpp_num_padown_regs; unsigned int gpp_num_padown_regs;
size_t npins; size_t npins;
unsigned features; unsigned int features;
const struct intel_padgroup *gpps; const struct intel_padgroup *gpps;
size_t ngpps; size_t ngpps;
/* Reserved for the core driver */ /* Reserved for the core driver */
...@@ -173,9 +175,17 @@ struct intel_pinctrl_soc_data { ...@@ -173,9 +175,17 @@ struct intel_pinctrl_soc_data {
int intel_pinctrl_probe(struct platform_device *pdev, int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data); const struct intel_pinctrl_soc_data *soc_data);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
int intel_pinctrl_suspend(struct device *dev); int intel_pinctrl_suspend(struct device *dev);
int intel_pinctrl_resume(struct device *dev); int intel_pinctrl_resume(struct device *dev);
#endif #endif
#define INTEL_PINCTRL_PM_OPS(_name) \
const struct dev_pm_ops _name = { \
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, intel_pinctrl_resume) \
}
#endif /* PINCTRL_INTEL_H */ #endif /* PINCTRL_INTEL_H */
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include <linux/acpi.h> #include <linux/acpi.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
...@@ -313,10 +313,7 @@ static int lbg_pinctrl_probe(struct platform_device *pdev) ...@@ -313,10 +313,7 @@ static int lbg_pinctrl_probe(struct platform_device *pdev)
return intel_pinctrl_probe(pdev, &lbg_soc_data); return intel_pinctrl_probe(pdev, &lbg_soc_data);
} }
static const struct dev_pm_ops lbg_pinctrl_pm_ops = { static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = { static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
{ "INT3536" }, { "INT3536" },
......
...@@ -476,6 +476,34 @@ static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin ...@@ -476,6 +476,34 @@ static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin
return family->regs + BUFCFG_OFFSET + bufno * 4; return family->regs + BUFCFG_OFFSET + bufno * 4;
} }
static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
{
void __iomem *bufcfg;
if (!mrfld_buf_available(mp, pin))
return -EBUSY;
bufcfg = mrfld_get_bufcfg(mp, pin);
*value = readl(bufcfg);
return 0;
}
static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
u32 bits, u32 mask)
{
void __iomem *bufcfg;
u32 value;
bufcfg = mrfld_get_bufcfg(mp, pin);
value = readl(bufcfg);
value &= ~mask;
value |= bits & mask;
writel(value, bufcfg);
}
static int mrfld_get_groups_count(struct pinctrl_dev *pctldev) static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
{ {
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
...@@ -505,17 +533,15 @@ static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, ...@@ -505,17 +533,15 @@ static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int pin) unsigned int pin)
{ {
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
void __iomem *bufcfg;
u32 value, mode; u32 value, mode;
int ret;
if (!mrfld_buf_available(mp, pin)) { ret = mrfld_read_bufcfg(mp, pin, &value);
if (ret) {
seq_puts(s, "not available"); seq_puts(s, "not available");
return; return;
} }
bufcfg = mrfld_get_bufcfg(mp, pin);
value = readl(bufcfg);
mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
if (!mode) if (!mode)
seq_puts(s, "GPIO "); seq_puts(s, "GPIO ");
...@@ -559,21 +585,6 @@ static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, ...@@ -559,21 +585,6 @@ static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
return 0; return 0;
} }
static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
u32 bits, u32 mask)
{
void __iomem *bufcfg;
u32 value;
bufcfg = mrfld_get_bufcfg(mp, pin);
value = readl(bufcfg);
value &= ~mask;
value |= bits & mask;
writel(value, bufcfg);
}
static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev, static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int function,
unsigned int group) unsigned int group)
...@@ -637,11 +648,12 @@ static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, ...@@ -637,11 +648,12 @@ static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
enum pin_config_param param = pinconf_to_config_param(*config); enum pin_config_param param = pinconf_to_config_param(*config);
u32 value, term; u32 value, term;
u16 arg = 0; u16 arg = 0;
int ret;
if (!mrfld_buf_available(mp, pin)) ret = mrfld_read_bufcfg(mp, pin, &value);
if (ret)
return -ENOTSUPP; return -ENOTSUPP;
value = readl(mrfld_get_bufcfg(mp, pin));
term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
switch (param) { switch (param) {
......
...@@ -7,10 +7,10 @@ ...@@ -7,10 +7,10 @@
* Mika Westerberg <mika.westerberg@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com>
*/ */
#include <linux/acpi.h> #include <linux/mod_devicetable.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
...@@ -593,21 +593,10 @@ MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match); ...@@ -593,21 +593,10 @@ MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
static int spt_pinctrl_probe(struct platform_device *pdev) static int spt_pinctrl_probe(struct platform_device *pdev)
{ {
const struct intel_pinctrl_soc_data *soc_data; return intel_pinctrl_probe_by_hid(pdev);
const struct acpi_device_id *id;
id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev);
if (!id || !id->driver_data)
return -ENODEV;
soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
return intel_pinctrl_probe(pdev, soc_data);
} }
static const struct dev_pm_ops spt_pinctrl_pm_ops = { static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static struct platform_driver spt_pinctrl_driver = { static struct platform_driver spt_pinctrl_driver = {
.probe = spt_pinctrl_probe, .probe = spt_pinctrl_probe,
......
...@@ -3,7 +3,8 @@ menu "MediaTek pinctrl drivers" ...@@ -3,7 +3,8 @@ menu "MediaTek pinctrl drivers"
config EINT_MTK config EINT_MTK
bool "MediaTek External Interrupt Support" bool "MediaTek External Interrupt Support"
depends on PINCTRL_MTK || PINCTRL_MT7622 || COMPILE_TEST depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST
select GPIOLIB
select IRQ_DOMAIN select IRQ_DOMAIN
config PINCTRL_MTK config PINCTRL_MTK
...@@ -15,6 +16,24 @@ config PINCTRL_MTK ...@@ -15,6 +16,24 @@ config PINCTRL_MTK
select EINT_MTK select EINT_MTK
select OF_GPIO select OF_GPIO
config PINCTRL_MTK_MOORE
bool "MediaTek Moore Core that implements generic binding"
depends on OF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select OF_GPIO
config PINCTRL_MTK_PARIS
bool "MediaTek Paris Core that implements vendor binding"
depends on OF
select PINMUX
select GENERIC_PINCONF
select GPIOLIB
select EINT_MTK
select OF_GPIO
# For ARMv7 SoCs # For ARMv7 SoCs
config PINCTRL_MT2701 config PINCTRL_MT2701
bool "Mediatek MT2701 pin control" bool "Mediatek MT2701 pin control"
...@@ -23,6 +42,12 @@ config PINCTRL_MT2701 ...@@ -23,6 +42,12 @@ config PINCTRL_MT2701
default MACH_MT2701 default MACH_MT2701
select PINCTRL_MTK select PINCTRL_MTK
config PINCTRL_MT7623
bool "Mediatek MT7623 pin control with generic binding"
depends on MACH_MT7623 || COMPILE_TEST
depends on PINCTRL_MTK_MOORE
default y
config PINCTRL_MT8135 config PINCTRL_MT8135
bool "Mediatek MT8135 pin control" bool "Mediatek MT8135 pin control"
depends on MACH_MT8135 || COMPILE_TEST depends on MACH_MT8135 || COMPILE_TEST
...@@ -45,15 +70,18 @@ config PINCTRL_MT2712 ...@@ -45,15 +70,18 @@ config PINCTRL_MT2712
default ARM64 && ARCH_MEDIATEK default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK select PINCTRL_MTK
config PINCTRL_MT6765
bool "Mediatek MT6765 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT7622 config PINCTRL_MT7622
bool "MediaTek MT7622 pin control" bool "MediaTek MT7622 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST depends on ARM64 || COMPILE_TEST
select GENERIC_PINCONF depends on PINCTRL_MTK_MOORE
select GENERIC_PINCTRL_GROUPS default y
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select OF_GPIO
config PINCTRL_MT8173 config PINCTRL_MT8173
bool "Mediatek MT8173 pin control" bool "Mediatek MT8173 pin control"
...@@ -62,6 +90,13 @@ config PINCTRL_MT8173 ...@@ -62,6 +90,13 @@ config PINCTRL_MT8173
default ARM64 && ARCH_MEDIATEK default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK select PINCTRL_MTK
config PINCTRL_MT8183
bool "Mediatek MT8183 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
# For PMIC # For PMIC
config PINCTRL_MT6397 config PINCTRL_MT6397
bool "Mediatek MT6397 pin control" bool "Mediatek MT6397 pin control"
......
...@@ -2,12 +2,17 @@ ...@@ -2,12 +2,17 @@
# Core # Core
obj-$(CONFIG_EINT_MTK) += mtk-eint.o obj-$(CONFIG_EINT_MTK) += mtk-eint.o
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o
obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o
# SoC Drivers # SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/gpio.h> #include <linux/gpio/driver.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/irqchip/chained_irq.h> #include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
......
...@@ -92,13 +92,13 @@ static inline int mtk_eint_do_resume(struct mtk_eint *eint) ...@@ -92,13 +92,13 @@ static inline int mtk_eint_do_resume(struct mtk_eint *eint)
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n, static inline int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
unsigned int debounce) unsigned int debounce)
{ {
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) static inline int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
{ {
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
......
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017-2018 MediaTek Inc.
*
* Author: Sean Wang <sean.wang@mediatek.com>
*
*/
#ifndef __PINCTRL_MOORE_H
#define __PINCTRL_MOORE_H
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinmux.h"
#include "mtk-eint.h"
#include "pinctrl-mtk-common-v2.h"
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
#define MTK_PIN(_number, _name, _eint_m, _eint_n, _drv_n) { \
.number = _number, \
.name = _name, \
.eint = { \
.eint_m = _eint_m, \
.eint_n = _eint_n, \
}, \
.drv_n = _drv_n, \
.funcs = NULL, \
}
#define PINCTRL_PIN_GROUP(name, id) \
{ \
name, \
id##_pins, \
ARRAY_SIZE(id##_pins), \
id##_funcs, \
}
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc);
#endif /* __PINCTRL_MOORE_H */
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...@@ -514,8 +514,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, ...@@ -514,8 +514,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
pins = of_find_property(node, "pinmux", NULL); pins = of_find_property(node, "pinmux", NULL);
if (!pins) { if (!pins) {
dev_err(pctl->dev, "missing pins property in node %s .\n", dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
node->name); node);
return -EINVAL; return -EINVAL;
} }
......
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...@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG ...@@ -47,4 +47,10 @@ config PINCTRL_MESON_AXG
config PINCTRL_MESON_AXG_PMX config PINCTRL_MESON_AXG_PMX
bool bool
config PINCTRL_MESON_G12A
bool "Meson g12a Soc pinctrl driver"
depends on ARM64
select PINCTRL_MESON_AXG_PMX
default y
endif endif
...@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o ...@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
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...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
*/ */
#include <linux/device.h> #include <linux/device.h>
#include <linux/gpio.h> #include <linux/gpio/driver.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
...@@ -451,7 +451,7 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc, ...@@ -451,7 +451,7 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
meson_regmap_config.max_register = resource_size(&res) - 4; meson_regmap_config.max_register = resource_size(&res) - 4;
meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
"%s-%s", node->name, "%pOFn-%s", node,
name); name);
if (!meson_regmap_config.name) if (!meson_regmap_config.name)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
......
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# SPDX-License-Identifier: GPL-2.0
# Nuvoton pinctrl support
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
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