Commit b224c4dc authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Unbreak interrupts on pre-gen6

Prior to gen6 we didn't have per-ring IMR registers, which means that
since commit 61ff75ac ("drm/i915: Simplify enabling
user-interrupts with L3-remapping") we're now masking off all interrupts
when init_render_ring() gets called. That's rather rude. Let's limit
the ring IMR frobbing to machines that actually have the per-ring IMR
registers.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 61ff75ac ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1468340687-3596-1-git-send-email-ville.syrjala@linux.intel.comReviewd-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 035ea405)
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5b585925
...@@ -1305,7 +1305,8 @@ static int init_render_ring(struct intel_engine_cs *engine) ...@@ -1305,7 +1305,8 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (IS_GEN(dev_priv, 6, 7)) if (IS_GEN(dev_priv, 6, 7))
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
I915_WRITE_IMR(engine, ~engine->irq_keep_mask); if (INTEL_INFO(dev_priv)->gen >= 6)
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
return init_workarounds_ring(engine); return init_workarounds_ring(engine);
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment