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Commit b35ddfd4 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/rt5514', 'asoc/topic/rt5616',... 

Merge remote-tracking branches 'asoc/topic/rt5514', 'asoc/topic/rt5616', 'asoc/topic/rt5640', 'asoc/topic/rt5660' and 'asoc/topic/rt5663' into asoc-next
parents 2f69b4b2 6342ad66 33ada14a ca5f17c5 d01580c3 73444723
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Showing with 8206 additions and 1151 deletions
Documentation/devicetree/bindings/sound/rt5514.txt
View file @ b35ddfd4
......@@ -13,6 +13,9 @@ Optional properties:
- clocks: The phandle of the master clock to the CODEC
- clock-names: Should be "mclk"
- realtek,dmic-init-delay-ms
Set the DMIC initial delay (ms) to wait it ready.
Pins on the device (for linking into audio routes) for RT5514:
* DMIC1L
......
Documentation/devicetree/bindings/sound/rt5663.txt
View file @ b35ddfd4
RT5663/RT5668 audio CODEC
RT5663 audio CODEC
This device supports I2C only.
Required properties:
- compatible : One of "realtek,rt5663" or "realtek,rt5668".
- compatible : "realtek,rt5663".
- reg : The I2C address of the device.
......@@ -12,7 +12,7 @@ Required properties:
Optional properties:
Pins on the device (for linking into audio routes) for RT5663/RT5668:
Pins on the device (for linking into audio routes) for RT5663:
* IN1P
* IN1N
......
Documentation/devicetree/bindings/sound/rt5665.txt 0 → 100755
View file @ b35ddfd4
RT5665/RT5666/RT5668 audio CODEC
This device supports I2C only.
Required properties:
- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668".
- reg : The I2C address of the device.
- interrupts : The CODEC's interrupt output.
Optional properties:
- realtek,in1-differential
- realtek,in2-differential
- realtek,in3-differential
- realtek,in4-differential
Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended.
- realtek,dmic1-data-pin
0: dmic1 is not used
1: using GPIO4 pin as dmic1 data pin
2: using IN2N pin as dmic2 data pin
- realtek,dmic2-data-pin
0: dmic2 is not used
1: using GPIO5 pin as dmic2 data pin
2: using IN2P pin as dmic2 data pin
- realtek,jd-src
0: No JD is used
1: using JD1 as JD source
- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
Pins on the device (for linking into audio routes) for RT5659/RT5658:
* DMIC L1
* DMIC R1
* DMIC L2
* DMIC R2
* IN1P
* IN1N
* IN2P
* IN2N
* IN3P
* IN3N
* IN4P
* IN4N
* HPOL
* HPOR
* LOUTL
* LOUTR
* MONOOUT
* PDML
* PDMR
Example:
rt5659 {
compatible = "realtek,rt5665";
reg = <0x1b>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
include/sound/rt5514.h 0 → 100644
View file @ b35ddfd4
/*
* linux/sound/rt5514.h -- Platform data for RT5514
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Oder Chiou <oder_chiou@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_RT5514_H
#define __LINUX_SND_RT5514_H
struct rt5514_platform_data {
unsigned int dmic_init_delay;
};
#endif
include/sound/rt5665.h 0 → 100755
View file @ b35ddfd4
/*
* linux/sound/rt5665.h -- Platform data for RT5665
*
* Copyright 2016 Realtek Microelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_RT5665_H
#define __LINUX_SND_RT5665_H
enum rt5665_dmic1_data_pin {
RT5665_DMIC1_NULL,
RT5665_DMIC1_DATA_GPIO4,
RT5665_DMIC1_DATA_IN2N,
};
enum rt5665_dmic2_data_pin {
RT5665_DMIC2_NULL,
RT5665_DMIC2_DATA_GPIO5,
RT5665_DMIC2_DATA_IN2P,
};
enum rt5665_jd_src {
RT5665_JD_NULL,
RT5665_JD1,
};
struct rt5665_platform_data {
bool in1_diff;
bool in2_diff;
bool in3_diff;
bool in4_diff;
int ldo1_en; /* GPIO for LDO1_EN */
enum rt5665_dmic1_data_pin dmic1_data_pin;
enum rt5665_dmic2_data_pin dmic2_data_pin;
enum rt5665_jd_src jd_src;
unsigned int sar_hs_type;
};
#endif
sound/soc/codecs/Kconfig
View file @ b35ddfd4
......@@ -117,6 +117,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_RT5651 if I2C
select SND_SOC_RT5659 if I2C
select SND_SOC_RT5660 if I2C
select SND_SOC_RT5665 if I2C
select SND_SOC_RT5663 if I2C
select SND_SOC_RT5670 if I2C
select SND_SOC_RT5677 if I2C && SPI_MASTER
......@@ -667,6 +668,7 @@ config SND_SOC_RL6231
default y if SND_SOC_RT5651=y
default y if SND_SOC_RT5659=y
default y if SND_SOC_RT5660=y
default y if SND_SOC_RT5665=y
default y if SND_SOC_RT5663=y
default y if SND_SOC_RT5670=y
default y if SND_SOC_RT5677=y
......@@ -677,6 +679,7 @@ config SND_SOC_RL6231
default m if SND_SOC_RT5651=m
default m if SND_SOC_RT5659=m
default m if SND_SOC_RT5660=m
default m if SND_SOC_RT5665=m
default m if SND_SOC_RT5663=m
default m if SND_SOC_RT5670=m
default m if SND_SOC_RT5677=m
......@@ -725,6 +728,9 @@ config SND_SOC_RT5659
config SND_SOC_RT5660
tristate
config SND_SOC_RT5665
tristate
config SND_SOC_RT5663
tristate
......
sound/soc/codecs/Makefile
View file @ b35ddfd4
......@@ -118,6 +118,7 @@ snd-soc-rt5645-objs := rt5645.o
snd-soc-rt5651-objs := rt5651.o
snd-soc-rt5659-objs := rt5659.o
snd-soc-rt5660-objs := rt5660.o
snd-soc-rt5665-objs := rt5665.o
snd-soc-rt5663-objs := rt5663.o
snd-soc-rt5670-objs := rt5670.o
snd-soc-rt5677-objs := rt5677.o
......@@ -345,6 +346,7 @@ obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o
obj-$(CONFIG_SND_SOC_RT5660) += snd-soc-rt5660.o
obj-$(CONFIG_SND_SOC_RT5665) += snd-soc-rt5665.o
obj-$(CONFIG_SND_SOC_RT5663) += snd-soc-rt5663.o
obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
......
sound/soc/codecs/rt5514-spi.c
View file @ b35ddfd4
......@@ -20,7 +20,6 @@
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/sched.h>
#include <linux/kthread.h>
#include <linux/uaccess.h>
#include <linux/miscdevice.h>
#include <linux/regulator/consumer.h>
......
sound/soc/codecs/rt5514.c
View file @ b35ddfd4
......@@ -452,6 +452,9 @@ static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
RT5514_CLK_DMIC_OUT_SEL_MASK,
idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
if (rt5514->pdata.dmic_init_delay)
msleep(rt5514->pdata.dmic_init_delay);
return idx;
}
......@@ -1073,9 +1076,18 @@ static const struct of_device_id rt5514_of_match[] = {
MODULE_DEVICE_TABLE(of, rt5514_of_match);
#endif
static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev)
{
device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
&rt5514->pdata.dmic_init_delay);
return 0;
}
static int rt5514_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5514_priv *rt5514;
int ret;
unsigned int val;
......@@ -1087,6 +1099,11 @@ static int rt5514_i2c_probe(struct i2c_client *i2c,
i2c_set_clientdata(i2c, rt5514);
if (pdata)
rt5514->pdata = *pdata;
else if (i2c->dev.of_node)
rt5514_parse_dt(rt5514, &i2c->dev);
rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
if (IS_ERR(rt5514->i2c_regmap)) {
ret = PTR_ERR(rt5514->i2c_regmap);
......
sound/soc/codecs/rt5514.h
View file @ b35ddfd4
......@@ -13,6 +13,7 @@
#define __RT5514_H__
#include <linux/clk.h>
#include <sound/rt5514.h>
#define RT5514_DEVICE_ID 0x10ec5514
......@@ -243,6 +244,7 @@ enum {
};
struct rt5514_priv {
struct rt5514_platform_data pdata;
struct snd_soc_codec *codec;
struct regmap *i2c_regmap, *regmap;
struct clk *mclk;
......
sound/soc/codecs/rt5616.c
View file @ b35ddfd4
......@@ -960,8 +960,7 @@ static int rt5616_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_codec *codec = rtd->codec;
struct snd_soc_codec *codec = dai->codec;
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
......
sound/soc/codecs/rt5640.c
View file @ b35ddfd4
......@@ -423,6 +423,8 @@ static const struct snd_kcontrol_new rt5640_snd_controls[] = {
SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
127, 0, adc_vol_tlv),
SOC_DOUBLE("Mono ADC Capture Switch", RT5640_DUMMY1,
RT5640_M_MONO_ADC_L_SFT, RT5640_M_MONO_ADC_R_SFT, 1, 1),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
127, 0, adc_vol_tlv),
......@@ -2407,6 +2409,9 @@ static int rt5640_i2c_probe(struct i2c_client *i2c,
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5640->regmap, RT5640_DUMMY1,
RT5640_MCLK_DET, RT5640_MCLK_DET);
if (rt5640->pdata.in1_diff)
regmap_update_bits(rt5640->regmap, RT5640_IN1_IN2,
RT5640_IN_DF1, RT5640_IN_DF1);
......
sound/soc/codecs/rt5640.h
View file @ b35ddfd4
......@@ -1970,6 +1970,12 @@
#define RT5640_ZCD_HP_DIS (0x0 << 15)
#define RT5640_ZCD_HP_EN (0x1 << 15)
/* General Control 1 (0xfa) */
#define RT5640_M_MONO_ADC_L (0x1 << 13)
#define RT5640_M_MONO_ADC_L_SFT 13
#define RT5640_M_MONO_ADC_R (0x1 << 12)
#define RT5640_M_MONO_ADC_R_SFT 12
#define RT5640_MCLK_DET (0x1 << 11)
/* Codec Private Register definition */
/* 3D Speaker Control (0x63) */
......
sound/soc/codecs/rt5660.c
View file @ b35ddfd4
......@@ -1311,6 +1311,10 @@ static int rt5660_i2c_probe(struct i2c_client *i2c,
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5660->regmap, RT5660_GEN_CTRL1,
RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET,
RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET);
if (rt5660->pdata.dmic1_data_pin) {
regmap_update_bits(rt5660->regmap, RT5660_GPIO_CTRL1,
RT5660_GP1_PIN_MASK, RT5660_GP1_PIN_DMIC1_SCL);
......
sound/soc/codecs/rt5660.h
View file @ b35ddfd4
......@@ -810,6 +810,9 @@
/* General Control 1 (0xfa) */
#define RT5660_PWR_VREF_HP (0x1 << 11)
#define RT5660_PWR_VREF_HP_SFT 11
#define RT5660_AUTO_DIS_AMP (0x1 << 6)
#define RT5660_MCLK_DET (0x1 << 5)
#define RT5660_POW_CLKDET (0x1 << 1)
#define RT5660_DIG_GATE_CTRL (0x1)
#define RT5660_DIG_GATE_CTRL_SFT 0
......
sound/soc/codecs/rt5663.c
View file @ b35ddfd4
/*
* rt5663.c -- RT5668/RT5663 ALSA SoC audio codec driver
* rt5663.c -- RT5663 ALSA SoC audio codec driver
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Jack Yu <jack.yu@realtek.com>
......@@ -30,12 +30,12 @@
#include "rt5663.h"
#include "rl6231.h"
#define RT5668_DEVICE_ID 0x6451
#define RT5663_DEVICE_ID 0x6406
#define RT5663_DEVICE_ID_2 0x6451
#define RT5663_DEVICE_ID_1 0x6406
enum {
CODEC_TYPE_RT5668,
CODEC_TYPE_RT5663,
CODEC_VER_1,
CODEC_VER_0,
};
struct rt5663_priv {
......@@ -45,7 +45,7 @@ struct rt5663_priv {
struct snd_soc_jack *hs_jack;
struct timer_list btn_check_timer;
int codec_type;
int codec_ver;
int sysclk;
int sysclk_src;
int lrck;
......@@ -57,7 +57,7 @@ struct rt5663_priv {
int jack_type;
};
static const struct reg_default rt5668_reg[] = {
static const struct reg_default rt5663_v2_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0001, 0xc8c8 },
{ 0x0002, 0x8080 },
......@@ -730,7 +730,7 @@ static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5663_INT_ST_2:
case RT5663_GPIO_STA:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
......@@ -846,7 +846,7 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
case RT5663_INT_ST_2:
case RT5663_GPIO_1:
case RT5663_GPIO_2:
case RT5663_GPIO_STA:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
......@@ -1036,23 +1036,23 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
}
}
static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_RESET:
case RT5668_CBJ_TYPE_2:
case RT5668_PDM_OUT_CTL:
case RT5668_PDM_I2C_DATA_CTL1:
case RT5668_PDM_I2C_DATA_CTL4:
case RT5668_ALC_BK_GAIN:
case RT5663_CBJ_TYPE_2:
case RT5663_PDM_OUT_CTL:
case RT5663_PDM_I2C_DATA_CTL1:
case RT5663_PDM_I2C_DATA_CTL4:
case RT5663_ALC_BK_GAIN:
case RT5663_PLL_2:
case RT5663_MICBIAS_1:
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5668_GPIO_STA:
case RT5663_GPIO_STA2:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
case RT5668_A_JD_CTRL:
case RT5663_A_JD_CTRL:
case RT5663_JD_CTRL2:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
......@@ -1061,15 +1061,15 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
case RT5663_STO_DRE_5:
case RT5663_STO_DRE_6:
case RT5663_STO_DRE_7:
case RT5668_MONO_DYNA_6:
case RT5668_STO1_SIL_DET:
case RT5668_MONOL_SIL_DET:
case RT5668_MONOR_SIL_DET:
case RT5668_STO2_DAC_SIL:
case RT5668_MONO_AMP_CAL_ST1:
case RT5668_MONO_AMP_CAL_ST2:
case RT5668_MONO_AMP_CAL_ST3:
case RT5668_MONO_AMP_CAL_ST4:
case RT5663_MONO_DYNA_6:
case RT5663_STO1_SIL_DET:
case RT5663_MONOL_SIL_DET:
case RT5663_MONOR_SIL_DET:
case RT5663_STO2_DAC_SIL:
case RT5663_MONO_AMP_CAL_ST1:
case RT5663_MONO_AMP_CAL_ST2:
case RT5663_MONO_AMP_CAL_ST3:
case RT5663_MONO_AMP_CAL_ST4:
case RT5663_HP_IMP_SEN_2:
case RT5663_HP_IMP_SEN_3:
case RT5663_HP_IMP_SEN_4:
......@@ -1083,218 +1083,218 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
case RT5663_HP_CALIB_ST7:
case RT5663_HP_CALIB_ST8:
case RT5663_HP_CALIB_ST9:
case RT5668_HP_CALIB_ST10:
case RT5668_HP_CALIB_ST11:
case RT5663_HP_CALIB_ST10:
case RT5663_HP_CALIB_ST11:
return true;
default:
return false;
}
}
static bool rt5668_readable_register(struct device *dev, unsigned int reg)
static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5668_LOUT_CTRL:
case RT5668_HP_AMP_2:
case RT5668_MONO_OUT:
case RT5668_MONO_GAIN:
case RT5668_AEC_BST:
case RT5668_IN1_IN2:
case RT5668_IN3_IN4:
case RT5668_INL1_INR1:
case RT5668_CBJ_TYPE_2:
case RT5668_CBJ_TYPE_3:
case RT5668_CBJ_TYPE_4:
case RT5668_CBJ_TYPE_5:
case RT5668_CBJ_TYPE_8:
case RT5668_DAC3_DIG_VOL:
case RT5668_DAC3_CTRL:
case RT5668_MONO_ADC_DIG_VOL:
case RT5668_STO2_ADC_DIG_VOL:
case RT5668_MONO_ADC_BST_GAIN:
case RT5668_STO2_ADC_BST_GAIN:
case RT5668_SIDETONE_CTRL:
case RT5668_MONO1_ADC_MIXER:
case RT5668_STO2_ADC_MIXER:
case RT5668_MONO_DAC_MIXER:
case RT5668_DAC2_SRC_CTRL:
case RT5668_IF_3_4_DATA_CTL:
case RT5668_IF_5_DATA_CTL:
case RT5668_PDM_OUT_CTL:
case RT5668_PDM_I2C_DATA_CTL1:
case RT5668_PDM_I2C_DATA_CTL2:
case RT5668_PDM_I2C_DATA_CTL3:
case RT5668_PDM_I2C_DATA_CTL4:
case RT5668_RECMIX1_NEW:
case RT5668_RECMIX1L_0:
case RT5668_RECMIX1L:
case RT5668_RECMIX1R_0:
case RT5668_RECMIX1R:
case RT5668_RECMIX2_NEW:
case RT5668_RECMIX2_L_2:
case RT5668_RECMIX2_R:
case RT5668_RECMIX2_R_2:
case RT5668_CALIB_REC_LR:
case RT5668_ALC_BK_GAIN:
case RT5668_MONOMIX_GAIN:
case RT5668_MONOMIX_IN_GAIN:
case RT5668_OUT_MIXL_GAIN:
case RT5668_OUT_LMIX_IN_GAIN:
case RT5668_OUT_RMIX_IN_GAIN:
case RT5668_OUT_RMIX_IN_GAIN1:
case RT5668_LOUT_MIXER_CTRL:
case RT5668_PWR_VOL:
case RT5668_ADCDAC_RST:
case RT5668_I2S34_SDP:
case RT5668_I2S5_SDP:
case RT5668_TDM_5:
case RT5668_TDM_6:
case RT5668_TDM_7:
case RT5668_TDM_8:
case RT5668_ASRC_3:
case RT5668_ASRC_6:
case RT5668_ASRC_7:
case RT5668_PLL_TRK_13:
case RT5668_I2S_M_CLK_CTL:
case RT5668_FDIV_I2S34_M_CLK:
case RT5668_FDIV_I2S34_M_CLK2:
case RT5668_FDIV_I2S5_M_CLK:
case RT5668_FDIV_I2S5_M_CLK2:
case RT5668_IRQ_4:
case RT5668_GPIO_3:
case RT5668_GPIO_4:
case RT5668_GPIO_STA:
case RT5668_HP_AMP_DET1:
case RT5668_HP_AMP_DET2:
case RT5668_HP_AMP_DET3:
case RT5668_MID_BD_HP_AMP:
case RT5668_LOW_BD_HP_AMP:
case RT5668_SOF_VOL_ZC2:
case RT5668_ADC_STO2_ADJ1:
case RT5668_ADC_STO2_ADJ2:
case RT5668_A_JD_CTRL:
case RT5668_JD1_TRES_CTRL:
case RT5668_JD2_TRES_CTRL:
case RT5668_JD_CTRL2:
case RT5668_DUM_REG_2:
case RT5668_DUM_REG_3:
case RT5663_LOUT_CTRL:
case RT5663_HP_AMP_2:
case RT5663_MONO_OUT:
case RT5663_MONO_GAIN:
case RT5663_AEC_BST:
case RT5663_IN1_IN2:
case RT5663_IN3_IN4:
case RT5663_INL1_INR1:
case RT5663_CBJ_TYPE_2:
case RT5663_CBJ_TYPE_3:
case RT5663_CBJ_TYPE_4:
case RT5663_CBJ_TYPE_5:
case RT5663_CBJ_TYPE_8:
case RT5663_DAC3_DIG_VOL:
case RT5663_DAC3_CTRL:
case RT5663_MONO_ADC_DIG_VOL:
case RT5663_STO2_ADC_DIG_VOL:
case RT5663_MONO_ADC_BST_GAIN:
case RT5663_STO2_ADC_BST_GAIN:
case RT5663_SIDETONE_CTRL:
case RT5663_MONO1_ADC_MIXER:
case RT5663_STO2_ADC_MIXER:
case RT5663_MONO_DAC_MIXER:
case RT5663_DAC2_SRC_CTRL:
case RT5663_IF_3_4_DATA_CTL:
case RT5663_IF_5_DATA_CTL:
case RT5663_PDM_OUT_CTL:
case RT5663_PDM_I2C_DATA_CTL1:
case RT5663_PDM_I2C_DATA_CTL2:
case RT5663_PDM_I2C_DATA_CTL3:
case RT5663_PDM_I2C_DATA_CTL4:
case RT5663_RECMIX1_NEW:
case RT5663_RECMIX1L_0:
case RT5663_RECMIX1L:
case RT5663_RECMIX1R_0:
case RT5663_RECMIX1R:
case RT5663_RECMIX2_NEW:
case RT5663_RECMIX2_L_2:
case RT5663_RECMIX2_R:
case RT5663_RECMIX2_R_2:
case RT5663_CALIB_REC_LR:
case RT5663_ALC_BK_GAIN:
case RT5663_MONOMIX_GAIN:
case RT5663_MONOMIX_IN_GAIN:
case RT5663_OUT_MIXL_GAIN:
case RT5663_OUT_LMIX_IN_GAIN:
case RT5663_OUT_RMIX_IN_GAIN:
case RT5663_OUT_RMIX_IN_GAIN1:
case RT5663_LOUT_MIXER_CTRL:
case RT5663_PWR_VOL:
case RT5663_ADCDAC_RST:
case RT5663_I2S34_SDP:
case RT5663_I2S5_SDP:
case RT5663_TDM_6:
case RT5663_TDM_7:
case RT5663_TDM_8:
case RT5663_TDM_9:
case RT5663_ASRC_3:
case RT5663_ASRC_6:
case RT5663_ASRC_7:
case RT5663_PLL_TRK_13:
case RT5663_I2S_M_CLK_CTL:
case RT5663_FDIV_I2S34_M_CLK:
case RT5663_FDIV_I2S34_M_CLK2:
case RT5663_FDIV_I2S5_M_CLK:
case RT5663_FDIV_I2S5_M_CLK2:
case RT5663_V2_IRQ_4:
case RT5663_GPIO_3:
case RT5663_GPIO_4:
case RT5663_GPIO_STA2:
case RT5663_HP_AMP_DET1:
case RT5663_HP_AMP_DET2:
case RT5663_HP_AMP_DET3:
case RT5663_MID_BD_HP_AMP:
case RT5663_LOW_BD_HP_AMP:
case RT5663_SOF_VOL_ZC2:
case RT5663_ADC_STO2_ADJ1:
case RT5663_ADC_STO2_ADJ2:
case RT5663_A_JD_CTRL:
case RT5663_JD1_TRES_CTRL:
case RT5663_JD2_TRES_CTRL:
case RT5663_V2_JD_CTRL2:
case RT5663_DUM_REG_2:
case RT5663_DUM_REG_3:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
case RT5668_DACADC_DIG_VOL2:
case RT5668_DIG_IN_PIN2:
case RT5668_PAD_DRV_CTL1:
case RT5668_SOF_RAM_DEPOP:
case RT5668_VOL_TEST:
case RT5668_TEST_MODE_3:
case RT5668_TEST_MODE_4:
case RT5663_DACADC_DIG_VOL2:
case RT5663_DIG_IN_PIN2:
case RT5663_PAD_DRV_CTL1:
case RT5663_SOF_RAM_DEPOP:
case RT5663_VOL_TEST:
case RT5663_TEST_MODE_4:
case RT5663_TEST_MODE_5:
case RT5663_STO_DRE_9:
case RT5668_MONO_DYNA_1:
case RT5668_MONO_DYNA_2:
case RT5668_MONO_DYNA_3:
case RT5668_MONO_DYNA_4:
case RT5668_MONO_DYNA_5:
case RT5668_MONO_DYNA_6:
case RT5668_STO1_SIL_DET:
case RT5668_MONOL_SIL_DET:
case RT5668_MONOR_SIL_DET:
case RT5668_STO2_DAC_SIL:
case RT5668_PWR_SAV_CTL1:
case RT5668_PWR_SAV_CTL2:
case RT5668_PWR_SAV_CTL3:
case RT5668_PWR_SAV_CTL4:
case RT5668_PWR_SAV_CTL5:
case RT5668_PWR_SAV_CTL6:
case RT5668_MONO_AMP_CAL1:
case RT5668_MONO_AMP_CAL2:
case RT5668_MONO_AMP_CAL3:
case RT5668_MONO_AMP_CAL4:
case RT5668_MONO_AMP_CAL5:
case RT5668_MONO_AMP_CAL6:
case RT5668_MONO_AMP_CAL7:
case RT5668_MONO_AMP_CAL_ST1:
case RT5668_MONO_AMP_CAL_ST2:
case RT5668_MONO_AMP_CAL_ST3:
case RT5668_MONO_AMP_CAL_ST4:
case RT5668_MONO_AMP_CAL_ST5:
case RT5668_HP_IMP_SEN_13:
case RT5668_HP_IMP_SEN_14:
case RT5668_HP_IMP_SEN_6:
case RT5668_HP_IMP_SEN_7:
case RT5668_HP_IMP_SEN_8:
case RT5668_HP_IMP_SEN_9:
case RT5668_HP_IMP_SEN_10:
case RT5668_HP_LOGIC_3:
case RT5668_HP_CALIB_ST10:
case RT5668_HP_CALIB_ST11:
case RT5668_PRO_REG_TBL_4:
case RT5668_PRO_REG_TBL_5:
case RT5668_PRO_REG_TBL_6:
case RT5668_PRO_REG_TBL_7:
case RT5668_PRO_REG_TBL_8:
case RT5668_PRO_REG_TBL_9:
case RT5668_SAR_ADC_INL_1:
case RT5668_SAR_ADC_INL_2:
case RT5668_SAR_ADC_INL_3:
case RT5668_SAR_ADC_INL_4:
case RT5668_SAR_ADC_INL_5:
case RT5668_SAR_ADC_INL_6:
case RT5668_SAR_ADC_INL_7:
case RT5668_SAR_ADC_INL_8:
case RT5668_SAR_ADC_INL_9:
case RT5668_SAR_ADC_INL_10:
case RT5668_SAR_ADC_INL_11:
case RT5668_SAR_ADC_INL_12:
case RT5668_DRC_CTRL_1:
case RT5668_DRC1_CTRL_2:
case RT5668_DRC1_CTRL_3:
case RT5668_DRC1_CTRL_4:
case RT5668_DRC1_CTRL_5:
case RT5668_DRC1_CTRL_6:
case RT5668_DRC1_HD_CTRL_1:
case RT5668_DRC1_HD_CTRL_2:
case RT5668_DRC1_PRI_REG_1:
case RT5668_DRC1_PRI_REG_2:
case RT5668_DRC1_PRI_REG_3:
case RT5668_DRC1_PRI_REG_4:
case RT5668_DRC1_PRI_REG_5:
case RT5668_DRC1_PRI_REG_6:
case RT5668_DRC1_PRI_REG_7:
case RT5668_DRC1_PRI_REG_8:
case RT5668_ALC_PGA_CTL_1:
case RT5668_ALC_PGA_CTL_2:
case RT5668_ALC_PGA_CTL_3:
case RT5668_ALC_PGA_CTL_4:
case RT5668_ALC_PGA_CTL_5:
case RT5668_ALC_PGA_CTL_6:
case RT5668_ALC_PGA_CTL_7:
case RT5668_ALC_PGA_CTL_8:
case RT5668_ALC_PGA_REG_1:
case RT5668_ALC_PGA_REG_2:
case RT5668_ALC_PGA_REG_3:
case RT5668_ADC_EQ_RECOV_1:
case RT5668_ADC_EQ_RECOV_2:
case RT5668_ADC_EQ_RECOV_3:
case RT5668_ADC_EQ_RECOV_4:
case RT5668_ADC_EQ_RECOV_5:
case RT5668_ADC_EQ_RECOV_6:
case RT5668_ADC_EQ_RECOV_7:
case RT5668_ADC_EQ_RECOV_8:
case RT5668_ADC_EQ_RECOV_9:
case RT5668_ADC_EQ_RECOV_10:
case RT5668_ADC_EQ_RECOV_11:
case RT5668_ADC_EQ_RECOV_12:
case RT5668_ADC_EQ_RECOV_13:
case RT5668_VID_HIDDEN:
case RT5668_VID_CUSTOMER:
case RT5668_SCAN_MODE:
case RT5668_I2C_BYPA:
case RT5663_MONO_DYNA_1:
case RT5663_MONO_DYNA_2:
case RT5663_MONO_DYNA_3:
case RT5663_MONO_DYNA_4:
case RT5663_MONO_DYNA_5:
case RT5663_MONO_DYNA_6:
case RT5663_STO1_SIL_DET:
case RT5663_MONOL_SIL_DET:
case RT5663_MONOR_SIL_DET:
case RT5663_STO2_DAC_SIL:
case RT5663_PWR_SAV_CTL1:
case RT5663_PWR_SAV_CTL2:
case RT5663_PWR_SAV_CTL3:
case RT5663_PWR_SAV_CTL4:
case RT5663_PWR_SAV_CTL5:
case RT5663_PWR_SAV_CTL6:
case RT5663_MONO_AMP_CAL1:
case RT5663_MONO_AMP_CAL2:
case RT5663_MONO_AMP_CAL3:
case RT5663_MONO_AMP_CAL4:
case RT5663_MONO_AMP_CAL5:
case RT5663_MONO_AMP_CAL6:
case RT5663_MONO_AMP_CAL7:
case RT5663_MONO_AMP_CAL_ST1:
case RT5663_MONO_AMP_CAL_ST2:
case RT5663_MONO_AMP_CAL_ST3:
case RT5663_MONO_AMP_CAL_ST4:
case RT5663_MONO_AMP_CAL_ST5:
case RT5663_V2_HP_IMP_SEN_13:
case RT5663_V2_HP_IMP_SEN_14:
case RT5663_V2_HP_IMP_SEN_6:
case RT5663_V2_HP_IMP_SEN_7:
case RT5663_V2_HP_IMP_SEN_8:
case RT5663_V2_HP_IMP_SEN_9:
case RT5663_V2_HP_IMP_SEN_10:
case RT5663_HP_LOGIC_3:
case RT5663_HP_CALIB_ST10:
case RT5663_HP_CALIB_ST11:
case RT5663_PRO_REG_TBL_4:
case RT5663_PRO_REG_TBL_5:
case RT5663_PRO_REG_TBL_6:
case RT5663_PRO_REG_TBL_7:
case RT5663_PRO_REG_TBL_8:
case RT5663_PRO_REG_TBL_9:
case RT5663_SAR_ADC_INL_1:
case RT5663_SAR_ADC_INL_2:
case RT5663_SAR_ADC_INL_3:
case RT5663_SAR_ADC_INL_4:
case RT5663_SAR_ADC_INL_5:
case RT5663_SAR_ADC_INL_6:
case RT5663_SAR_ADC_INL_7:
case RT5663_SAR_ADC_INL_8:
case RT5663_SAR_ADC_INL_9:
case RT5663_SAR_ADC_INL_10:
case RT5663_SAR_ADC_INL_11:
case RT5663_SAR_ADC_INL_12:
case RT5663_DRC_CTRL_1:
case RT5663_DRC1_CTRL_2:
case RT5663_DRC1_CTRL_3:
case RT5663_DRC1_CTRL_4:
case RT5663_DRC1_CTRL_5:
case RT5663_DRC1_CTRL_6:
case RT5663_DRC1_HD_CTRL_1:
case RT5663_DRC1_HD_CTRL_2:
case RT5663_DRC1_PRI_REG_1:
case RT5663_DRC1_PRI_REG_2:
case RT5663_DRC1_PRI_REG_3:
case RT5663_DRC1_PRI_REG_4:
case RT5663_DRC1_PRI_REG_5:
case RT5663_DRC1_PRI_REG_6:
case RT5663_DRC1_PRI_REG_7:
case RT5663_DRC1_PRI_REG_8:
case RT5663_ALC_PGA_CTL_1:
case RT5663_ALC_PGA_CTL_2:
case RT5663_ALC_PGA_CTL_3:
case RT5663_ALC_PGA_CTL_4:
case RT5663_ALC_PGA_CTL_5:
case RT5663_ALC_PGA_CTL_6:
case RT5663_ALC_PGA_CTL_7:
case RT5663_ALC_PGA_CTL_8:
case RT5663_ALC_PGA_REG_1:
case RT5663_ALC_PGA_REG_2:
case RT5663_ALC_PGA_REG_3:
case RT5663_ADC_EQ_RECOV_1:
case RT5663_ADC_EQ_RECOV_2:
case RT5663_ADC_EQ_RECOV_3:
case RT5663_ADC_EQ_RECOV_4:
case RT5663_ADC_EQ_RECOV_5:
case RT5663_ADC_EQ_RECOV_6:
case RT5663_ADC_EQ_RECOV_7:
case RT5663_ADC_EQ_RECOV_8:
case RT5663_ADC_EQ_RECOV_9:
case RT5663_ADC_EQ_RECOV_10:
case RT5663_ADC_EQ_RECOV_11:
case RT5663_ADC_EQ_RECOV_12:
case RT5663_ADC_EQ_RECOV_13:
case RT5663_VID_HIDDEN:
case RT5663_VID_CUSTOMER:
case RT5663_SCAN_MODE:
case RT5663_I2C_BYPA:
return true;
case RT5663_TDM_1:
case RT5663_DEPOP_3:
case RT5663_ASRC_11_2:
case RT5663_INT_ST_2:
case RT5663_GPIO_STA:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
......@@ -1344,7 +1344,7 @@ static bool rt5668_readable_register(struct device *dev, unsigned int reg)
}
static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
static const DECLARE_TLV_DB_SCALE(rt5668_hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
......@@ -1374,57 +1374,57 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
if (enable) {
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_EN);
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
/* reset in-line command */
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_RESET);
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_RESET);
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_NOR);
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_NOR);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_update_bits(codec, RT5663_IRQ_3,
RT5668_EN_IRQ_INLINE_MASK,
RT5668_EN_IRQ_INLINE_NOR);
RT5663_V2_EN_IRQ_INLINE_MASK,
RT5663_V2_EN_IRQ_INLINE_NOR);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
snd_soc_update_bits(codec, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_NOR);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
} else {
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_update_bits(codec, RT5663_IRQ_3,
RT5668_EN_IRQ_INLINE_MASK,
RT5668_EN_IRQ_INLINE_BYP);
RT5663_V2_EN_IRQ_INLINE_MASK,
RT5663_V2_EN_IRQ_INLINE_BYP);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
snd_soc_update_bits(codec, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_BYP);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_DIS);
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
/* reset in-line command */
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_RESET);
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_RESET);
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_NOR);
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_NOR);
}
}
/**
* rt5668_jack_detect - Detect headset.
* rt5663_v2_jack_detect - Detect headset.
* @codec: SoC audio codec device.
* @jack_insert: Jack insert or not.
*
......@@ -1433,16 +1433,16 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
* Returns detect status.
*/
static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
{
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
if (jack_insert) {
snd_soc_write(codec, RT5668_CBJ_TYPE_2, 0x8040);
snd_soc_write(codec, RT5668_CBJ_TYPE_3, 0x1484);
snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
......@@ -1450,12 +1450,12 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
snd_soc_update_bits(codec, RT5663_RC_CLK,
RT5668_DIG_1M_CLK_MASK, RT5668_DIG_1M_CLK_EN);
RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
while (i < 5) {
msleep(sleep_time[i]);
val = snd_soc_read(codec, RT5668_CBJ_TYPE_2) & 0x0003;
val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
if (val == 0x1 || val == 0x2 || val == 0x3)
break;
dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
......@@ -1466,7 +1466,7 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
switch (val) {
case 1:
case 2:
rt5668->jack_type = SND_JACK_HEADSET;
rt5663->jack_type = SND_JACK_HEADSET;
rt5663_enable_push_button_irq(codec, true);
break;
default:
......@@ -1475,13 +1475,13 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
rt5668->jack_type = SND_JACK_HEADPHONE;
rt5663->jack_type = SND_JACK_HEADPHONE;
break;
}
} else {
snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
if (rt5668->jack_type == SND_JACK_HEADSET) {
if (rt5663->jack_type == SND_JACK_HEADSET) {
rt5663_enable_push_button_irq(codec, false);
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
......@@ -1489,11 +1489,11 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
}
rt5668->jack_type = 0;
rt5663->jack_type = 0;
}
dev_dbg(codec->dev, "jack_type = %d\n", rt5668->jack_type);
return rt5668->jack_type;
dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
return rt5663->jack_type;
}
/**
......@@ -1514,11 +1514,11 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
if (jack_insert) {
snd_soc_update_bits(codec, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5663_SI_HP_MASK | RT5668_OSW_HP_L_MASK |
RT5668_OSW_HP_R_MASK, RT5663_SI_HP_EN |
RT5668_OSW_HP_L_DIS | RT5668_OSW_HP_R_DIS);
RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
snd_soc_update_bits(codec, RT5663_DUMMY_1,
RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
......@@ -1530,17 +1530,17 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
/* BST1 power on for JD */
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
RT5668_PWR_BST1_MASK, RT5668_PWR_BST1_ON);
RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_MB_MASK | RT5668_LDO1_DVO_MASK |
RT5668_AMP_HP_MASK, RT5668_PWR_MB |
RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
RT5663_AMP_HP_MASK, RT5663_PWR_MB |
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
snd_soc_update_bits(codec, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
while (i < 5) {
......@@ -1619,13 +1619,13 @@ static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
/* JD1 */
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
return !(val & 0x2000);
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
return !(val & 0x1000);
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
return false;
......@@ -1645,15 +1645,16 @@ static void rt5663_jack_detect_work(struct work_struct *work)
/* jack in */
if (rt5663->jack_type == 0) {
/* jack was out, report jack type */
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
report = rt5668_jack_detect(rt5663->codec, 1);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
report = rt5663_v2_jack_detect(
rt5663->codec, 1);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->codec, 1);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
} else {
/* jack is already in, report button event */
......@@ -1702,15 +1703,15 @@ static void rt5663_jack_detect_work(struct work_struct *work)
}
} else {
/* jack out */
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
report = rt5668_jack_detect(rt5663->codec, 0);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
report = rt5663_v2_jack_detect(rt5663->codec, 0);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->codec, 0);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
}
dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
......@@ -1722,24 +1723,24 @@ static void rt5663_jack_detect_work(struct work_struct *work)
static const struct snd_kcontrol_new rt5663_snd_controls[] = {
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
RT5668_DAC_L1_VOL_SHIFT + 1, RT5668_DAC_R1_VOL_SHIFT + 1,
RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
87, 0, dac_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
RT5668_ADC_L_MUTE_SHIFT, RT5668_ADC_R_MUTE_SHIFT, 1, 1),
RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
RT5668_ADC_L_VOL_SHIFT + 1, RT5668_ADC_R_VOL_SHIFT + 1,
RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
63, 0, adc_vol_tlv),
};
static const struct snd_kcontrol_new rt5668_specific_controls[] = {
static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
RT5663_HP_RCH_DRE, RT5668_GAIN_HP_SHIFT, 15, 1,
rt5668_hp_vol_tlv),
RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
rt5663_v2_hp_vol_tlv),
/* Mic Boost Volume */
SOC_SINGLE_TLV("IN1 Capture Volume", RT5668_AEC_BST,
RT5668_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
};
static const struct snd_kcontrol_new rt5663_specific_controls[] = {
......@@ -1775,15 +1776,15 @@ static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
switch (w->shift) {
case RT5668_ADC_STO1_ASRC_SHIFT:
reg = RT5668_ASRC_3;
shift = RT5668_AD_STO1_TRACK_SHIFT;
case RT5663_ADC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_3;
shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
case RT5668_DAC_STO1_ASRC_SHIFT:
case RT5663_DAC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_2;
shift = RT5668_DA_STO1_TRACK_SHIFT;
shift = RT5663_DA_STO1_TRACK_SHIFT;
break;
default:
return 0;
......@@ -1820,17 +1821,17 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
ad_asrc_en = (snd_soc_read(codec, RT5668_ASRC_3) &
RT5668_AD_STO1_TRACK_MASK) ? 1 : 0;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
return 1;
}
......@@ -1849,7 +1850,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
......@@ -1860,7 +1861,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
unsigned int filter_mask, unsigned int clk_src)
{
struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
unsigned int asrc3_mask = 0;
......@@ -1876,22 +1877,22 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
}
if (filter_mask & RT5663_DA_STEREO_FILTER) {
asrc2_mask |= RT5668_DA_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5668_DA_STO1_TRACK_SHIFT;
asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
}
if (filter_mask & RT5663_AD_STEREO_FILTER) {
switch (rt5668->codec_type) {
case CODEC_TYPE_RT5668:
asrc3_mask |= RT5668_AD_STO1_TRACK_MASK;
asrc3_value |= clk_src << RT5668_AD_STO1_TRACK_SHIFT;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
}
......@@ -1900,7 +1901,7 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
asrc2_value);
if (asrc3_mask)
snd_soc_update_bits(codec, RT5668_ASRC_3, asrc3_mask,
snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
asrc3_value);
return 0;
......@@ -1908,82 +1909,82 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
/* Analog Mixer */
static const struct snd_kcontrol_new rt5668_recmix1l[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1L,
RT5668_RECMIX1L_BST2_SHIFT, 1, 1),
SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5668_RECMIX1L,
RT5668_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
static const struct snd_kcontrol_new rt5663_recmix1l[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_recmix1r[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1R,
RT5668_RECMIX1R_BST2_SHIFT, 1, 1),
static const struct snd_kcontrol_new rt5663_recmix1r[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
};
/* Digital Mixer */
static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_L1_SHIFT, 1, 1),
RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_L2_SHIFT, 1, 1),
RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_R1_SHIFT, 1, 1),
RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_R2_SHIFT, 1, 1),
RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
RT5668_M_ADCMIX_L_SHIFT, 1, 1),
RT5663_M_ADCMIX_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
RT5668_M_DAC1_L_SHIFT, 1, 1),
RT5663_M_DAC1_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
RT5668_M_ADCMIX_R_SHIFT, 1, 1),
RT5663_M_ADCMIX_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
RT5668_M_DAC1_R_SHIFT, 1, 1),
RT5663_M_DAC1_R_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_L1_STO_L_SHIFT, 1, 1),
RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_R1_STO_L_SHIFT, 1, 1),
RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_L1_STO_R_SHIFT, 1, 1),
RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_R1_STO_R_SHIFT, 1, 1),
RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
};
/* Out Switch */
static const struct snd_kcontrol_new rt5668_hpo_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_AMP_2,
RT5668_EN_DAC_HPO_SHIFT, 1, 0);
static const struct snd_kcontrol_new rt5663_hpo_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
RT5663_EN_DAC_HPO_SHIFT, 1, 0);
/* Stereo ADC source */
static const char * const rt5668_sto1_adc_src[] = {
static const char * const rt5663_sto1_adc_src[] = {
"ADC L", "ADC R"
};
static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_L_SRC_SHIFT, rt5668_sto1_adc_src);
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
SOC_DAPM_ENUM("STO1 ADC L Mux", rt5668_sto1_adcl_enum);
static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_R_SRC_SHIFT, rt5668_sto1_adc_src);
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
SOC_DAPM_ENUM("STO1 ADC R Mux", rt5668_sto1_adcr_enum);
static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
/* RT5663: Analog DACL1 input source */
static const char * const rt5663_alg_dacl_src[] = {
......@@ -2015,12 +2016,12 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5668_SEL_PM_HP_SHIFT, RT5668_SEL_PM_HP_HIGH);
RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
RT5668_HP_SIG_SRC1_MASK,
RT5668_HP_SIG_SRC1_SILENCE);
RT5663_HP_SIG_SRC1_MASK,
RT5663_HP_SIG_SRC1_SILENCE);
} else {
snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
......@@ -2028,7 +2029,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
0x0030);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_DIS);
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
......@@ -2041,14 +2042,14 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
break;
case SND_SOC_DAPM_PRE_PMD:
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
RT5668_HP_SIG_SRC1_MASK,
RT5668_HP_SIG_SRC1_REG);
RT5663_HP_SIG_SRC1_MASK,
RT5663_HP_SIG_SRC1_REG);
} else {
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_EN);
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
0x000b);
......@@ -2062,7 +2063,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
return 0;
}
static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
......@@ -2070,13 +2071,13 @@ static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK,
RT5668_PWR_BST2 | RT5668_PWR_BST2_OP);
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 0);
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
break;
default:
......@@ -2110,14 +2111,14 @@ static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
}
static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5668_PWR_PLL_SHIFT, 0,
SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
NULL, 0),
/* micbias */
SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
RT5668_PWR_MB1_SHIFT, 0),
RT5663_PWR_MB1_SHIFT, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
RT5668_PWR_MB2_SHIFT, 0),
RT5663_PWR_MB2_SHIFT, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN1P"),
......@@ -2125,14 +2126,14 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* REC Mixer Power */
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
RT5668_PWR_RECMIX1_SHIFT, 0, NULL, 0),
RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
RT5668_PWR_ADC_L1_SHIFT, 0, NULL, 0),
RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
RT5668_CKGEN_ADCC_SHIFT, 0, NULL, 0),
RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
/* ADC Mixer */
SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
......@@ -2141,10 +2142,10 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* ADC Filter Power */
SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
RT5668_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5668_PWR_I2S1_SHIFT, 0,
SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
......@@ -2166,7 +2167,7 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
RT5668_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
......@@ -2174,9 +2175,9 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* DACs */
SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
RT5668_PWR_DAC_L1_SHIFT, 0, NULL, 0),
RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
RT5668_PWR_DAC_R1_SHIFT, 0, NULL, 0),
RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
......@@ -2189,21 +2190,21 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
RT5668_PWR_LDO2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5668_PWR_VOL,
RT5668_PWR_MIC_DET_SHIFT, 0, NULL, 0),
RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
RT5668_I2S1_ASRC_SHIFT, 0, NULL, 0),
RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
RT5668_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
RT5668_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN2P"),
......@@ -2212,51 +2213,51 @@ static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
RT5668_PWR_CBJ_SHIFT, 0, NULL, 0),
RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
rt5668_bst2_power, SND_SOC_DAPM_PRE_PMD |
rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_recmix1l,
ARRAY_SIZE(rt5668_recmix1l)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5668_recmix1r,
ARRAY_SIZE(rt5668_recmix1r)),
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
ARRAY_SIZE(rt5663_recmix1l)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
ARRAY_SIZE(rt5663_recmix1r)),
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
RT5668_PWR_RECMIX2_SHIFT, 0, NULL, 0),
RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
RT5668_PWR_ADC_R1_SHIFT, 0, NULL, 0),
RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adcl_mux),
&rt5663_sto1_adcl_mux),
SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adcr_mux),
&rt5663_sto1_adcr_mux),
/* ADC Mix */
SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5668_sto1_adc_r_mix, ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
/* Analog DAC Clock */
SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
RT5668_CKGEN_DAC1_SHIFT, 0, NULL, 0),
RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
/* Headphone out */
SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
&rt5668_hpo_switch),
&rt5663_hpo_switch),
};
static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
......@@ -2267,7 +2268,7 @@ static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
/* LDO */
SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
......@@ -2341,7 +2342,7 @@ static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
{ "HP Amp", NULL, "DAC R" },
};
static const struct snd_soc_dapm_route rt5668_specific_dapm_routes[] = {
static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
{ "MICBIAS1", NULL, "LDO2" },
{ "MICBIAS2", NULL, "LDO2" },
......@@ -2440,26 +2441,26 @@ static int rt5663_hw_params(struct snd_pcm_substream *substream,
switch (params_width(params)) {
case 8:
val_len = RT5668_I2S_DL_8;
val_len = RT5663_I2S_DL_8;
break;
case 16:
val_len = RT5668_I2S_DL_16;
val_len = RT5663_I2S_DL_16;
break;
case 20:
val_len = RT5668_I2S_DL_20;
val_len = RT5663_I2S_DL_20;
break;
case 24:
val_len = RT5668_I2S_DL_24;
val_len = RT5663_I2S_DL_24;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_I2S1_SDP,
RT5668_I2S_DL_MASK, val_len);
RT5663_I2S_DL_MASK, val_len);
snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
RT5668_I2S_PD1_MASK, pre_div << RT5668_I2S_PD1_SHIFT);
RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
return 0;
}
......@@ -2473,7 +2474,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_CBM_CFM:
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5668_I2S_MS_S;
reg_val |= RT5663_I2S_MS_S;
break;
default:
return -EINVAL;
......@@ -2483,7 +2484,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5668_I2S_BP_INV;
reg_val |= RT5663_I2S_BP_INV;
break;
default:
return -EINVAL;
......@@ -2493,20 +2494,20 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5668_I2S_DF_LEFT;
reg_val |= RT5663_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5668_I2S_DF_PCM_A;
reg_val |= RT5663_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5668_I2S_DF_PCM_B;
reg_val |= RT5663_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5668_I2S_MS_MASK |
RT5668_I2S_BP_MASK | RT5668_I2S_DF_MASK, reg_val);
snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
return 0;
}
......@@ -2535,7 +2536,7 @@ static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5668_SCLK_SRC_MASK,
snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
reg_val);
rt5663->sysclk = freq;
rt5663->sysclk_src = clk_id;
......@@ -2569,17 +2570,17 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
return 0;
}
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
mask = RT5668_PLL1_SRC_MASK;
shift = RT5668_PLL1_SRC_SHIFT;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
mask = RT5663_V2_PLL1_SRC_MASK;
shift = RT5663_V2_PLL1_SRC_SHIFT;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
mask = RT5663_PLL1_SRC_MASK;
shift = RT5663_PLL1_SRC_SHIFT;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
......@@ -2607,10 +2608,10 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
pll_code.k_code);
snd_soc_write(codec, RT5663_PLL_1,
pll_code.n_code << RT5668_PLL_N_SHIFT | pll_code.k_code);
pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
snd_soc_write(codec, RT5663_PLL_2,
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SHIFT |
pll_code.m_bp << RT5668_PLL_M_BP_SHIFT);
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
rt5663->pll_in = freq_in;
rt5663->pll_out = freq_out;
......@@ -2627,20 +2628,20 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int val = 0, reg;
if (rx_mask || tx_mask)
val |= RT5668_TDM_MODE_TDM;
val |= RT5663_TDM_MODE_TDM;
switch (slots) {
case 4:
val |= RT5668_TDM_IN_CH_4;
val |= RT5668_TDM_OUT_CH_4;
val |= RT5663_TDM_IN_CH_4;
val |= RT5663_TDM_OUT_CH_4;
break;
case 6:
val |= RT5668_TDM_IN_CH_6;
val |= RT5668_TDM_OUT_CH_6;
val |= RT5663_TDM_IN_CH_6;
val |= RT5663_TDM_OUT_CH_6;
break;
case 8:
val |= RT5668_TDM_IN_CH_8;
val |= RT5668_TDM_OUT_CH_8;
val |= RT5663_TDM_IN_CH_8;
val |= RT5663_TDM_OUT_CH_8;
break;
case 2:
break;
......@@ -2650,16 +2651,16 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
switch (slot_width) {
case 20:
val |= RT5668_TDM_IN_LEN_20;
val |= RT5668_TDM_OUT_LEN_20;
val |= RT5663_TDM_IN_LEN_20;
val |= RT5663_TDM_OUT_LEN_20;
break;
case 24:
val |= RT5668_TDM_IN_LEN_24;
val |= RT5668_TDM_OUT_LEN_24;
val |= RT5663_TDM_IN_LEN_24;
val |= RT5663_TDM_OUT_LEN_24;
break;
case 32:
val |= RT5668_TDM_IN_LEN_32;
val |= RT5668_TDM_OUT_LEN_32;
val |= RT5663_TDM_IN_LEN_32;
val |= RT5663_TDM_OUT_LEN_32;
break;
case 16:
break;
......@@ -2667,21 +2668,21 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
return -EINVAL;
}
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
reg = RT5663_TDM_2;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
reg = RT5663_TDM_1;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
snd_soc_update_bits(codec, reg, RT5668_TDM_MODE_MASK |
RT5668_TDM_IN_CH_MASK | RT5668_TDM_OUT_CH_MASK |
RT5668_TDM_IN_LEN_MASK | RT5668_TDM_OUT_LEN_MASK, val);
snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
return 0;
}
......@@ -2694,8 +2695,8 @@ static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
if (rt5663->codec_type == CODEC_TYPE_RT5668)
reg = RT5668_TDM_8;
if (rt5663->codec_ver == CODEC_VER_1)
reg = RT5663_TDM_9;
else
reg = RT5663_TDM_5;
......@@ -2736,47 +2737,47 @@ static int rt5663_set_bias_level(struct snd_soc_codec *codec,
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK,
RT5668_PWR_FV1 | RT5668_PWR_FV2);
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_FV1 | RT5663_PWR_FV2);
break;
case SND_SOC_BIAS_PREPARE:
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK,
RT5668_DIG_GATE_CTRL_EN);
RT5663_DIG_GATE_CTRL_MASK,
RT5663_DIG_GATE_CTRL_EN);
snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
RT5668_EN_ANA_CLK_DET_MASK |
RT5668_PWR_CLK_DET_MASK,
RT5668_EN_ANA_CLK_DET_AUTO |
RT5668_PWR_CLK_DET_EN);
RT5663_EN_ANA_CLK_DET_MASK |
RT5663_PWR_CLK_DET_MASK,
RT5663_EN_ANA_CLK_DET_AUTO |
RT5663_PWR_CLK_DET_EN);
}
break;
case SND_SOC_BIAS_STANDBY:
if (rt5663->codec_type == CODEC_TYPE_RT5668)
if (rt5663->codec_ver == CODEC_VER_1)
snd_soc_update_bits(codec, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK,
RT5668_DIG_GATE_CTRL_DIS);
RT5663_DIG_GATE_CTRL_MASK,
RT5663_DIG_GATE_CTRL_DIS);
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK |
RT5668_PWR_MB_MASK, RT5668_PWR_VREF1 |
RT5668_PWR_VREF2 | RT5668_PWR_MB);
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
RT5663_PWR_VREF2 | RT5663_PWR_MB);
usleep_range(10000, 10005);
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
RT5668_EN_ANA_CLK_DET_MASK |
RT5668_PWR_CLK_DET_MASK,
RT5668_EN_ANA_CLK_DET_DIS |
RT5668_PWR_CLK_DET_DIS);
RT5663_EN_ANA_CLK_DET_MASK |
RT5663_PWR_CLK_DET_MASK,
RT5663_EN_ANA_CLK_DET_DIS |
RT5663_PWR_CLK_DET_DIS);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
RT5668_PWR_FV1 | RT5668_PWR_FV2, 0x0);
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
break;
default:
......@@ -2793,18 +2794,18 @@ static int rt5663_probe(struct snd_soc_codec *codec)
rt5663->codec = codec;
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_dapm_new_controls(dapm,
rt5668_specific_dapm_widgets,
ARRAY_SIZE(rt5668_specific_dapm_widgets));
rt5663_v2_specific_dapm_widgets,
ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5668_specific_dapm_routes,
ARRAY_SIZE(rt5668_specific_dapm_routes));
snd_soc_add_codec_controls(codec, rt5668_specific_controls,
ARRAY_SIZE(rt5668_specific_controls));
rt5663_v2_specific_dapm_routes,
ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
ARRAY_SIZE(rt5663_v2_specific_controls));
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
snd_soc_dapm_new_controls(dapm,
rt5663_specific_dapm_widgets,
ARRAY_SIZE(rt5663_specific_dapm_widgets));
......@@ -2905,16 +2906,16 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
}
};
static const struct regmap_config rt5668_regmap = {
static const struct regmap_config rt5663_v2_regmap = {
.reg_bits = 16,
.val_bits = 16,
.use_single_rw = true,
.max_register = 0x07fa,
.volatile_reg = rt5668_volatile_register,
.readable_reg = rt5668_readable_register,
.volatile_reg = rt5663_v2_volatile_register,
.readable_reg = rt5663_v2_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt5668_reg,
.num_reg_defaults = ARRAY_SIZE(rt5668_reg),
.reg_defaults = rt5663_v2_reg,
.num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
};
static const struct regmap_config rt5663_regmap = {
......@@ -2939,7 +2940,6 @@ static const struct regmap_config temp_regmap = {
};
static const struct i2c_device_id rt5663_i2c_id[] = {
{ "rt5668", 0 },
{ "rt5663", 0 },
{}
};
......@@ -2947,7 +2947,6 @@ MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5663_of_match[] = {
{ .compatible = "realtek,rt5668", },
{ .compatible = "realtek,rt5663", },
{},
};
......@@ -2956,80 +2955,79 @@ MODULE_DEVICE_TABLE(of, rt5663_of_match);
#ifdef CONFIG_ACPI
static struct acpi_device_id rt5663_acpi_match[] = {
{ "10EC5668", 0},
{ "10EC5663", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
#endif
static void rt5668_calibrate(struct rt5663_priv *rt5668)
static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
{
regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0xa402);
regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x0100);
regmap_write(rt5668->regmap, RT5663_RECMIX, 0x4040);
regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x0001);
regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0380);
regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1000);
regmap_write(rt5668->regmap, RT5663_CHOP_DAC_L, 0x3030);
regmap_write(rt5668->regmap, RT5663_CALIB_ADC, 0x3c05);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa23e);
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
msleep(40);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf23e);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x0321);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0xfc00);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
msleep(500);
}
static void rt5663_calibrate(struct rt5663_priv *rt5668)
static void rt5663_calibrate(struct rt5663_priv *rt5663)
{
int value, count;
regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0280);
regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x8001);
regmap_write(rt5668->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa2be);
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0280);
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
msleep(20);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf2be);
regmap_write(rt5668->regmap, RT5663_PWR_DIG_2, 0x8400);
regmap_write(rt5668->regmap, RT5663_CHOP_ADC, 0x3000);
regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x8df8);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_2, 0x0003);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_3, 0x018c);
regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1111);
regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
regmap_write(rt5668->regmap, RT5663_DEPOP_2, 0x3003);
regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
regmap_write(rt5668->regmap, RT5663_DACREF_LDO, 0x3b0b);
regmap_write(rt5668->regmap, RT5663_STO_DAC_MIXER, 0x2080);
regmap_write(rt5668->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
regmap_write(rt5668->regmap, RT5663_HP_BIAS, 0xabba);
regmap_write(rt5668->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
regmap_write(rt5668->regmap, RT5663_HP_OUT_EN, 0x8088);
regmap_write(rt5668->regmap, RT5663_STO_DRE_9, 0x0017);
regmap_write(rt5668->regmap, RT5663_STO_DRE_10, 0x0017);
regmap_write(rt5668->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
regmap_write(rt5668->regmap, RT5663_RECMIX, 0x0005);
regmap_write(rt5668->regmap, RT5663_ADDA_RST, 0xc000);
regmap_write(rt5668->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x00c9);
regmap_write(rt5668->regmap, RT5663_DUMMY_1, 0x004c);
regmap_write(rt5668->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0x4702);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0003);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1111);
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x2080);
regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xabba);
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4702);
msleep(200);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0x0069);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_3, 0x06c2);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06c2);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
count = 0;
while (true) {
regmap_read(rt5668->regmap, RT5663_HP_CALIB_1_1, &value);
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
......@@ -3066,17 +3064,17 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
}
regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
switch (val) {
case RT5668_DEVICE_ID:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
rt5663->codec_type = CODEC_TYPE_RT5668;
case RT5663_DEVICE_ID_2:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
rt5663->codec_ver = CODEC_VER_1;
break;
case RT5663_DEVICE_ID:
case RT5663_DEVICE_ID_1:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
rt5663->codec_type = CODEC_TYPE_RT5663;
rt5663->codec_ver = CODEC_VER_0;
break;
default:
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5663 or rt5668\n",
"Device with ID register %#x is not rt5663\n",
val);
return -ENODEV;
}
......@@ -3091,11 +3089,11 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
/* reset and calibrate */
regmap_write(rt5663->regmap, RT5663_RESET, 0);
regcache_cache_bypass(rt5663->regmap, true);
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
rt5668_calibrate(rt5663);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
rt5663_v2_calibrate(rt5663);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
rt5663_calibrate(rt5663);
break;
default:
......@@ -3106,46 +3104,55 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
dev_dbg(&i2c->dev, "calibrate done\n");
/* GPIO1 as IRQ */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5668_GP1_PIN_MASK,
RT5668_GP1_PIN_IRQ);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
RT5663_GP1_PIN_IRQ);
/* 4btn inline command debounce */
regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
RT5668_4BTN_CLK_DEB_MASK, RT5668_4BTN_CLK_DEB_65MS);
RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
/* JD1 */
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
RT5668_IRQ_POW_SAV_MASK | RT5668_IRQ_POW_SAV_JD1_MASK,
RT5668_IRQ_POW_SAV_EN | RT5668_IRQ_POW_SAV_JD1_EN);
RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
RT5668_PWR_JD1_MASK, RT5668_PWR_JD1);
RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5668_EN_CB_JD_MASK, RT5668_EN_CB_JD_EN);
RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
RT5668_HP_SIG_SRC1_MASK, RT5668_HP_SIG_SRC1_REG);
RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
RT5668_VREF_BIAS_MASK | RT5668_CBJ_DET_MASK |
RT5668_DET_TYPE_MASK, RT5668_VREF_BIAS_REG |
RT5668_CBJ_DET_EN | RT5668_DET_TYPE_QFN);
RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
/* Set GPIO4 and GPIO8 as input for combo jack */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
RT5668_GP4_PIN_CONF_MASK, RT5668_GP4_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5668_GPIO_3,
RT5668_GP8_PIN_CONF_MASK, RT5668_GP8_PIN_CONF_INPUT);
RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
RT5668_LDO1_DVO_MASK | RT5668_AMP_HP_MASK,
RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
msleep(20);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
RT5663_GP1_PIN_CONF_MASK, RT5663_GP1_PIN_CONF_OUTPUT);
RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
/* DACREF LDO control */
regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
0x3a0a);
......
sound/soc/codecs/rt5663.h
View file @ b35ddfd4
......@@ -18,655 +18,652 @@
#define RT5663_VENDOR_ID_1 0x00fe
#define RT5663_VENDOR_ID_2 0x00ff
#define RT5668_LOUT_CTRL 0x0001
#define RT5668_HP_AMP_2 0x0003
#define RT5668_MONO_OUT 0x0004
#define RT5668_MONO_GAIN 0x0007
#define RT5668_AEC_BST 0x000b
#define RT5668_IN1_IN2 0x000c
#define RT5668_IN3_IN4 0x000d
#define RT5668_INL1_INR1 0x000f
#define RT5668_CBJ_TYPE_2 0x0011
#define RT5668_CBJ_TYPE_3 0x0012
#define RT5668_CBJ_TYPE_4 0x0013
#define RT5668_CBJ_TYPE_5 0x0014
#define RT5668_CBJ_TYPE_8 0x0017
#define RT5663_LOUT_CTRL 0x0001
#define RT5663_HP_AMP_2 0x0003
#define RT5663_MONO_OUT 0x0004
#define RT5663_MONO_GAIN 0x0007
#define RT5663_AEC_BST 0x000b
#define RT5663_IN1_IN2 0x000c
#define RT5663_IN3_IN4 0x000d
#define RT5663_INL1_INR1 0x000f
#define RT5663_CBJ_TYPE_2 0x0011
#define RT5663_CBJ_TYPE_3 0x0012
#define RT5663_CBJ_TYPE_4 0x0013
#define RT5663_CBJ_TYPE_5 0x0014
#define RT5663_CBJ_TYPE_8 0x0017
/* I/O - ADC/DAC/DMIC */
#define RT5668_DAC3_DIG_VOL 0x001a
#define RT5668_DAC3_CTRL 0x001b
#define RT5668_MONO_ADC_DIG_VOL 0x001d
#define RT5668_STO2_ADC_DIG_VOL 0x001e
#define RT5668_MONO_ADC_BST_GAIN 0x0020
#define RT5668_STO2_ADC_BST_GAIN 0x0021
#define RT5668_SIDETONE_CTRL 0x0024
#define RT5663_DAC3_DIG_VOL 0x001a
#define RT5663_DAC3_CTRL 0x001b
#define RT5663_MONO_ADC_DIG_VOL 0x001d
#define RT5663_STO2_ADC_DIG_VOL 0x001e
#define RT5663_MONO_ADC_BST_GAIN 0x0020
#define RT5663_STO2_ADC_BST_GAIN 0x0021
#define RT5663_SIDETONE_CTRL 0x0024
/* Mixer - D-D */
#define RT5668_MONO1_ADC_MIXER 0x0027
#define RT5668_STO2_ADC_MIXER 0x0028
#define RT5668_MONO_DAC_MIXER 0x002b
#define RT5668_DAC2_SRC_CTRL 0x002e
#define RT5668_IF_3_4_DATA_CTL 0x002f
#define RT5668_IF_5_DATA_CTL 0x0030
#define RT5668_PDM_OUT_CTL 0x0031
#define RT5668_PDM_I2C_DATA_CTL1 0x0032
#define RT5668_PDM_I2C_DATA_CTL2 0x0033
#define RT5668_PDM_I2C_DATA_CTL3 0x0034
#define RT5668_PDM_I2C_DATA_CTL4 0x0035
#define RT5663_MONO1_ADC_MIXER 0x0027
#define RT5663_STO2_ADC_MIXER 0x0028
#define RT5663_MONO_DAC_MIXER 0x002b
#define RT5663_DAC2_SRC_CTRL 0x002e
#define RT5663_IF_3_4_DATA_CTL 0x002f
#define RT5663_IF_5_DATA_CTL 0x0030
#define RT5663_PDM_OUT_CTL 0x0031
#define RT5663_PDM_I2C_DATA_CTL1 0x0032
#define RT5663_PDM_I2C_DATA_CTL2 0x0033
#define RT5663_PDM_I2C_DATA_CTL3 0x0034
#define RT5663_PDM_I2C_DATA_CTL4 0x0035
/*Mixer - Analog*/
#define RT5668_RECMIX1_NEW 0x003a
#define RT5668_RECMIX1L_0 0x003b
#define RT5668_RECMIX1L 0x003c
#define RT5668_RECMIX1R_0 0x003d
#define RT5668_RECMIX1R 0x003e
#define RT5668_RECMIX2_NEW 0x003f
#define RT5668_RECMIX2_L_2 0x0041
#define RT5668_RECMIX2_R 0x0042
#define RT5668_RECMIX2_R_2 0x0043
#define RT5668_CALIB_REC_LR 0x0044
#define RT5668_ALC_BK_GAIN 0x0049
#define RT5668_MONOMIX_GAIN 0x004a
#define RT5668_MONOMIX_IN_GAIN 0x004b
#define RT5668_OUT_MIXL_GAIN 0x004d
#define RT5668_OUT_LMIX_IN_GAIN 0x004e
#define RT5668_OUT_RMIX_IN_GAIN 0x004f
#define RT5668_OUT_RMIX_IN_GAIN1 0x0050
#define RT5668_LOUT_MIXER_CTRL 0x0052
#define RT5663_RECMIX1_NEW 0x003a
#define RT5663_RECMIX1L_0 0x003b
#define RT5663_RECMIX1L 0x003c
#define RT5663_RECMIX1R_0 0x003d
#define RT5663_RECMIX1R 0x003e
#define RT5663_RECMIX2_NEW 0x003f
#define RT5663_RECMIX2_L_2 0x0041
#define RT5663_RECMIX2_R 0x0042
#define RT5663_RECMIX2_R_2 0x0043
#define RT5663_CALIB_REC_LR 0x0044
#define RT5663_ALC_BK_GAIN 0x0049
#define RT5663_MONOMIX_GAIN 0x004a
#define RT5663_MONOMIX_IN_GAIN 0x004b
#define RT5663_OUT_MIXL_GAIN 0x004d
#define RT5663_OUT_LMIX_IN_GAIN 0x004e
#define RT5663_OUT_RMIX_IN_GAIN 0x004f
#define RT5663_OUT_RMIX_IN_GAIN1 0x0050
#define RT5663_LOUT_MIXER_CTRL 0x0052
/* Power */
#define RT5668_PWR_VOL 0x0067
#define RT5663_PWR_VOL 0x0067
#define RT5668_ADCDAC_RST 0x006d
#define RT5663_ADCDAC_RST 0x006d
/* Format - ADC/DAC */
#define RT5668_I2S34_SDP 0x0071
#define RT5668_I2S5_SDP 0x0072
/* Format - TDM Control */
#define RT5668_TDM_5 0x007c
#define RT5668_TDM_6 0x007d
#define RT5668_TDM_7 0x007e
#define RT5668_TDM_8 0x007f
#define RT5663_I2S34_SDP 0x0071
#define RT5663_I2S5_SDP 0x0072
/* Function - Analog */
#define RT5668_ASRC_3 0x0085
#define RT5668_ASRC_6 0x0088
#define RT5668_ASRC_7 0x0089
#define RT5668_PLL_TRK_13 0x0099
#define RT5668_I2S_M_CLK_CTL 0x00a0
#define RT5668_FDIV_I2S34_M_CLK 0x00a1
#define RT5668_FDIV_I2S34_M_CLK2 0x00a2
#define RT5668_FDIV_I2S5_M_CLK 0x00a3
#define RT5668_FDIV_I2S5_M_CLK2 0x00a4
#define RT5663_ASRC_3 0x0085
#define RT5663_ASRC_6 0x0088
#define RT5663_ASRC_7 0x0089
#define RT5663_PLL_TRK_13 0x0099
#define RT5663_I2S_M_CLK_CTL 0x00a0
#define RT5663_FDIV_I2S34_M_CLK 0x00a1
#define RT5663_FDIV_I2S34_M_CLK2 0x00a2
#define RT5663_FDIV_I2S5_M_CLK 0x00a3
#define RT5663_FDIV_I2S5_M_CLK2 0x00a4
/* Function - Digital */
#define RT5668_IRQ_4 0x00b9
#define RT5668_GPIO_3 0x00c2
#define RT5668_GPIO_4 0x00c3
#define RT5668_GPIO_STA 0x00c4
#define RT5668_HP_AMP_DET1 0x00d0
#define RT5668_HP_AMP_DET2 0x00d1
#define RT5668_HP_AMP_DET3 0x00d2
#define RT5668_MID_BD_HP_AMP 0x00d3
#define RT5668_LOW_BD_HP_AMP 0x00d4
#define RT5668_SOF_VOL_ZC2 0x00da
#define RT5668_ADC_STO2_ADJ1 0x00ee
#define RT5668_ADC_STO2_ADJ2 0x00ef
#define RT5663_V2_IRQ_4 0x00b9
#define RT5663_GPIO_3 0x00c2
#define RT5663_GPIO_4 0x00c3
#define RT5663_GPIO_STA2 0x00c4
#define RT5663_HP_AMP_DET1 0x00d0
#define RT5663_HP_AMP_DET2 0x00d1
#define RT5663_HP_AMP_DET3 0x00d2
#define RT5663_MID_BD_HP_AMP 0x00d3
#define RT5663_LOW_BD_HP_AMP 0x00d4
#define RT5663_SOF_VOL_ZC2 0x00da
#define RT5663_ADC_STO2_ADJ1 0x00ee
#define RT5663_ADC_STO2_ADJ2 0x00ef
/* General Control */
#define RT5668_A_JD_CTRL 0x00f0
#define RT5668_JD1_TRES_CTRL 0x00f1
#define RT5668_JD2_TRES_CTRL 0x00f2
#define RT5668_JD_CTRL2 0x00f7
#define RT5668_DUM_REG_2 0x00fb
#define RT5668_DUM_REG_3 0x00fc
#define RT5668_DACADC_DIG_VOL2 0x0101
#define RT5668_DIG_IN_PIN2 0x0133
#define RT5668_PAD_DRV_CTL1 0x0136
#define RT5668_SOF_RAM_DEPOP 0x0138
#define RT5668_VOL_TEST 0x013f
#define RT5668_TEST_MODE_3 0x0147
#define RT5668_TEST_MODE_4 0x0148
#define RT5668_MONO_DYNA_1 0x0170
#define RT5668_MONO_DYNA_2 0x0171
#define RT5668_MONO_DYNA_3 0x0172
#define RT5668_MONO_DYNA_4 0x0173
#define RT5668_MONO_DYNA_5 0x0174
#define RT5668_MONO_DYNA_6 0x0175
#define RT5668_STO1_SIL_DET 0x0190
#define RT5668_MONOL_SIL_DET 0x0191
#define RT5668_MONOR_SIL_DET 0x0192
#define RT5668_STO2_DAC_SIL 0x0193
#define RT5668_PWR_SAV_CTL1 0x0194
#define RT5668_PWR_SAV_CTL2 0x0195
#define RT5668_PWR_SAV_CTL3 0x0196
#define RT5668_PWR_SAV_CTL4 0x0197
#define RT5668_PWR_SAV_CTL5 0x0198
#define RT5668_PWR_SAV_CTL6 0x0199
#define RT5668_MONO_AMP_CAL1 0x01a0
#define RT5668_MONO_AMP_CAL2 0x01a1
#define RT5668_MONO_AMP_CAL3 0x01a2
#define RT5668_MONO_AMP_CAL4 0x01a3
#define RT5668_MONO_AMP_CAL5 0x01a4
#define RT5668_MONO_AMP_CAL6 0x01a5
#define RT5668_MONO_AMP_CAL7 0x01a6
#define RT5668_MONO_AMP_CAL_ST1 0x01a7
#define RT5668_MONO_AMP_CAL_ST2 0x01a8
#define RT5668_MONO_AMP_CAL_ST3 0x01a9
#define RT5668_MONO_AMP_CAL_ST4 0x01aa
#define RT5668_MONO_AMP_CAL_ST5 0x01ab
#define RT5668_HP_IMP_SEN_13 0x01b9
#define RT5668_HP_IMP_SEN_14 0x01ba
#define RT5668_HP_IMP_SEN_6 0x01bb
#define RT5668_HP_IMP_SEN_7 0x01bc
#define RT5668_HP_IMP_SEN_8 0x01bd
#define RT5668_HP_IMP_SEN_9 0x01be
#define RT5668_HP_IMP_SEN_10 0x01bf
#define RT5668_HP_LOGIC_3 0x01dc
#define RT5668_HP_CALIB_ST10 0x01f3
#define RT5668_HP_CALIB_ST11 0x01f4
#define RT5668_PRO_REG_TBL_4 0x0203
#define RT5668_PRO_REG_TBL_5 0x0204
#define RT5668_PRO_REG_TBL_6 0x0205
#define RT5668_PRO_REG_TBL_7 0x0206
#define RT5668_PRO_REG_TBL_8 0x0207
#define RT5668_PRO_REG_TBL_9 0x0208
#define RT5668_SAR_ADC_INL_1 0x0210
#define RT5668_SAR_ADC_INL_2 0x0211
#define RT5668_SAR_ADC_INL_3 0x0212
#define RT5668_SAR_ADC_INL_4 0x0213
#define RT5668_SAR_ADC_INL_5 0x0214
#define RT5668_SAR_ADC_INL_6 0x0215
#define RT5668_SAR_ADC_INL_7 0x0216
#define RT5668_SAR_ADC_INL_8 0x0217
#define RT5668_SAR_ADC_INL_9 0x0218
#define RT5668_SAR_ADC_INL_10 0x0219
#define RT5668_SAR_ADC_INL_11 0x021a
#define RT5668_SAR_ADC_INL_12 0x021b
#define RT5668_DRC_CTRL_1 0x02ff
#define RT5668_DRC1_CTRL_2 0x0301
#define RT5668_DRC1_CTRL_3 0x0302
#define RT5668_DRC1_CTRL_4 0x0303
#define RT5668_DRC1_CTRL_5 0x0304
#define RT5668_DRC1_CTRL_6 0x0305
#define RT5668_DRC1_HD_CTRL_1 0x0306
#define RT5668_DRC1_HD_CTRL_2 0x0307
#define RT5668_DRC1_PRI_REG_1 0x0310
#define RT5668_DRC1_PRI_REG_2 0x0311
#define RT5668_DRC1_PRI_REG_3 0x0312
#define RT5668_DRC1_PRI_REG_4 0x0313
#define RT5668_DRC1_PRI_REG_5 0x0314
#define RT5668_DRC1_PRI_REG_6 0x0315
#define RT5668_DRC1_PRI_REG_7 0x0316
#define RT5668_DRC1_PRI_REG_8 0x0317
#define RT5668_ALC_PGA_CTL_1 0x0330
#define RT5668_ALC_PGA_CTL_2 0x0331
#define RT5668_ALC_PGA_CTL_3 0x0332
#define RT5668_ALC_PGA_CTL_4 0x0333
#define RT5668_ALC_PGA_CTL_5 0x0334
#define RT5668_ALC_PGA_CTL_6 0x0335
#define RT5668_ALC_PGA_CTL_7 0x0336
#define RT5668_ALC_PGA_CTL_8 0x0337
#define RT5668_ALC_PGA_REG_1 0x0338
#define RT5668_ALC_PGA_REG_2 0x0339
#define RT5668_ALC_PGA_REG_3 0x033a
#define RT5668_ADC_EQ_RECOV_1 0x03c0
#define RT5668_ADC_EQ_RECOV_2 0x03c1
#define RT5668_ADC_EQ_RECOV_3 0x03c2
#define RT5668_ADC_EQ_RECOV_4 0x03c3
#define RT5668_ADC_EQ_RECOV_5 0x03c4
#define RT5668_ADC_EQ_RECOV_6 0x03c5
#define RT5668_ADC_EQ_RECOV_7 0x03c6
#define RT5668_ADC_EQ_RECOV_8 0x03c7
#define RT5668_ADC_EQ_RECOV_9 0x03c8
#define RT5668_ADC_EQ_RECOV_10 0x03c9
#define RT5668_ADC_EQ_RECOV_11 0x03ca
#define RT5668_ADC_EQ_RECOV_12 0x03cb
#define RT5668_ADC_EQ_RECOV_13 0x03cc
#define RT5668_VID_HIDDEN 0x03fe
#define RT5668_VID_CUSTOMER 0x03ff
#define RT5668_SCAN_MODE 0x07f0
#define RT5668_I2C_BYPA 0x07fa
#define RT5663_A_JD_CTRL 0x00f0
#define RT5663_JD1_TRES_CTRL 0x00f1
#define RT5663_JD2_TRES_CTRL 0x00f2
#define RT5663_V2_JD_CTRL2 0x00f7
#define RT5663_DUM_REG_2 0x00fb
#define RT5663_DUM_REG_3 0x00fc
#define RT5663_DACADC_DIG_VOL2 0x0101
#define RT5663_DIG_IN_PIN2 0x0133
#define RT5663_PAD_DRV_CTL1 0x0136
#define RT5663_SOF_RAM_DEPOP 0x0138
#define RT5663_VOL_TEST 0x013f
#define RT5663_MONO_DYNA_1 0x0170
#define RT5663_MONO_DYNA_2 0x0171
#define RT5663_MONO_DYNA_3 0x0172
#define RT5663_MONO_DYNA_4 0x0173
#define RT5663_MONO_DYNA_5 0x0174
#define RT5663_MONO_DYNA_6 0x0175
#define RT5663_STO1_SIL_DET 0x0190
#define RT5663_MONOL_SIL_DET 0x0191
#define RT5663_MONOR_SIL_DET 0x0192
#define RT5663_STO2_DAC_SIL 0x0193
#define RT5663_PWR_SAV_CTL1 0x0194
#define RT5663_PWR_SAV_CTL2 0x0195
#define RT5663_PWR_SAV_CTL3 0x0196
#define RT5663_PWR_SAV_CTL4 0x0197
#define RT5663_PWR_SAV_CTL5 0x0198
#define RT5663_PWR_SAV_CTL6 0x0199
#define RT5663_MONO_AMP_CAL1 0x01a0
#define RT5663_MONO_AMP_CAL2 0x01a1
#define RT5663_MONO_AMP_CAL3 0x01a2
#define RT5663_MONO_AMP_CAL4 0x01a3
#define RT5663_MONO_AMP_CAL5 0x01a4
#define RT5663_MONO_AMP_CAL6 0x01a5
#define RT5663_MONO_AMP_CAL7 0x01a6
#define RT5663_MONO_AMP_CAL_ST1 0x01a7
#define RT5663_MONO_AMP_CAL_ST2 0x01a8
#define RT5663_MONO_AMP_CAL_ST3 0x01a9
#define RT5663_MONO_AMP_CAL_ST4 0x01aa
#define RT5663_MONO_AMP_CAL_ST5 0x01ab
#define RT5663_V2_HP_IMP_SEN_13 0x01b9
#define RT5663_V2_HP_IMP_SEN_14 0x01ba
#define RT5663_V2_HP_IMP_SEN_6 0x01bb
#define RT5663_V2_HP_IMP_SEN_7 0x01bc
#define RT5663_V2_HP_IMP_SEN_8 0x01bd
#define RT5663_V2_HP_IMP_SEN_9 0x01be
#define RT5663_V2_HP_IMP_SEN_10 0x01bf
#define RT5663_HP_LOGIC_3 0x01dc
#define RT5663_HP_CALIB_ST10 0x01f3
#define RT5663_HP_CALIB_ST11 0x01f4
#define RT5663_PRO_REG_TBL_4 0x0203
#define RT5663_PRO_REG_TBL_5 0x0204
#define RT5663_PRO_REG_TBL_6 0x0205
#define RT5663_PRO_REG_TBL_7 0x0206
#define RT5663_PRO_REG_TBL_8 0x0207
#define RT5663_PRO_REG_TBL_9 0x0208
#define RT5663_SAR_ADC_INL_1 0x0210
#define RT5663_SAR_ADC_INL_2 0x0211
#define RT5663_SAR_ADC_INL_3 0x0212
#define RT5663_SAR_ADC_INL_4 0x0213
#define RT5663_SAR_ADC_INL_5 0x0214
#define RT5663_SAR_ADC_INL_6 0x0215
#define RT5663_SAR_ADC_INL_7 0x0216
#define RT5663_SAR_ADC_INL_8 0x0217
#define RT5663_SAR_ADC_INL_9 0x0218
#define RT5663_SAR_ADC_INL_10 0x0219
#define RT5663_SAR_ADC_INL_11 0x021a
#define RT5663_SAR_ADC_INL_12 0x021b
#define RT5663_DRC_CTRL_1 0x02ff
#define RT5663_DRC1_CTRL_2 0x0301
#define RT5663_DRC1_CTRL_3 0x0302
#define RT5663_DRC1_CTRL_4 0x0303
#define RT5663_DRC1_CTRL_5 0x0304
#define RT5663_DRC1_CTRL_6 0x0305
#define RT5663_DRC1_HD_CTRL_1 0x0306
#define RT5663_DRC1_HD_CTRL_2 0x0307
#define RT5663_DRC1_PRI_REG_1 0x0310
#define RT5663_DRC1_PRI_REG_2 0x0311
#define RT5663_DRC1_PRI_REG_3 0x0312
#define RT5663_DRC1_PRI_REG_4 0x0313
#define RT5663_DRC1_PRI_REG_5 0x0314
#define RT5663_DRC1_PRI_REG_6 0x0315
#define RT5663_DRC1_PRI_REG_7 0x0316
#define RT5663_DRC1_PRI_REG_8 0x0317
#define RT5663_ALC_PGA_CTL_1 0x0330
#define RT5663_ALC_PGA_CTL_2 0x0331
#define RT5663_ALC_PGA_CTL_3 0x0332
#define RT5663_ALC_PGA_CTL_4 0x0333
#define RT5663_ALC_PGA_CTL_5 0x0334
#define RT5663_ALC_PGA_CTL_6 0x0335
#define RT5663_ALC_PGA_CTL_7 0x0336
#define RT5663_ALC_PGA_CTL_8 0x0337
#define RT5663_ALC_PGA_REG_1 0x0338
#define RT5663_ALC_PGA_REG_2 0x0339
#define RT5663_ALC_PGA_REG_3 0x033a
#define RT5663_ADC_EQ_RECOV_1 0x03c0
#define RT5663_ADC_EQ_RECOV_2 0x03c1
#define RT5663_ADC_EQ_RECOV_3 0x03c2
#define RT5663_ADC_EQ_RECOV_4 0x03c3
#define RT5663_ADC_EQ_RECOV_5 0x03c4
#define RT5663_ADC_EQ_RECOV_6 0x03c5
#define RT5663_ADC_EQ_RECOV_7 0x03c6
#define RT5663_ADC_EQ_RECOV_8 0x03c7
#define RT5663_ADC_EQ_RECOV_9 0x03c8
#define RT5663_ADC_EQ_RECOV_10 0x03c9
#define RT5663_ADC_EQ_RECOV_11 0x03ca
#define RT5663_ADC_EQ_RECOV_12 0x03cb
#define RT5663_ADC_EQ_RECOV_13 0x03cc
#define RT5663_VID_HIDDEN 0x03fe
#define RT5663_VID_CUSTOMER 0x03ff
#define RT5663_SCAN_MODE 0x07f0
#define RT5663_I2C_BYPA 0x07fa
/* Headphone Amp Control 2 (0x0003) */
#define RT5668_EN_DAC_HPO_MASK (0x1 << 14)
#define RT5668_EN_DAC_HPO_SHIFT 14
#define RT5668_EN_DAC_HPO_DIS (0x0 << 14)
#define RT5668_EN_DAC_HPO_EN (0x1 << 14)
#define RT5663_EN_DAC_HPO_MASK (0x1 << 14)
#define RT5663_EN_DAC_HPO_SHIFT 14
#define RT5663_EN_DAC_HPO_DIS (0x0 << 14)
#define RT5663_EN_DAC_HPO_EN (0x1 << 14)
/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
#define RT5668_GAIN_HP (0x1f << 8)
#define RT5668_GAIN_HP_SHIFT 8
#define RT5663_GAIN_HP (0x1f << 8)
#define RT5663_GAIN_HP_SHIFT 8
/* AEC BST Control (0x000b) */
#define RT5668_GAIN_CBJ_MASK (0xf << 8)
#define RT5668_GAIN_CBJ_SHIFT 8
#define RT5663_GAIN_CBJ_MASK (0xf << 8)
#define RT5663_GAIN_CBJ_SHIFT 8
/* IN1 Control / MIC GND REF (0x000c) */
#define RT5668_IN1_DF_MASK (0x1 << 15)
#define RT5668_IN1_DF_SHIFT 15
#define RT5663_IN1_DF_MASK (0x1 << 15)
#define RT5663_IN1_DF_SHIFT 15
/* Combo Jack and Type Detection Control 1 (0x0010) */
#define RT5668_CBJ_DET_MASK (0x1 << 15)
#define RT5668_CBJ_DET_SHIFT 15
#define RT5668_CBJ_DET_DIS (0x0 << 15)
#define RT5668_CBJ_DET_EN (0x1 << 15)
#define RT5668_DET_TYPE_MASK (0x1 << 12)
#define RT5668_DET_TYPE_SHIFT 12
#define RT5668_DET_TYPE_WLCSP (0x0 << 12)
#define RT5668_DET_TYPE_QFN (0x1 << 12)
#define RT5668_VREF_BIAS_MASK (0x1 << 6)
#define RT5668_VREF_BIAS_SHIFT 6
#define RT5668_VREF_BIAS_FSM (0x0 << 6)
#define RT5668_VREF_BIAS_REG (0x1 << 6)
#define RT5663_CBJ_DET_MASK (0x1 << 15)
#define RT5663_CBJ_DET_SHIFT 15
#define RT5663_CBJ_DET_DIS (0x0 << 15)
#define RT5663_CBJ_DET_EN (0x1 << 15)
#define RT5663_DET_TYPE_MASK (0x1 << 12)
#define RT5663_DET_TYPE_SHIFT 12
#define RT5663_DET_TYPE_WLCSP (0x0 << 12)
#define RT5663_DET_TYPE_QFN (0x1 << 12)
#define RT5663_VREF_BIAS_MASK (0x1 << 6)
#define RT5663_VREF_BIAS_SHIFT 6
#define RT5663_VREF_BIAS_FSM (0x0 << 6)
#define RT5663_VREF_BIAS_REG (0x1 << 6)
/* REC Left Mixer Control 2 (0x003c) */
#define RT5668_RECMIX1L_BST1_CBJ (0x1 << 7)
#define RT5668_RECMIX1L_BST1_CBJ_SHIFT 7
#define RT5668_RECMIX1L_BST2 (0x1 << 4)
#define RT5668_RECMIX1L_BST2_SHIFT 4
#define RT5663_RECMIX1L_BST1_CBJ (0x1 << 7)
#define RT5663_RECMIX1L_BST1_CBJ_SHIFT 7
#define RT5663_RECMIX1L_BST2 (0x1 << 4)
#define RT5663_RECMIX1L_BST2_SHIFT 4
/* REC Right Mixer Control 2 (0x003e) */
#define RT5668_RECMIX1R_BST2 (0x1 << 4)
#define RT5668_RECMIX1R_BST2_SHIFT 4
#define RT5663_RECMIX1R_BST2 (0x1 << 4)
#define RT5663_RECMIX1R_BST2_SHIFT 4
/* DAC1 Digital Volume (0x0019) */
#define RT5668_DAC_L1_VOL_MASK (0xff << 8)
#define RT5668_DAC_L1_VOL_SHIFT 8
#define RT5668_DAC_R1_VOL_MASK (0xff)
#define RT5668_DAC_R1_VOL_SHIFT 0
#define RT5663_DAC_L1_VOL_MASK (0xff << 8)
#define RT5663_DAC_L1_VOL_SHIFT 8
#define RT5663_DAC_R1_VOL_MASK (0xff)
#define RT5663_DAC_R1_VOL_SHIFT 0
/* ADC Digital Volume Control (0x001c) */
#define RT5668_ADC_L_MUTE_MASK (0x1 << 15)
#define RT5668_ADC_L_MUTE_SHIFT 15
#define RT5668_ADC_L_VOL_MASK (0x7f << 8)
#define RT5668_ADC_L_VOL_SHIFT 8
#define RT5668_ADC_R_MUTE_MASK (0x1 << 7)
#define RT5668_ADC_R_MUTE_SHIFT 7
#define RT5668_ADC_R_VOL_MASK (0x7f)
#define RT5668_ADC_R_VOL_SHIFT 0
#define RT5663_ADC_L_MUTE_MASK (0x1 << 15)
#define RT5663_ADC_L_MUTE_SHIFT 15
#define RT5663_ADC_L_VOL_MASK (0x7f << 8)
#define RT5663_ADC_L_VOL_SHIFT 8
#define RT5663_ADC_R_MUTE_MASK (0x1 << 7)
#define RT5663_ADC_R_MUTE_SHIFT 7
#define RT5663_ADC_R_VOL_MASK (0x7f)
#define RT5663_ADC_R_VOL_SHIFT 0
/* Stereo ADC Mixer Control (0x0026) */
#define RT5668_M_STO1_ADC_L1 (0x1 << 15)
#define RT5668_M_STO1_ADC_L1_SHIFT 15
#define RT5668_M_STO1_ADC_L2 (0x1 << 14)
#define RT5668_M_STO1_ADC_L2_SHIFT 14
#define RT5668_STO1_ADC_L1_SRC (0x1 << 13)
#define RT5668_STO1_ADC_L1_SRC_SHIFT 13
#define RT5668_STO1_ADC_L2_SRC (0x1 << 12)
#define RT5668_STO1_ADC_L2_SRC_SHIFT 12
#define RT5668_STO1_ADC_L_SRC (0x3 << 10)
#define RT5668_STO1_ADC_L_SRC_SHIFT 10
#define RT5668_M_STO1_ADC_R1 (0x1 << 7)
#define RT5668_M_STO1_ADC_R1_SHIFT 7
#define RT5668_M_STO1_ADC_R2 (0x1 << 6)
#define RT5668_M_STO1_ADC_R2_SHIFT 6
#define RT5668_STO1_ADC_R1_SRC (0x1 << 5)
#define RT5668_STO1_ADC_R1_SRC_SHIFT 5
#define RT5668_STO1_ADC_R2_SRC (0x1 << 4)
#define RT5668_STO1_ADC_R2_SRC_SHIFT 4
#define RT5668_STO1_ADC_R_SRC (0x3 << 2)
#define RT5668_STO1_ADC_R_SRC_SHIFT 2
#define RT5663_M_STO1_ADC_L1 (0x1 << 15)
#define RT5663_M_STO1_ADC_L1_SHIFT 15
#define RT5663_M_STO1_ADC_L2 (0x1 << 14)
#define RT5663_M_STO1_ADC_L2_SHIFT 14
#define RT5663_STO1_ADC_L1_SRC (0x1 << 13)
#define RT5663_STO1_ADC_L1_SRC_SHIFT 13
#define RT5663_STO1_ADC_L2_SRC (0x1 << 12)
#define RT5663_STO1_ADC_L2_SRC_SHIFT 12
#define RT5663_STO1_ADC_L_SRC (0x3 << 10)
#define RT5663_STO1_ADC_L_SRC_SHIFT 10
#define RT5663_M_STO1_ADC_R1 (0x1 << 7)
#define RT5663_M_STO1_ADC_R1_SHIFT 7
#define RT5663_M_STO1_ADC_R2 (0x1 << 6)
#define RT5663_M_STO1_ADC_R2_SHIFT 6
#define RT5663_STO1_ADC_R1_SRC (0x1 << 5)
#define RT5663_STO1_ADC_R1_SRC_SHIFT 5
#define RT5663_STO1_ADC_R2_SRC (0x1 << 4)
#define RT5663_STO1_ADC_R2_SRC_SHIFT 4
#define RT5663_STO1_ADC_R_SRC (0x3 << 2)
#define RT5663_STO1_ADC_R_SRC_SHIFT 2
/* ADC Mixer to DAC Mixer Control (0x0029) */
#define RT5668_M_ADCMIX_L (0x1 << 15)
#define RT5668_M_ADCMIX_L_SHIFT 15
#define RT5668_M_DAC1_L (0x1 << 14)
#define RT5668_M_DAC1_L_SHIFT 14
#define RT5668_M_ADCMIX_R (0x1 << 7)
#define RT5668_M_ADCMIX_R_SHIFT 7
#define RT5668_M_DAC1_R (0x1 << 6)
#define RT5668_M_DAC1_R_SHIFT 6
#define RT5663_M_ADCMIX_L (0x1 << 15)
#define RT5663_M_ADCMIX_L_SHIFT 15
#define RT5663_M_DAC1_L (0x1 << 14)
#define RT5663_M_DAC1_L_SHIFT 14
#define RT5663_M_ADCMIX_R (0x1 << 7)
#define RT5663_M_ADCMIX_R_SHIFT 7
#define RT5663_M_DAC1_R (0x1 << 6)
#define RT5663_M_DAC1_R_SHIFT 6
/* Stereo DAC Mixer Control (0x002a) */
#define RT5668_M_DAC_L1_STO_L (0x1 << 15)
#define RT5668_M_DAC_L1_STO_L_SHIFT 15
#define RT5668_M_DAC_R1_STO_L (0x1 << 13)
#define RT5668_M_DAC_R1_STO_L_SHIFT 13
#define RT5668_M_DAC_L1_STO_R (0x1 << 7)
#define RT5668_M_DAC_L1_STO_R_SHIFT 7
#define RT5668_M_DAC_R1_STO_R (0x1 << 5)
#define RT5668_M_DAC_R1_STO_R_SHIFT 5
#define RT5663_M_DAC_L1_STO_L (0x1 << 15)
#define RT5663_M_DAC_L1_STO_L_SHIFT 15
#define RT5663_M_DAC_R1_STO_L (0x1 << 13)
#define RT5663_M_DAC_R1_STO_L_SHIFT 13
#define RT5663_M_DAC_L1_STO_R (0x1 << 7)
#define RT5663_M_DAC_L1_STO_R_SHIFT 7
#define RT5663_M_DAC_R1_STO_R (0x1 << 5)
#define RT5663_M_DAC_R1_STO_R_SHIFT 5
/* Power Management for Digital 1 (0x0061) */
#define RT5668_PWR_I2S1 (0x1 << 15)
#define RT5668_PWR_I2S1_SHIFT 15
#define RT5668_PWR_DAC_L1 (0x1 << 11)
#define RT5668_PWR_DAC_L1_SHIFT 11
#define RT5668_PWR_DAC_R1 (0x1 << 10)
#define RT5668_PWR_DAC_R1_SHIFT 10
#define RT5668_PWR_LDO_DACREF_MASK (0x1 << 8)
#define RT5668_PWR_LDO_DACREF_SHIFT 8
#define RT5668_PWR_LDO_DACREF_ON (0x1 << 8)
#define RT5668_PWR_LDO_DACREF_DOWN (0x0 << 8)
#define RT5668_PWR_LDO_SHIFT 8
#define RT5668_PWR_ADC_L1 (0x1 << 4)
#define RT5668_PWR_ADC_L1_SHIFT 4
#define RT5668_PWR_ADC_R1 (0x1 << 3)
#define RT5668_PWR_ADC_R1_SHIFT 3
#define RT5663_PWR_I2S1 (0x1 << 15)
#define RT5663_PWR_I2S1_SHIFT 15
#define RT5663_PWR_DAC_L1 (0x1 << 11)
#define RT5663_PWR_DAC_L1_SHIFT 11
#define RT5663_PWR_DAC_R1 (0x1 << 10)
#define RT5663_PWR_DAC_R1_SHIFT 10
#define RT5663_PWR_LDO_DACREF_MASK (0x1 << 8)
#define RT5663_PWR_LDO_DACREF_SHIFT 8
#define RT5663_PWR_LDO_DACREF_ON (0x1 << 8)
#define RT5663_PWR_LDO_DACREF_DOWN (0x0 << 8)
#define RT5663_PWR_LDO_SHIFT 8
#define RT5663_PWR_ADC_L1 (0x1 << 4)
#define RT5663_PWR_ADC_L1_SHIFT 4
#define RT5663_PWR_ADC_R1 (0x1 << 3)
#define RT5663_PWR_ADC_R1_SHIFT 3
/* Power Management for Digital 2 (0x0062) */
#define RT5668_PWR_ADC_S1F (0x1 << 15)
#define RT5668_PWR_ADC_S1F_SHIFT 15
#define RT5668_PWR_DAC_S1F (0x1 << 10)
#define RT5668_PWR_DAC_S1F_SHIFT 10
#define RT5663_PWR_ADC_S1F (0x1 << 15)
#define RT5663_PWR_ADC_S1F_SHIFT 15
#define RT5663_PWR_DAC_S1F (0x1 << 10)
#define RT5663_PWR_DAC_S1F_SHIFT 10
/* Power Management for Analog 1 (0x0063) */
#define RT5668_PWR_VREF1 (0x1 << 15)
#define RT5668_PWR_VREF1_MASK (0x1 << 15)
#define RT5668_PWR_VREF1_SHIFT 15
#define RT5668_PWR_FV1 (0x1 << 14)
#define RT5668_PWR_FV1_MASK (0x1 << 14)
#define RT5668_PWR_FV1_SHIFT 14
#define RT5668_PWR_VREF2 (0x1 << 13)
#define RT5668_PWR_VREF2_MASK (0x1 << 13)
#define RT5668_PWR_VREF2_SHIFT 13
#define RT5668_PWR_FV2 (0x1 << 12)
#define RT5668_PWR_FV2_MASK (0x1 << 12)
#define RT5668_PWR_FV2_SHIFT 12
#define RT5668_PWR_MB (0x1 << 9)
#define RT5668_PWR_MB_MASK (0x1 << 9)
#define RT5668_PWR_MB_SHIFT 9
#define RT5668_AMP_HP_MASK (0x3 << 2)
#define RT5668_AMP_HP_SHIFT 2
#define RT5668_AMP_HP_1X (0x0 << 2)
#define RT5668_AMP_HP_3X (0x1 << 2)
#define RT5668_AMP_HP_5X (0x3 << 2)
#define RT5668_LDO1_DVO_MASK (0x3)
#define RT5668_LDO1_DVO_SHIFT 0
#define RT5668_LDO1_DVO_0_9V (0x0)
#define RT5668_LDO1_DVO_1_0V (0x1)
#define RT5668_LDO1_DVO_1_2V (0x2)
#define RT5668_LDO1_DVO_1_4V (0x3)
#define RT5663_PWR_VREF1 (0x1 << 15)
#define RT5663_PWR_VREF1_MASK (0x1 << 15)
#define RT5663_PWR_VREF1_SHIFT 15
#define RT5663_PWR_FV1 (0x1 << 14)
#define RT5663_PWR_FV1_MASK (0x1 << 14)
#define RT5663_PWR_FV1_SHIFT 14
#define RT5663_PWR_VREF2 (0x1 << 13)
#define RT5663_PWR_VREF2_MASK (0x1 << 13)
#define RT5663_PWR_VREF2_SHIFT 13
#define RT5663_PWR_FV2 (0x1 << 12)
#define RT5663_PWR_FV2_MASK (0x1 << 12)
#define RT5663_PWR_FV2_SHIFT 12
#define RT5663_PWR_MB (0x1 << 9)
#define RT5663_PWR_MB_MASK (0x1 << 9)
#define RT5663_PWR_MB_SHIFT 9
#define RT5663_AMP_HP_MASK (0x3 << 2)
#define RT5663_AMP_HP_SHIFT 2
#define RT5663_AMP_HP_1X (0x0 << 2)
#define RT5663_AMP_HP_3X (0x1 << 2)
#define RT5663_AMP_HP_5X (0x3 << 2)
#define RT5663_LDO1_DVO_MASK (0x3)
#define RT5663_LDO1_DVO_SHIFT 0
#define RT5663_LDO1_DVO_0_9V (0x0)
#define RT5663_LDO1_DVO_1_0V (0x1)
#define RT5663_LDO1_DVO_1_2V (0x2)
#define RT5663_LDO1_DVO_1_4V (0x3)
/* Power Management for Analog 2 (0x0064) */
#define RT5668_PWR_BST1 (0x1 << 15)
#define RT5668_PWR_BST1_MASK (0x1 << 15)
#define RT5668_PWR_BST1_SHIFT 15
#define RT5668_PWR_BST1_OFF (0x0 << 15)
#define RT5668_PWR_BST1_ON (0x1 << 15)
#define RT5668_PWR_BST2 (0x1 << 14)
#define RT5668_PWR_BST2_MASK (0x1 << 14)
#define RT5668_PWR_BST2_SHIFT 14
#define RT5668_PWR_MB1 (0x1 << 11)
#define RT5668_PWR_MB1_SHIFT 11
#define RT5668_PWR_MB2 (0x1 << 10)
#define RT5668_PWR_MB2_SHIFT 10
#define RT5668_PWR_BST2_OP (0x1 << 6)
#define RT5668_PWR_BST2_OP_MASK (0x1 << 6)
#define RT5668_PWR_BST2_OP_SHIFT 6
#define RT5668_PWR_JD1 (0x1 << 3)
#define RT5668_PWR_JD1_MASK (0x1 << 3)
#define RT5668_PWR_JD1_SHIFT 3
#define RT5668_PWR_JD2 (0x1 << 2)
#define RT5668_PWR_JD2_MASK (0x1 << 2)
#define RT5668_PWR_JD2_SHIFT 2
#define RT5668_PWR_RECMIX1 (0x1 << 1)
#define RT5668_PWR_RECMIX1_SHIFT 1
#define RT5668_PWR_RECMIX2 (0x1)
#define RT5668_PWR_RECMIX2_SHIFT 0
#define RT5663_PWR_BST1 (0x1 << 15)
#define RT5663_PWR_BST1_MASK (0x1 << 15)
#define RT5663_PWR_BST1_SHIFT 15
#define RT5663_PWR_BST1_OFF (0x0 << 15)
#define RT5663_PWR_BST1_ON (0x1 << 15)
#define RT5663_PWR_BST2 (0x1 << 14)
#define RT5663_PWR_BST2_MASK (0x1 << 14)
#define RT5663_PWR_BST2_SHIFT 14
#define RT5663_PWR_MB1 (0x1 << 11)
#define RT5663_PWR_MB1_SHIFT 11
#define RT5663_PWR_MB2 (0x1 << 10)
#define RT5663_PWR_MB2_SHIFT 10
#define RT5663_PWR_BST2_OP (0x1 << 6)
#define RT5663_PWR_BST2_OP_MASK (0x1 << 6)
#define RT5663_PWR_BST2_OP_SHIFT 6
#define RT5663_PWR_JD1 (0x1 << 3)
#define RT5663_PWR_JD1_MASK (0x1 << 3)
#define RT5663_PWR_JD1_SHIFT 3
#define RT5663_PWR_JD2 (0x1 << 2)
#define RT5663_PWR_JD2_MASK (0x1 << 2)
#define RT5663_PWR_JD2_SHIFT 2
#define RT5663_PWR_RECMIX1 (0x1 << 1)
#define RT5663_PWR_RECMIX1_SHIFT 1
#define RT5663_PWR_RECMIX2 (0x1)
#define RT5663_PWR_RECMIX2_SHIFT 0
/* Power Management for Analog 3 (0x0065) */
#define RT5668_PWR_CBJ_MASK (0x1 << 9)
#define RT5668_PWR_CBJ_SHIFT 9
#define RT5668_PWR_CBJ_OFF (0x0 << 9)
#define RT5668_PWR_CBJ_ON (0x1 << 9)
#define RT5668_PWR_PLL (0x1 << 6)
#define RT5668_PWR_PLL_SHIFT 6
#define RT5668_PWR_LDO2 (0x1 << 2)
#define RT5668_PWR_LDO2_SHIFT 2
#define RT5663_PWR_CBJ_MASK (0x1 << 9)
#define RT5663_PWR_CBJ_SHIFT 9
#define RT5663_PWR_CBJ_OFF (0x0 << 9)
#define RT5663_PWR_CBJ_ON (0x1 << 9)
#define RT5663_PWR_PLL (0x1 << 6)
#define RT5663_PWR_PLL_SHIFT 6
#define RT5663_PWR_LDO2 (0x1 << 2)
#define RT5663_PWR_LDO2_SHIFT 2
/* Power Management for Volume (0x0067) */
#define RT5668_PWR_MIC_DET (0x1 << 5)
#define RT5668_PWR_MIC_DET_SHIFT 5
#define RT5663_V2_PWR_MIC_DET (0x1 << 5)
#define RT5663_V2_PWR_MIC_DET_SHIFT 5
/* MCLK and System Clock Detection Control (0x006b) */
#define RT5668_EN_ANA_CLK_DET_MASK (0x1 << 15)
#define RT5668_EN_ANA_CLK_DET_SHIFT 15
#define RT5668_EN_ANA_CLK_DET_DIS (0x0 << 15)
#define RT5668_EN_ANA_CLK_DET_AUTO (0x1 << 15)
#define RT5668_PWR_CLK_DET_MASK (0x1)
#define RT5668_PWR_CLK_DET_SHIFT 0
#define RT5668_PWR_CLK_DET_DIS (0x0)
#define RT5668_PWR_CLK_DET_EN (0x1)
#define RT5663_EN_ANA_CLK_DET_MASK (0x1 << 15)
#define RT5663_EN_ANA_CLK_DET_SHIFT 15
#define RT5663_EN_ANA_CLK_DET_DIS (0x0 << 15)
#define RT5663_EN_ANA_CLK_DET_AUTO (0x1 << 15)
#define RT5663_PWR_CLK_DET_MASK (0x1)
#define RT5663_PWR_CLK_DET_SHIFT 0
#define RT5663_PWR_CLK_DET_DIS (0x0)
#define RT5663_PWR_CLK_DET_EN (0x1)
/* I2S1 Audio Serial Data Port Control (0x0070) */
#define RT5668_I2S_MS_MASK (0x1 << 15)
#define RT5668_I2S_MS_SHIFT 15
#define RT5668_I2S_MS_M (0x0 << 15)
#define RT5668_I2S_MS_S (0x1 << 15)
#define RT5668_I2S_BP_MASK (0x1 << 8)
#define RT5668_I2S_BP_SHIFT 8
#define RT5668_I2S_BP_NOR (0x0 << 8)
#define RT5668_I2S_BP_INV (0x1 << 8)
#define RT5668_I2S_DL_MASK (0x3 << 4)
#define RT5668_I2S_DL_SHIFT 4
#define RT5668_I2S_DL_16 (0x0 << 4)
#define RT5668_I2S_DL_20 (0x1 << 4)
#define RT5668_I2S_DL_24 (0x2 << 4)
#define RT5668_I2S_DL_8 (0x3 << 4)
#define RT5668_I2S_DF_MASK (0x7)
#define RT5668_I2S_DF_SHIFT 0
#define RT5668_I2S_DF_I2S (0x0)
#define RT5668_I2S_DF_LEFT (0x1)
#define RT5668_I2S_DF_PCM_A (0x2)
#define RT5668_I2S_DF_PCM_B (0x3)
#define RT5668_I2S_DF_PCM_A_N (0x6)
#define RT5668_I2S_DF_PCM_B_N (0x7)
#define RT5663_I2S_MS_MASK (0x1 << 15)
#define RT5663_I2S_MS_SHIFT 15
#define RT5663_I2S_MS_M (0x0 << 15)
#define RT5663_I2S_MS_S (0x1 << 15)
#define RT5663_I2S_BP_MASK (0x1 << 8)
#define RT5663_I2S_BP_SHIFT 8
#define RT5663_I2S_BP_NOR (0x0 << 8)
#define RT5663_I2S_BP_INV (0x1 << 8)
#define RT5663_I2S_DL_MASK (0x3 << 4)
#define RT5663_I2S_DL_SHIFT 4
#define RT5663_I2S_DL_16 (0x0 << 4)
#define RT5663_I2S_DL_20 (0x1 << 4)
#define RT5663_I2S_DL_24 (0x2 << 4)
#define RT5663_I2S_DL_8 (0x3 << 4)
#define RT5663_I2S_DF_MASK (0x7)
#define RT5663_I2S_DF_SHIFT 0
#define RT5663_I2S_DF_I2S (0x0)
#define RT5663_I2S_DF_LEFT (0x1)
#define RT5663_I2S_DF_PCM_A (0x2)
#define RT5663_I2S_DF_PCM_B (0x3)
#define RT5663_I2S_DF_PCM_A_N (0x6)
#define RT5663_I2S_DF_PCM_B_N (0x7)
/* ADC/DAC Clock Control 1 (0x0073) */
#define RT5668_I2S_PD1_MASK (0x7 << 12)
#define RT5668_I2S_PD1_SHIFT 12
#define RT5668_M_I2S_DIV_MASK (0x7 << 8)
#define RT5668_M_I2S_DIV_SHIFT 8
#define RT5668_CLK_SRC_MASK (0x3 << 4)
#define RT5668_CLK_SRC_MCLK (0x0 << 4)
#define RT5668_CLK_SRC_PLL_OUT (0x1 << 4)
#define RT5668_CLK_SRC_DIV (0x2 << 4)
#define RT5668_CLK_SRC_RC (0x3 << 4)
#define RT5668_DAC_OSR_MASK (0x3 << 2)
#define RT5668_DAC_OSR_SHIFT 2
#define RT5668_DAC_OSR_128 (0x0 << 2)
#define RT5668_DAC_OSR_64 (0x1 << 2)
#define RT5668_DAC_OSR_32 (0x2 << 2)
#define RT5668_ADC_OSR_MASK (0x3)
#define RT5668_ADC_OSR_SHIFT 0
#define RT5668_ADC_OSR_128 (0x0)
#define RT5668_ADC_OSR_64 (0x1)
#define RT5668_ADC_OSR_32 (0x2)
#define RT5663_I2S_PD1_MASK (0x7 << 12)
#define RT5663_I2S_PD1_SHIFT 12
#define RT5663_M_I2S_DIV_MASK (0x7 << 8)
#define RT5663_M_I2S_DIV_SHIFT 8
#define RT5663_CLK_SRC_MASK (0x3 << 4)
#define RT5663_CLK_SRC_MCLK (0x0 << 4)
#define RT5663_CLK_SRC_PLL_OUT (0x1 << 4)
#define RT5663_CLK_SRC_DIV (0x2 << 4)
#define RT5663_CLK_SRC_RC (0x3 << 4)
#define RT5663_DAC_OSR_MASK (0x3 << 2)
#define RT5663_DAC_OSR_SHIFT 2
#define RT5663_DAC_OSR_128 (0x0 << 2)
#define RT5663_DAC_OSR_64 (0x1 << 2)
#define RT5663_DAC_OSR_32 (0x2 << 2)
#define RT5663_ADC_OSR_MASK (0x3)
#define RT5663_ADC_OSR_SHIFT 0
#define RT5663_ADC_OSR_128 (0x0)
#define RT5663_ADC_OSR_64 (0x1)
#define RT5663_ADC_OSR_32 (0x2)
/* TDM1 control 1 (0x0078) */
#define RT5668_TDM_MODE_MASK (0x1 << 15)
#define RT5668_TDM_MODE_SHIFT 15
#define RT5668_TDM_MODE_I2S (0x0 << 15)
#define RT5668_TDM_MODE_TDM (0x1 << 15)
#define RT5668_TDM_IN_CH_MASK (0x3 << 10)
#define RT5668_TDM_IN_CH_SHIFT 10
#define RT5668_TDM_IN_CH_2 (0x0 << 10)
#define RT5668_TDM_IN_CH_4 (0x1 << 10)
#define RT5668_TDM_IN_CH_6 (0x2 << 10)
#define RT5668_TDM_IN_CH_8 (0x3 << 10)
#define RT5668_TDM_OUT_CH_MASK (0x3 << 8)
#define RT5668_TDM_OUT_CH_SHIFT 8
#define RT5668_TDM_OUT_CH_2 (0x0 << 8)
#define RT5668_TDM_OUT_CH_4 (0x1 << 8)
#define RT5668_TDM_OUT_CH_6 (0x2 << 8)
#define RT5668_TDM_OUT_CH_8 (0x3 << 8)
#define RT5668_TDM_IN_LEN_MASK (0x3 << 6)
#define RT5668_TDM_IN_LEN_SHIFT 6
#define RT5668_TDM_IN_LEN_16 (0x0 << 6)
#define RT5668_TDM_IN_LEN_20 (0x1 << 6)
#define RT5668_TDM_IN_LEN_24 (0x2 << 6)
#define RT5668_TDM_IN_LEN_32 (0x3 << 6)
#define RT5668_TDM_OUT_LEN_MASK (0x3 << 4)
#define RT5668_TDM_OUT_LEN_SHIFT 4
#define RT5668_TDM_OUT_LEN_16 (0x0 << 4)
#define RT5668_TDM_OUT_LEN_20 (0x1 << 4)
#define RT5668_TDM_OUT_LEN_24 (0x2 << 4)
#define RT5668_TDM_OUT_LEN_32 (0x3 << 4)
#define RT5663_TDM_MODE_MASK (0x1 << 15)
#define RT5663_TDM_MODE_SHIFT 15
#define RT5663_TDM_MODE_I2S (0x0 << 15)
#define RT5663_TDM_MODE_TDM (0x1 << 15)
#define RT5663_TDM_IN_CH_MASK (0x3 << 10)
#define RT5663_TDM_IN_CH_SHIFT 10
#define RT5663_TDM_IN_CH_2 (0x0 << 10)
#define RT5663_TDM_IN_CH_4 (0x1 << 10)
#define RT5663_TDM_IN_CH_6 (0x2 << 10)
#define RT5663_TDM_IN_CH_8 (0x3 << 10)
#define RT5663_TDM_OUT_CH_MASK (0x3 << 8)
#define RT5663_TDM_OUT_CH_SHIFT 8
#define RT5663_TDM_OUT_CH_2 (0x0 << 8)
#define RT5663_TDM_OUT_CH_4 (0x1 << 8)
#define RT5663_TDM_OUT_CH_6 (0x2 << 8)
#define RT5663_TDM_OUT_CH_8 (0x3 << 8)
#define RT5663_TDM_IN_LEN_MASK (0x3 << 6)
#define RT5663_TDM_IN_LEN_SHIFT 6
#define RT5663_TDM_IN_LEN_16 (0x0 << 6)
#define RT5663_TDM_IN_LEN_20 (0x1 << 6)
#define RT5663_TDM_IN_LEN_24 (0x2 << 6)
#define RT5663_TDM_IN_LEN_32 (0x3 << 6)
#define RT5663_TDM_OUT_LEN_MASK (0x3 << 4)
#define RT5663_TDM_OUT_LEN_SHIFT 4
#define RT5663_TDM_OUT_LEN_16 (0x0 << 4)
#define RT5663_TDM_OUT_LEN_20 (0x1 << 4)
#define RT5663_TDM_OUT_LEN_24 (0x2 << 4)
#define RT5663_TDM_OUT_LEN_32 (0x3 << 4)
/* Global Clock Control (0x0080) */
#define RT5668_SCLK_SRC_MASK (0x3 << 14)
#define RT5668_SCLK_SRC_SHIFT 14
#define RT5668_SCLK_SRC_MCLK (0x0 << 14)
#define RT5668_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5668_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5668_PLL1_SRC_MASK (0x7 << 8)
#define RT5668_PLL1_SRC_SHIFT 8
#define RT5668_PLL1_SRC_MCLK (0x0 << 8)
#define RT5668_PLL1_SRC_BCLK1 (0x1 << 8)
#define RT5668_PLL1_PD_MASK (0x1 << 4)
#define RT5668_PLL1_PD_SHIFT 4
#define RT5668_PLL_INP_MAX 40000000
#define RT5668_PLL_INP_MIN 256000
#define RT5663_SCLK_SRC_MASK (0x3 << 14)
#define RT5663_SCLK_SRC_SHIFT 14
#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5663_PLL1_SRC_MASK (0x7 << 11)
#define RT5663_PLL1_SRC_SHIFT 11
#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
#define RT5663_V2_PLL1_SRC_MASK (0x7 << 8)
#define RT5663_V2_PLL1_SRC_SHIFT 8
#define RT5663_V2_PLL1_SRC_MCLK (0x0 << 8)
#define RT5663_V2_PLL1_SRC_BCLK1 (0x1 << 8)
#define RT5663_PLL1_PD_MASK (0x1 << 4)
#define RT5663_PLL1_PD_SHIFT 4
#define RT5663_PLL_INP_MAX 40000000
#define RT5663_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x0081) */
#define RT5668_PLL_N_MAX 0x001ff
#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)
#define RT5668_PLL_N_SHIFT 7
#define RT5668_PLL_K_MAX 0x001f
#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)
#define RT5668_PLL_K_SHIFT 0
#define RT5663_PLL_N_MAX 0x001ff
#define RT5663_PLL_N_MASK (RT5663_PLL_N_MAX << 7)
#define RT5663_PLL_N_SHIFT 7
#define RT5663_PLL_K_MAX 0x001f
#define RT5663_PLL_K_MASK (RT5663_PLL_K_MAX)
#define RT5663_PLL_K_SHIFT 0
/* PLL M/N/K Code Control 2 (0x0082) */
#define RT5668_PLL_M_MAX 0x00f
#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
#define RT5668_PLL_M_SHIFT 12
#define RT5668_PLL_M_BP (0x1 << 11)
#define RT5668_PLL_M_BP_SHIFT 11
#define RT5663_PLL_M_MAX 0x00f
#define RT5663_PLL_M_MASK (RT5663_PLL_M_MAX << 12)
#define RT5663_PLL_M_SHIFT 12
#define RT5663_PLL_M_BP (0x1 << 11)
#define RT5663_PLL_M_BP_SHIFT 11
/* PLL tracking mode 1 (0x0083) */
#define RT5668_I2S1_ASRC_MASK (0x1 << 13)
#define RT5668_I2S1_ASRC_SHIFT 13
#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
#define RT5668_DAC_STO1_ASRC_SHIFT 12
#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 4)
#define RT5668_ADC_STO1_ASRC_SHIFT 4
#define RT5663_V2_I2S1_ASRC_MASK (0x1 << 13)
#define RT5663_V2_I2S1_ASRC_SHIFT 13
#define RT5663_V2_DAC_STO1_ASRC_MASK (0x1 << 12)
#define RT5663_V2_DAC_STO1_ASRC_SHIFT 12
#define RT5663_V2_ADC_STO1_ASRC_MASK (0x1 << 4)
#define RT5663_V2_ADC_STO1_ASRC_SHIFT 4
/* PLL tracking mode 2 (0x0084)*/
#define RT5668_DA_STO1_TRACK_MASK (0x7 << 12)
#define RT5668_DA_STO1_TRACK_SHIFT 12
#define RT5668_DA_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5668_DA_STO1_TRACK_I2S1 (0x1 << 12)
#define RT5663_DA_STO1_TRACK_MASK (0x7 << 12)
#define RT5663_DA_STO1_TRACK_SHIFT 12
#define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12)
/* PLL tracking mode 3 (0x0085)*/
#define RT5668_AD_STO1_TRACK_MASK (0x7 << 12)
#define RT5668_AD_STO1_TRACK_SHIFT 12
#define RT5668_AD_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5668_AD_STO1_TRACK_I2S1 (0x1 << 12)
#define RT5663_V2_AD_STO1_TRACK_MASK (0x7 << 12)
#define RT5663_V2_AD_STO1_TRACK_SHIFT 12
#define RT5663_V2_AD_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5663_V2_AD_STO1_TRACK_I2S1 (0x1 << 12)
/* HPOUT Charge pump control 1 (0x0091) */
#define RT5668_OSW_HP_L_MASK (0x1 << 11)
#define RT5668_OSW_HP_L_SHIFT 11
#define RT5668_OSW_HP_L_EN (0x1 << 11)
#define RT5668_OSW_HP_L_DIS (0x0 << 11)
#define RT5668_OSW_HP_R_MASK (0x1 << 10)
#define RT5668_OSW_HP_R_SHIFT 10
#define RT5668_OSW_HP_R_EN (0x1 << 10)
#define RT5668_OSW_HP_R_DIS (0x0 << 10)
#define RT5668_SEL_PM_HP_MASK (0x3 << 8)
#define RT5668_SEL_PM_HP_SHIFT 8
#define RT5668_SEL_PM_HP_0_6 (0x0 << 8)
#define RT5668_SEL_PM_HP_0_9 (0x1 << 8)
#define RT5668_SEL_PM_HP_1_8 (0x2 << 8)
#define RT5668_SEL_PM_HP_HIGH (0x3 << 8)
#define RT5668_OVCD_HP_MASK (0x1 << 2)
#define RT5668_OVCD_HP_SHIFT 2
#define RT5668_OVCD_HP_EN (0x1 << 2)
#define RT5668_OVCD_HP_DIS (0x0 << 2)
#define RT5663_OSW_HP_L_MASK (0x1 << 11)
#define RT5663_OSW_HP_L_SHIFT 11
#define RT5663_OSW_HP_L_EN (0x1 << 11)
#define RT5663_OSW_HP_L_DIS (0x0 << 11)
#define RT5663_OSW_HP_R_MASK (0x1 << 10)
#define RT5663_OSW_HP_R_SHIFT 10
#define RT5663_OSW_HP_R_EN (0x1 << 10)
#define RT5663_OSW_HP_R_DIS (0x0 << 10)
#define RT5663_SEL_PM_HP_MASK (0x3 << 8)
#define RT5663_SEL_PM_HP_SHIFT 8
#define RT5663_SEL_PM_HP_0_6 (0x0 << 8)
#define RT5663_SEL_PM_HP_0_9 (0x1 << 8)
#define RT5663_SEL_PM_HP_1_8 (0x2 << 8)
#define RT5663_SEL_PM_HP_HIGH (0x3 << 8)
#define RT5663_OVCD_HP_MASK (0x1 << 2)
#define RT5663_OVCD_HP_SHIFT 2
#define RT5663_OVCD_HP_EN (0x1 << 2)
#define RT5663_OVCD_HP_DIS (0x0 << 2)
/* RC Clock Control (0x0094) */
#define RT5668_DIG_25M_CLK_MASK (0x1 << 9)
#define RT5668_DIG_25M_CLK_SHIFT 9
#define RT5668_DIG_25M_CLK_DIS (0x0 << 9)
#define RT5668_DIG_25M_CLK_EN (0x1 << 9)
#define RT5668_DIG_1M_CLK_MASK (0x1 << 8)
#define RT5668_DIG_1M_CLK_SHIFT 8
#define RT5668_DIG_1M_CLK_DIS (0x0 << 8)
#define RT5668_DIG_1M_CLK_EN (0x1 << 8)
#define RT5663_DIG_25M_CLK_MASK (0x1 << 9)
#define RT5663_DIG_25M_CLK_SHIFT 9
#define RT5663_DIG_25M_CLK_DIS (0x0 << 9)
#define RT5663_DIG_25M_CLK_EN (0x1 << 9)
#define RT5663_DIG_1M_CLK_MASK (0x1 << 8)
#define RT5663_DIG_1M_CLK_SHIFT 8
#define RT5663_DIG_1M_CLK_DIS (0x0 << 8)
#define RT5663_DIG_1M_CLK_EN (0x1 << 8)
/* Auto Turn On 1M RC CLK (0x009f) */
#define RT5668_IRQ_POW_SAV_MASK (0x1 << 15)
#define RT5668_IRQ_POW_SAV_SHIFT 15
#define RT5668_IRQ_POW_SAV_DIS (0x0 << 15)
#define RT5668_IRQ_POW_SAV_EN (0x1 << 15)
#define RT5668_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
#define RT5668_IRQ_POW_SAV_JD1_SHIFT 14
#define RT5668_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
#define RT5668_IRQ_POW_SAV_JD1_EN (0x1 << 14)
#define RT5663_IRQ_POW_SAV_MASK (0x1 << 15)
#define RT5663_IRQ_POW_SAV_SHIFT 15
#define RT5663_IRQ_POW_SAV_DIS (0x0 << 15)
#define RT5663_IRQ_POW_SAV_EN (0x1 << 15)
#define RT5663_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
#define RT5663_IRQ_POW_SAV_JD1_SHIFT 14
#define RT5663_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
#define RT5663_IRQ_POW_SAV_JD1_EN (0x1 << 14)
/* IRQ Control 1 (0x00b6) */
#define RT5668_EN_CB_JD_MASK (0x1 << 3)
#define RT5668_EN_CB_JD_SHIFT 3
#define RT5668_EN_CB_JD_EN (0x1 << 3)
#define RT5668_EN_CB_JD_DIS (0x0 << 3)
#define RT5663_EN_CB_JD_MASK (0x1 << 3)
#define RT5663_EN_CB_JD_SHIFT 3
#define RT5663_EN_CB_JD_EN (0x1 << 3)
#define RT5663_EN_CB_JD_DIS (0x0 << 3)
/* IRQ Control 3 (0x00b8) */
#define RT5668_EN_IRQ_INLINE_MASK (0x1 << 6)
#define RT5668_EN_IRQ_INLINE_SHIFT 6
#define RT5668_EN_IRQ_INLINE_BYP (0x0 << 6)
#define RT5668_EN_IRQ_INLINE_NOR (0x1 << 6)
#define RT5663_V2_EN_IRQ_INLINE_MASK (0x1 << 6)
#define RT5663_V2_EN_IRQ_INLINE_SHIFT 6
#define RT5663_V2_EN_IRQ_INLINE_BYP (0x0 << 6)
#define RT5663_V2_EN_IRQ_INLINE_NOR (0x1 << 6)
/* GPIO Control 1 (0x00c0) */
#define RT5668_GP1_PIN_MASK (0x1 << 15)
#define RT5668_GP1_PIN_SHIFT 15
#define RT5668_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5668_GP1_PIN_IRQ (0x1 << 15)
#define RT5663_GP1_PIN_MASK (0x1 << 15)
#define RT5663_GP1_PIN_SHIFT 15
#define RT5663_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5663_GP1_PIN_IRQ (0x1 << 15)
/* GPIO Control 2 (0x00c1) */
#define RT5668_GP4_PIN_CONF_MASK (0x1 << 5)
#define RT5668_GP4_PIN_CONF_SHIFT 5
#define RT5668_GP4_PIN_CONF_INPUT (0x0 << 5)
#define RT5668_GP4_PIN_CONF_OUTPUT (0x1 << 5)
#define RT5663_GP4_PIN_CONF_MASK (0x1 << 5)
#define RT5663_GP4_PIN_CONF_SHIFT 5
#define RT5663_GP4_PIN_CONF_INPUT (0x0 << 5)
#define RT5663_GP4_PIN_CONF_OUTPUT (0x1 << 5)
/* GPIO Control 2 (0x00c2) */
#define RT5668_GP8_PIN_CONF_MASK (0x1 << 13)
#define RT5668_GP8_PIN_CONF_SHIFT 13
#define RT5668_GP8_PIN_CONF_INPUT (0x0 << 13)
#define RT5668_GP8_PIN_CONF_OUTPUT (0x1 << 13)
#define RT5663_GP8_PIN_CONF_MASK (0x1 << 13)
#define RT5663_GP8_PIN_CONF_SHIFT 13
#define RT5663_GP8_PIN_CONF_INPUT (0x0 << 13)
#define RT5663_GP8_PIN_CONF_OUTPUT (0x1 << 13)
/* 4 Buttons Inline Command Function 1 (0x00df) */
#define RT5668_4BTN_CLK_DEB_MASK (0x3 << 2)
#define RT5668_4BTN_CLK_DEB_SHIFT 2
#define RT5668_4BTN_CLK_DEB_8MS (0x0 << 2)
#define RT5668_4BTN_CLK_DEB_16MS (0x1 << 2)
#define RT5668_4BTN_CLK_DEB_32MS (0x2 << 2)
#define RT5668_4BTN_CLK_DEB_65MS (0x3 << 2)
#define RT5663_4BTN_CLK_DEB_MASK (0x3 << 2)
#define RT5663_4BTN_CLK_DEB_SHIFT 2
#define RT5663_4BTN_CLK_DEB_8MS (0x0 << 2)
#define RT5663_4BTN_CLK_DEB_16MS (0x1 << 2)
#define RT5663_4BTN_CLK_DEB_32MS (0x2 << 2)
#define RT5663_4BTN_CLK_DEB_65MS (0x3 << 2)
/* Inline Command Function 6 (0x00e0) */
#define RT5668_EN_4BTN_INL_MASK (0x1 << 15)
#define RT5668_EN_4BTN_INL_SHIFT 15
#define RT5668_EN_4BTN_INL_DIS (0x0 << 15)
#define RT5668_EN_4BTN_INL_EN (0x1 << 15)
#define RT5668_RESET_4BTN_INL_MASK (0x1 << 14)
#define RT5668_RESET_4BTN_INL_SHIFT 14
#define RT5668_RESET_4BTN_INL_RESET (0x0 << 14)
#define RT5668_RESET_4BTN_INL_NOR (0x1 << 14)
#define RT5663_EN_4BTN_INL_MASK (0x1 << 15)
#define RT5663_EN_4BTN_INL_SHIFT 15
#define RT5663_EN_4BTN_INL_DIS (0x0 << 15)
#define RT5663_EN_4BTN_INL_EN (0x1 << 15)
#define RT5663_RESET_4BTN_INL_MASK (0x1 << 14)
#define RT5663_RESET_4BTN_INL_SHIFT 14
#define RT5663_RESET_4BTN_INL_RESET (0x0 << 14)
#define RT5663_RESET_4BTN_INL_NOR (0x1 << 14)
/* Digital Misc Control (0x00fa) */
#define RT5668_DIG_GATE_CTRL_MASK 0x1
#define RT5668_DIG_GATE_CTRL_SHIFT (0)
#define RT5668_DIG_GATE_CTRL_DIS 0x0
#define RT5668_DIG_GATE_CTRL_EN 0x1
#define RT5663_DIG_GATE_CTRL_MASK 0x1
#define RT5663_DIG_GATE_CTRL_SHIFT (0)
#define RT5663_DIG_GATE_CTRL_DIS 0x0
#define RT5663_DIG_GATE_CTRL_EN 0x1
/* Chopper and Clock control for DAC L (0x013a)*/
#define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
#define RT5668_CKXEN_DAC1_SHIFT 13
#define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
#define RT5668_CKGEN_DAC1_SHIFT 12
#define RT5663_CKXEN_DAC1_MASK (0x1 << 13)
#define RT5663_CKXEN_DAC1_SHIFT 13
#define RT5663_CKGEN_DAC1_MASK (0x1 << 12)
#define RT5663_CKGEN_DAC1_SHIFT 12
/* Chopper and Clock control for ADC (0x013b)*/
#define RT5668_CKXEN_ADCC_MASK (0x1 << 13)
#define RT5668_CKXEN_ADCC_SHIFT 13
#define RT5668_CKGEN_ADCC_MASK (0x1 << 12)
#define RT5668_CKGEN_ADCC_SHIFT 12
#define RT5663_CKXEN_ADCC_MASK (0x1 << 13)
#define RT5663_CKXEN_ADCC_SHIFT 13
#define RT5663_CKGEN_ADCC_MASK (0x1 << 12)
#define RT5663_CKGEN_ADCC_SHIFT 12
/* HP Behavior Logic Control 2 (0x01db) */
#define RT5668_HP_SIG_SRC1_MASK (0x3)
#define RT5668_HP_SIG_SRC1_SHIFT 0
#define RT5668_HP_SIG_SRC1_HP_DC (0x0)
#define RT5668_HP_SIG_SRC1_HP_CALIB (0x1)
#define RT5668_HP_SIG_SRC1_REG (0x2)
#define RT5668_HP_SIG_SRC1_SILENCE (0x3)
#define RT5663_HP_SIG_SRC1_MASK (0x3)
#define RT5663_HP_SIG_SRC1_SHIFT 0
#define RT5663_HP_SIG_SRC1_HP_DC (0x0)
#define RT5663_HP_SIG_SRC1_HP_CALIB (0x1)
#define RT5663_HP_SIG_SRC1_REG (0x2)
#define RT5663_HP_SIG_SRC1_SILENCE (0x3)
/* RT5663 specific register */
#define RT5663_HP_OUT_EN 0x0002
......@@ -707,6 +704,10 @@
#define RT5663_TDM_3 0x0079
#define RT5663_TDM_4 0x007a
#define RT5663_TDM_5 0x007b
#define RT5663_TDM_6 0x007c
#define RT5663_TDM_7 0x007d
#define RT5663_TDM_8 0x007e
#define RT5663_TDM_9 0x007f
#define RT5663_GLB_CLK 0x0080
#define RT5663_PLL_1 0x0081
#define RT5663_PLL_2 0x0082
......@@ -739,7 +740,7 @@
#define RT5663_INT_ST_2 0x00bf
#define RT5663_GPIO_1 0x00c0
#define RT5663_GPIO_2 0x00c1
#define RT5663_GPIO_STA 0x00c5
#define RT5663_GPIO_STA1 0x00c5
#define RT5663_SIN_GEN_1 0x00cb
#define RT5663_SIN_GEN_2 0x00cc
#define RT5663_SIN_GEN_3 0x00cd
......@@ -800,6 +801,8 @@
#define RT5663_TEST_MODE_1 0x0144
#define RT5663_TEST_MODE_2 0x0145
#define RT5663_TEST_MODE_3 0x0146
#define RT5663_TEST_MODE_4 0x0147
#define RT5663_TEST_MODE_5 0x0148
#define RT5663_STO_DRE_1 0x0160
#define RT5663_STO_DRE_2 0x0161
#define RT5663_STO_DRE_3 0x0162
......@@ -921,19 +924,19 @@
#define RT5663_ADC_EQ_POST_VOL_L 0x03f2
#define RT5663_ADC_EQ_POST_VOL_R 0x03f3
/* RT5663: RECMIX Control (0x0010) */
/* RECMIX Control (0x0010) */
#define RT5663_RECMIX1_BST1_MASK (0x1)
#define RT5663_RECMIX1_BST1_SHIFT 0
#define RT5663_RECMIX1_BST1_ON (0x0)
#define RT5663_RECMIX1_BST1_OFF (0x1)
/* RT5663: Bypass Stereo1 DAC Mixer Control (0x002d) */
/* Bypass Stereo1 DAC Mixer Control (0x002d) */
#define RT5663_DACL1_SRC_MASK (0x1 << 3)
#define RT5663_DACL1_SRC_SHIFT 3
#define RT5663_DACR1_SRC_MASK (0x1 << 2)
#define RT5663_DACR1_SRC_SHIFT 2
/* RT5663: TDM control 2 (0x0078) */
/* TDM control 2 (0x0078) */
#define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14)
#define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14
#define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14)
......@@ -941,7 +944,7 @@
#define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14)
#define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14)
/* RT5663: TDM control 5 (0x007b) */
/* TDM control 5 (0x007b) */
#define RT5663_TDM_LENGTN_MASK (0x3)
#define RT5663_TDM_LENGTN_SHIFT 0
#define RT5663_TDM_LENGTN_16 (0x0)
......@@ -949,17 +952,6 @@
#define RT5663_TDM_LENGTN_24 (0x2)
#define RT5663_TDM_LENGTN_32 (0x3)
/* RT5663: Global Clock Control (0x0080) */
#define RT5663_SCLK_SRC_MASK (0x3 << 14)
#define RT5663_SCLK_SRC_SHIFT 14
#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5663_PLL1_SRC_MASK (0x7 << 11)
#define RT5663_PLL1_SRC_SHIFT 11
#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
/* PLL tracking mode 1 (0x0083) */
#define RT5663_I2S1_ASRC_MASK (0x1 << 11)
#define RT5663_I2S1_ASRC_SHIFT 11
......@@ -978,37 +970,47 @@
#define RT5663_AD_STO1_TRACK_SYSCLK (0x0)
#define RT5663_AD_STO1_TRACK_I2S1 (0x1)
/* RT5663: HPOUT Charge pump control 1 (0x0091) */
/* HPOUT Charge pump control 1 (0x0091) */
#define RT5663_SI_HP_MASK (0x1 << 12)
#define RT5663_SI_HP_SHIFT 12
#define RT5663_SI_HP_EN (0x1 << 12)
#define RT5663_SI_HP_DIS (0x0 << 12)
/* RT5663: GPIO Control 2 (0x00b6) */
/* GPIO Control 2 (0x00b6) */
#define RT5663_GP1_PIN_CONF_MASK (0x1 << 2)
#define RT5663_GP1_PIN_CONF_SHIFT 2
#define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2)
#define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2)
/* RT5663: GPIO Control 2 (0x00b7) */
/* GPIO Control 2 (0x00b7) */
#define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3)
#define RT5663_EN_IRQ_INLINE_SHIFT 3
#define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3)
#define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3)
/* RT5663: IRQ Control 1 (0x00c1) */
/* GPIO Control 1 (0x00c0) */
#define RT5663_GPIO1_TYPE_MASK (0x1 << 15)
#define RT5663_GPIO1_TYPE_SHIFT 15
#define RT5663_GPIO1_TYPE_EN (0x1 << 15)
#define RT5663_GPIO1_TYPE_DIS (0x0 << 15)
/* IRQ Control 1 (0x00c1) */
#define RT5663_EN_IRQ_JD1_MASK (0x1 << 6)
#define RT5663_EN_IRQ_JD1_SHIFT 6
#define RT5663_EN_IRQ_JD1_EN (0x1 << 6)
#define RT5663_EN_IRQ_JD1_DIS (0x0 << 6)
#define RT5663_SEL_GPIO1_MASK (0x1 << 2)
#define RT5663_SEL_GPIO1_SHIFT 6
#define RT5663_SEL_GPIO1_EN (0x1 << 2)
#define RT5663_SEL_GPIO1_DIS (0x0 << 2)
/* RT5663: Inline Command Function 2 (0x00dc) */
/* Inline Command Function 2 (0x00dc) */
#define RT5663_PWR_MIC_DET_MASK (0x1)
#define RT5663_PWR_MIC_DET_SHIFT 0
#define RT5663_PWR_MIC_DET_ON (0x1)
#define RT5663_PWR_MIC_DET_OFF (0x0)
/* RT5663: Embeeded Jack and Type Detection Control 1 (0x00e6)*/
/* Embeeded Jack and Type Detection Control 1 (0x00e6)*/
#define RT5663_CBJ_DET_MASK (0x1 << 15)
#define RT5663_CBJ_DET_SHIFT 15
#define RT5663_CBJ_DET_DIS (0x0 << 15)
......@@ -1022,17 +1024,17 @@
#define RT5663_POL_EXT_JD_EN (0x1 << 10)
#define RT5663_POL_EXT_JD_DIS (0x0 << 10)
/* RT5663: DACREF LDO Control (0x0112)*/
/* DACREF LDO Control (0x0112)*/
#define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9)
#define RT5663_PWR_LDO_DACREFL_SHIFT 9
#define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1)
#define RT5663_PWR_LDO_DACREFR_SHIFT 1
/* RT5663: Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
/* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
#define RT5663_DRE_GAIN_HP_MASK (0x1f)
#define RT5663_DRE_GAIN_HP_SHIFT 0
/* RT5663: Combo Jack Control (0x0250) */
/* Combo Jack Control (0x0250) */
#define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11)
#define RT5663_INBUF_CBJ_BST1_SHIFT 11
#define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11)
......@@ -1042,11 +1044,11 @@
#define RT5663_CBJ_SENSE_BST1_L (0x1 << 10)
#define RT5663_CBJ_SENSE_BST1_R (0x0 << 10)
/* RT5663: Combo Jack Control (0x0251) */
/* Combo Jack Control (0x0251) */
#define RT5663_GAIN_BST1_MASK (0xf)
#define RT5663_GAIN_BST1_SHIFT 0
/* RT5663: Dummy register 1 (0x02fa) */
/* Dummy register 1 (0x02fa) */
#define RT5663_EMB_CLK_MASK (0x1 << 9)
#define RT5663_EMB_CLK_SHIFT 9
#define RT5663_EMB_CLK_EN (0x1 << 9)
......
sound/soc/codecs/rt5665.c 0 → 100644
View file @ b35ddfd4
This source diff could not be displayed because it is too large. You can view the blob instead.
sound/soc/codecs/rt5665.h 0 → 100644
View file @ b35ddfd4
/*
* rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
*
* Copyright 2016 Realtek Microelectronics
* Author: Bard Liao <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5665_H__
#define __RT5665_H__
#include <sound/rt5665.h>
#define DEVICE_ID 0x6451
/* Info */
#define RT5665_RESET 0x0000
#define RT5665_VENDOR_ID 0x00fd
#define RT5665_VENDOR_ID_1 0x00fe
#define RT5665_DEVICE_ID 0x00ff
/* I/O - Output */
#define RT5665_LOUT 0x0001
#define RT5665_HP_CTRL_1 0x0002
#define RT5665_HP_CTRL_2 0x0003
#define RT5665_MONO_OUT 0x0004
#define RT5665_HPL_GAIN 0x0005
#define RT5665_HPR_GAIN 0x0006
#define RT5665_MONO_GAIN 0x0007
/* I/O - Input */
#define RT5665_CAL_BST_CTRL 0x000a
#define RT5665_CBJ_BST_CTRL 0x000b
#define RT5665_IN1_IN2 0x000c
#define RT5665_IN3_IN4 0x000d
#define RT5665_INL1_INR1_VOL 0x000f
/* I/O - Speaker */
#define RT5665_EJD_CTRL_1 0x0010
#define RT5665_EJD_CTRL_2 0x0011
#define RT5665_EJD_CTRL_3 0x0012
#define RT5665_EJD_CTRL_4 0x0013
#define RT5665_EJD_CTRL_5 0x0014
#define RT5665_EJD_CTRL_6 0x0015
#define RT5665_EJD_CTRL_7 0x0016
/* I/O - ADC/DAC/DMIC */
#define RT5665_DAC2_CTRL 0x0017
#define RT5665_DAC2_DIG_VOL 0x0018
#define RT5665_DAC1_DIG_VOL 0x0019
#define RT5665_DAC3_DIG_VOL 0x001a
#define RT5665_DAC3_CTRL 0x001b
#define RT5665_STO1_ADC_DIG_VOL 0x001c
#define RT5665_MONO_ADC_DIG_VOL 0x001d
#define RT5665_STO2_ADC_DIG_VOL 0x001e
#define RT5665_STO1_ADC_BOOST 0x001f
#define RT5665_MONO_ADC_BOOST 0x0020
#define RT5665_STO2_ADC_BOOST 0x0021
#define RT5665_HP_IMP_GAIN_1 0x0022
#define RT5665_HP_IMP_GAIN_2 0x0023
/* Mixer - D-D */
#define RT5665_STO1_ADC_MIXER 0x0026
#define RT5665_MONO_ADC_MIXER 0x0027
#define RT5665_STO2_ADC_MIXER 0x0028
#define RT5665_AD_DA_MIXER 0x0029
#define RT5665_STO1_DAC_MIXER 0x002a
#define RT5665_MONO_DAC_MIXER 0x002b
#define RT5665_STO2_DAC_MIXER 0x002c
#define RT5665_A_DAC1_MUX 0x002d
#define RT5665_A_DAC2_MUX 0x002e
#define RT5665_DIG_INF2_DATA 0x002f
#define RT5665_DIG_INF3_DATA 0x0030
/* Mixer - PDM */
#define RT5665_PDM_OUT_CTRL 0x0031
#define RT5665_PDM_DATA_CTRL_1 0x0032
#define RT5665_PDM_DATA_CTRL_2 0x0033
#define RT5665_PDM_DATA_CTRL_3 0x0034
#define RT5665_PDM_DATA_CTRL_4 0x0035
/* Mixer - ADC */
#define RT5665_REC1_GAIN 0x003a
#define RT5665_REC1_L1_MIXER 0x003b
#define RT5665_REC1_L2_MIXER 0x003c
#define RT5665_REC1_R1_MIXER 0x003d
#define RT5665_REC1_R2_MIXER 0x003e
#define RT5665_REC2_GAIN 0x003f
#define RT5665_REC2_L1_MIXER 0x0040
#define RT5665_REC2_L2_MIXER 0x0041
#define RT5665_REC2_R1_MIXER 0x0042
#define RT5665_REC2_R2_MIXER 0x0043
#define RT5665_CAL_REC 0x0044
/* Mixer - DAC */
#define RT5665_ALC_BACK_GAIN 0x0049
#define RT5665_MONOMIX_GAIN 0x004a
#define RT5665_MONOMIX_IN_GAIN 0x004b
#define RT5665_OUT_L_GAIN 0x004d
#define RT5665_OUT_L_MIXER 0x004e
#define RT5665_OUT_R_GAIN 0x004f
#define RT5665_OUT_R_MIXER 0x0050
#define RT5665_LOUT_MIXER 0x0052
/* Power */
#define RT5665_PWR_DIG_1 0x0061
#define RT5665_PWR_DIG_2 0x0062
#define RT5665_PWR_ANLG_1 0x0063
#define RT5665_PWR_ANLG_2 0x0064
#define RT5665_PWR_ANLG_3 0x0065
#define RT5665_PWR_MIXER 0x0066
#define RT5665_PWR_VOL 0x0067
/* Clock Detect */
#define RT5665_CLK_DET 0x006b
/* Filter */
#define RT5665_HPF_CTRL1 0x006d
/* DMIC */
#define RT5665_DMIC_CTRL_1 0x006e
#define RT5665_DMIC_CTRL_2 0x006f
/* Format - ADC/DAC */
#define RT5665_I2S1_SDP 0x0070
#define RT5665_I2S2_SDP 0x0071
#define RT5665_I2S3_SDP 0x0072
#define RT5665_ADDA_CLK_1 0x0073
#define RT5665_ADDA_CLK_2 0x0074
#define RT5665_I2S1_F_DIV_CTRL_1 0x0075
#define RT5665_I2S1_F_DIV_CTRL_2 0x0076
/* Format - TDM Control */
#define RT5665_TDM_CTRL_1 0x0078
#define RT5665_TDM_CTRL_2 0x0079
#define RT5665_TDM_CTRL_3 0x007a
#define RT5665_TDM_CTRL_4 0x007b
#define RT5665_TDM_CTRL_5 0x007c
#define RT5665_TDM_CTRL_6 0x007d
#define RT5665_TDM_CTRL_7 0x007e
#define RT5665_TDM_CTRL_8 0x007f
/* Function - Analog */
#define RT5665_GLB_CLK 0x0080
#define RT5665_PLL_CTRL_1 0x0081
#define RT5665_PLL_CTRL_2 0x0082
#define RT5665_ASRC_1 0x0083
#define RT5665_ASRC_2 0x0084
#define RT5665_ASRC_3 0x0085
#define RT5665_ASRC_4 0x0086
#define RT5665_ASRC_5 0x0087
#define RT5665_ASRC_6 0x0088
#define RT5665_ASRC_7 0x0089
#define RT5665_ASRC_8 0x008a
#define RT5665_ASRC_9 0x008b
#define RT5665_ASRC_10 0x008c
#define RT5665_DEPOP_1 0x008e
#define RT5665_DEPOP_2 0x008f
#define RT5665_HP_CHARGE_PUMP_1 0x0091
#define RT5665_HP_CHARGE_PUMP_2 0x0092
#define RT5665_MICBIAS_1 0x0093
#define RT5665_MICBIAS_2 0x0094
#define RT5665_ASRC_12 0x0098
#define RT5665_ASRC_13 0x0099
#define RT5665_ASRC_14 0x009a
#define RT5665_RC_CLK_CTRL 0x009f
#define RT5665_I2S_M_CLK_CTRL_1 0x00a0
#define RT5665_I2S2_F_DIV_CTRL_1 0x00a1
#define RT5665_I2S2_F_DIV_CTRL_2 0x00a2
#define RT5665_I2S3_F_DIV_CTRL_1 0x00a3
#define RT5665_I2S3_F_DIV_CTRL_2 0x00a4
/* Function - Digital */
#define RT5665_EQ_CTRL_1 0x00ae
#define RT5665_EQ_CTRL_2 0x00af
#define RT5665_IRQ_CTRL_1 0x00b6
#define RT5665_IRQ_CTRL_2 0x00b7
#define RT5665_IRQ_CTRL_3 0x00b8
#define RT5665_IRQ_CTRL_4 0x00b9
#define RT5665_IRQ_CTRL_5 0x00ba
#define RT5665_IRQ_CTRL_6 0x00bb
#define RT5665_INT_ST_1 0x00be
#define RT5665_GPIO_CTRL_1 0x00c0
#define RT5665_GPIO_CTRL_2 0x00c1
#define RT5665_GPIO_CTRL_3 0x00c2
#define RT5665_GPIO_CTRL_4 0x00c3
#define RT5665_GPIO_STA 0x00c4
#define RT5665_HP_AMP_DET_CTRL_1 0x00d0
#define RT5665_HP_AMP_DET_CTRL_2 0x00d1
#define RT5665_MID_HP_AMP_DET 0x00d3
#define RT5665_LOW_HP_AMP_DET 0x00d4
#define RT5665_SV_ZCD_1 0x00d9
#define RT5665_SV_ZCD_2 0x00da
#define RT5665_IL_CMD_1 0x00db
#define RT5665_IL_CMD_2 0x00dc
#define RT5665_IL_CMD_3 0x00dd
#define RT5665_IL_CMD_4 0x00de
#define RT5665_4BTN_IL_CMD_1 0x00df
#define RT5665_4BTN_IL_CMD_2 0x00e0
#define RT5665_4BTN_IL_CMD_3 0x00e1
#define RT5665_PSV_IL_CMD_1 0x00e2
#define RT5665_ADC_STO1_HP_CTRL_1 0x00ea
#define RT5665_ADC_STO1_HP_CTRL_2 0x00eb
#define RT5665_ADC_MONO_HP_CTRL_1 0x00ec
#define RT5665_ADC_MONO_HP_CTRL_2 0x00ed
#define RT5665_ADC_STO2_HP_CTRL_1 0x00ee
#define RT5665_ADC_STO2_HP_CTRL_2 0x00ef
#define RT5665_AJD1_CTRL 0x00f0
#define RT5665_JD1_THD 0x00f1
#define RT5665_JD2_THD 0x00f2
#define RT5665_JD_CTRL_1 0x00f6
#define RT5665_JD_CTRL_2 0x00f7
#define RT5665_JD_CTRL_3 0x00f8
/* General Control */
#define RT5665_DIG_MISC 0x00fa
#define RT5665_DUMMY_2 0x00fb
#define RT5665_DUMMY_3 0x00fc
#define RT5665_DAC_ADC_DIG_VOL1 0x0100
#define RT5665_DAC_ADC_DIG_VOL2 0x0101
#define RT5665_BIAS_CUR_CTRL_1 0x010a
#define RT5665_BIAS_CUR_CTRL_2 0x010b
#define RT5665_BIAS_CUR_CTRL_3 0x010c
#define RT5665_BIAS_CUR_CTRL_4 0x010d
#define RT5665_BIAS_CUR_CTRL_5 0x010e
#define RT5665_BIAS_CUR_CTRL_6 0x010f
#define RT5665_BIAS_CUR_CTRL_7 0x0110
#define RT5665_BIAS_CUR_CTRL_8 0x0111
#define RT5665_BIAS_CUR_CTRL_9 0x0112
#define RT5665_BIAS_CUR_CTRL_10 0x0113
#define RT5665_VREF_REC_OP_FB_CAP_CTRL 0x0117
#define RT5665_CHARGE_PUMP_1 0x0125
#define RT5665_DIG_IN_CTRL_1 0x0132
#define RT5665_DIG_IN_CTRL_2 0x0133
#define RT5665_PAD_DRIVING_CTRL 0x0137
#define RT5665_SOFT_RAMP_DEPOP 0x0138
#define RT5665_PLL 0x0139
#define RT5665_CHOP_DAC 0x013a
#define RT5665_CHOP_ADC 0x013b
#define RT5665_CALIB_ADC_CTRL 0x013c
#define RT5665_VOL_TEST 0x013f
#define RT5665_TEST_MODE_CTRL_1 0x0145
#define RT5665_TEST_MODE_CTRL_2 0x0146
#define RT5665_TEST_MODE_CTRL_3 0x0147
#define RT5665_TEST_MODE_CTRL_4 0x0148
#define RT5665_BASSBACK_CTRL 0x0150
#define RT5665_STO_NG2_CTRL_1 0x0160
#define RT5665_STO_NG2_CTRL_2 0x0161
#define RT5665_STO_NG2_CTRL_3 0x0162
#define RT5665_STO_NG2_CTRL_4 0x0163
#define RT5665_STO_NG2_CTRL_5 0x0164
#define RT5665_STO_NG2_CTRL_6 0x0165
#define RT5665_STO_NG2_CTRL_7 0x0166
#define RT5665_STO_NG2_CTRL_8 0x0167
#define RT5665_MONO_NG2_CTRL_1 0x0170
#define RT5665_MONO_NG2_CTRL_2 0x0171
#define RT5665_MONO_NG2_CTRL_3 0x0172
#define RT5665_MONO_NG2_CTRL_4 0x0173
#define RT5665_MONO_NG2_CTRL_5 0x0174
#define RT5665_MONO_NG2_CTRL_6 0x0175
#define RT5665_STO1_DAC_SIL_DET 0x0190
#define RT5665_MONOL_DAC_SIL_DET 0x0191
#define RT5665_MONOR_DAC_SIL_DET 0x0192
#define RT5665_STO2_DAC_SIL_DET 0x0193
#define RT5665_SIL_PSV_CTRL1 0x0194
#define RT5665_SIL_PSV_CTRL2 0x0195
#define RT5665_SIL_PSV_CTRL3 0x0196
#define RT5665_SIL_PSV_CTRL4 0x0197
#define RT5665_SIL_PSV_CTRL5 0x0198
#define RT5665_SIL_PSV_CTRL6 0x0199
#define RT5665_MONO_AMP_CALIB_CTRL_1 0x01a0
#define RT5665_MONO_AMP_CALIB_CTRL_2 0x01a1
#define RT5665_MONO_AMP_CALIB_CTRL_3 0x01a2
#define RT5665_MONO_AMP_CALIB_CTRL_4 0x01a3
#define RT5665_MONO_AMP_CALIB_CTRL_5 0x01a4
#define RT5665_MONO_AMP_CALIB_CTRL_6 0x01a5
#define RT5665_MONO_AMP_CALIB_CTRL_7 0x01a6
#define RT5665_MONO_AMP_CALIB_STA1 0x01a7
#define RT5665_MONO_AMP_CALIB_STA2 0x01a8
#define RT5665_MONO_AMP_CALIB_STA3 0x01a9
#define RT5665_MONO_AMP_CALIB_STA4 0x01aa
#define RT5665_MONO_AMP_CALIB_STA6 0x01ab
#define RT5665_HP_IMP_SENS_CTRL_01 0x01b5
#define RT5665_HP_IMP_SENS_CTRL_02 0x01b6
#define RT5665_HP_IMP_SENS_CTRL_03 0x01b7
#define RT5665_HP_IMP_SENS_CTRL_04 0x01b8
#define RT5665_HP_IMP_SENS_CTRL_05 0x01b9
#define RT5665_HP_IMP_SENS_CTRL_06 0x01ba
#define RT5665_HP_IMP_SENS_CTRL_07 0x01bb
#define RT5665_HP_IMP_SENS_CTRL_08 0x01bc
#define RT5665_HP_IMP_SENS_CTRL_09 0x01bd
#define RT5665_HP_IMP_SENS_CTRL_10 0x01be
#define RT5665_HP_IMP_SENS_CTRL_11 0x01bf
#define RT5665_HP_IMP_SENS_CTRL_12 0x01c0
#define RT5665_HP_IMP_SENS_CTRL_13 0x01c1
#define RT5665_HP_IMP_SENS_CTRL_14 0x01c2
#define RT5665_HP_IMP_SENS_CTRL_15 0x01c3
#define RT5665_HP_IMP_SENS_CTRL_16 0x01c4
#define RT5665_HP_IMP_SENS_CTRL_17 0x01c5
#define RT5665_HP_IMP_SENS_CTRL_18 0x01c6
#define RT5665_HP_IMP_SENS_CTRL_19 0x01c7
#define RT5665_HP_IMP_SENS_CTRL_20 0x01c8
#define RT5665_HP_IMP_SENS_CTRL_21 0x01c9
#define RT5665_HP_IMP_SENS_CTRL_22 0x01ca
#define RT5665_HP_IMP_SENS_CTRL_23 0x01cb
#define RT5665_HP_IMP_SENS_CTRL_24 0x01cc
#define RT5665_HP_IMP_SENS_CTRL_25 0x01cd
#define RT5665_HP_IMP_SENS_CTRL_26 0x01ce
#define RT5665_HP_IMP_SENS_CTRL_27 0x01cf
#define RT5665_HP_IMP_SENS_CTRL_28 0x01d0
#define RT5665_HP_IMP_SENS_CTRL_29 0x01d1
#define RT5665_HP_IMP_SENS_CTRL_30 0x01d2
#define RT5665_HP_IMP_SENS_CTRL_31 0x01d3
#define RT5665_HP_IMP_SENS_CTRL_32 0x01d4
#define RT5665_HP_IMP_SENS_CTRL_33 0x01d5
#define RT5665_HP_IMP_SENS_CTRL_34 0x01d6
#define RT5665_HP_LOGIC_CTRL_1 0x01da
#define RT5665_HP_LOGIC_CTRL_2 0x01db
#define RT5665_HP_LOGIC_CTRL_3 0x01dc
#define RT5665_HP_CALIB_CTRL_1 0x01de
#define RT5665_HP_CALIB_CTRL_2 0x01df
#define RT5665_HP_CALIB_CTRL_3 0x01e0
#define RT5665_HP_CALIB_CTRL_4 0x01e1
#define RT5665_HP_CALIB_CTRL_5 0x01e2
#define RT5665_HP_CALIB_CTRL_6 0x01e3
#define RT5665_HP_CALIB_CTRL_7 0x01e4
#define RT5665_HP_CALIB_CTRL_9 0x01e6
#define RT5665_HP_CALIB_CTRL_10 0x01e7
#define RT5665_HP_CALIB_CTRL_11 0x01e8
#define RT5665_HP_CALIB_STA_1 0x01ea
#define RT5665_HP_CALIB_STA_2 0x01eb
#define RT5665_HP_CALIB_STA_3 0x01ec
#define RT5665_HP_CALIB_STA_4 0x01ed
#define RT5665_HP_CALIB_STA_5 0x01ee
#define RT5665_HP_CALIB_STA_6 0x01ef
#define RT5665_HP_CALIB_STA_7 0x01f0
#define RT5665_HP_CALIB_STA_8 0x01f1
#define RT5665_HP_CALIB_STA_9 0x01f2
#define RT5665_HP_CALIB_STA_10 0x01f3
#define RT5665_HP_CALIB_STA_11 0x01f4
#define RT5665_PGM_TAB_CTRL1 0x0200
#define RT5665_PGM_TAB_CTRL2 0x0201
#define RT5665_PGM_TAB_CTRL3 0x0202
#define RT5665_PGM_TAB_CTRL4 0x0203
#define RT5665_PGM_TAB_CTRL5 0x0204
#define RT5665_PGM_TAB_CTRL6 0x0205
#define RT5665_PGM_TAB_CTRL7 0x0206
#define RT5665_PGM_TAB_CTRL8 0x0207
#define RT5665_PGM_TAB_CTRL9 0x0208
#define RT5665_SAR_IL_CMD_1 0x0210
#define RT5665_SAR_IL_CMD_2 0x0211
#define RT5665_SAR_IL_CMD_3 0x0212
#define RT5665_SAR_IL_CMD_4 0x0213
#define RT5665_SAR_IL_CMD_5 0x0214
#define RT5665_SAR_IL_CMD_6 0x0215
#define RT5665_SAR_IL_CMD_7 0x0216
#define RT5665_SAR_IL_CMD_8 0x0217
#define RT5665_SAR_IL_CMD_9 0x0218
#define RT5665_SAR_IL_CMD_10 0x0219
#define RT5665_SAR_IL_CMD_11 0x021a
#define RT5665_SAR_IL_CMD_12 0x021b
#define RT5665_DRC1_CTRL_0 0x02ff
#define RT5665_DRC1_CTRL_1 0x0300
#define RT5665_DRC1_CTRL_2 0x0301
#define RT5665_DRC1_CTRL_3 0x0302
#define RT5665_DRC1_CTRL_4 0x0303
#define RT5665_DRC1_CTRL_5 0x0304
#define RT5665_DRC1_CTRL_6 0x0305
#define RT5665_DRC1_HARD_LMT_CTRL_1 0x0306
#define RT5665_DRC1_HARD_LMT_CTRL_2 0x0307
#define RT5665_DRC1_PRIV_1 0x0310
#define RT5665_DRC1_PRIV_2 0x0311
#define RT5665_DRC1_PRIV_3 0x0312
#define RT5665_DRC1_PRIV_4 0x0313
#define RT5665_DRC1_PRIV_5 0x0314
#define RT5665_DRC1_PRIV_6 0x0315
#define RT5665_DRC1_PRIV_7 0x0316
#define RT5665_DRC1_PRIV_8 0x0317
#define RT5665_ALC_PGA_CTRL_1 0x0330
#define RT5665_ALC_PGA_CTRL_2 0x0331
#define RT5665_ALC_PGA_CTRL_3 0x0332
#define RT5665_ALC_PGA_CTRL_4 0x0333
#define RT5665_ALC_PGA_CTRL_5 0x0334
#define RT5665_ALC_PGA_CTRL_6 0x0335
#define RT5665_ALC_PGA_CTRL_7 0x0336
#define RT5665_ALC_PGA_CTRL_8 0x0337
#define RT5665_ALC_PGA_STA_1 0x0338
#define RT5665_ALC_PGA_STA_2 0x0339
#define RT5665_ALC_PGA_STA_3 0x033a
#define RT5665_EQ_AUTO_RCV_CTRL1 0x03c0
#define RT5665_EQ_AUTO_RCV_CTRL2 0x03c1
#define RT5665_EQ_AUTO_RCV_CTRL3 0x03c2
#define RT5665_EQ_AUTO_RCV_CTRL4 0x03c3
#define RT5665_EQ_AUTO_RCV_CTRL5 0x03c4
#define RT5665_EQ_AUTO_RCV_CTRL6 0x03c5
#define RT5665_EQ_AUTO_RCV_CTRL7 0x03c6
#define RT5665_EQ_AUTO_RCV_CTRL8 0x03c7
#define RT5665_EQ_AUTO_RCV_CTRL9 0x03c8
#define RT5665_EQ_AUTO_RCV_CTRL10 0x03c9
#define RT5665_EQ_AUTO_RCV_CTRL11 0x03ca
#define RT5665_EQ_AUTO_RCV_CTRL12 0x03cb
#define RT5665_EQ_AUTO_RCV_CTRL13 0x03cc
#define RT5665_ADC_L_EQ_LPF1_A1 0x03d0
#define RT5665_R_EQ_LPF1_A1 0x03d1
#define RT5665_L_EQ_LPF1_H0 0x03d2
#define RT5665_R_EQ_LPF1_H0 0x03d3
#define RT5665_L_EQ_BPF1_A1 0x03d4
#define RT5665_R_EQ_BPF1_A1 0x03d5
#define RT5665_L_EQ_BPF1_A2 0x03d6
#define RT5665_R_EQ_BPF1_A2 0x03d7
#define RT5665_L_EQ_BPF1_H0 0x03d8
#define RT5665_R_EQ_BPF1_H0 0x03d9
#define RT5665_L_EQ_BPF2_A1 0x03da
#define RT5665_R_EQ_BPF2_A1 0x03db
#define RT5665_L_EQ_BPF2_A2 0x03dc
#define RT5665_R_EQ_BPF2_A2 0x03dd
#define RT5665_L_EQ_BPF2_H0 0x03de
#define RT5665_R_EQ_BPF2_H0 0x03df
#define RT5665_L_EQ_BPF3_A1 0x03e0
#define RT5665_R_EQ_BPF3_A1 0x03e1
#define RT5665_L_EQ_BPF3_A2 0x03e2
#define RT5665_R_EQ_BPF3_A2 0x03e3
#define RT5665_L_EQ_BPF3_H0 0x03e4
#define RT5665_R_EQ_BPF3_H0 0x03e5
#define RT5665_L_EQ_BPF4_A1 0x03e6
#define RT5665_R_EQ_BPF4_A1 0x03e7
#define RT5665_L_EQ_BPF4_A2 0x03e8
#define RT5665_R_EQ_BPF4_A2 0x03e9
#define RT5665_L_EQ_BPF4_H0 0x03ea
#define RT5665_R_EQ_BPF4_H0 0x03eb
#define RT5665_L_EQ_HPF1_A1 0x03ec
#define RT5665_R_EQ_HPF1_A1 0x03ed
#define RT5665_L_EQ_HPF1_H0 0x03ee
#define RT5665_R_EQ_HPF1_H0 0x03ef
#define RT5665_L_EQ_PRE_VOL 0x03f0
#define RT5665_R_EQ_PRE_VOL 0x03f1
#define RT5665_L_EQ_POST_VOL 0x03f2
#define RT5665_R_EQ_POST_VOL 0x03f3
#define RT5665_SCAN_MODE_CTRL 0x07f0
#define RT5665_I2C_MODE 0x07fa
/* global definition */
#define RT5665_L_MUTE (0x1 << 15)
#define RT5665_L_MUTE_SFT 15
#define RT5665_VOL_L_MUTE (0x1 << 14)
#define RT5665_VOL_L_SFT 14
#define RT5665_R_MUTE (0x1 << 7)
#define RT5665_R_MUTE_SFT 7
#define RT5665_VOL_R_MUTE (0x1 << 6)
#define RT5665_VOL_R_SFT 6
#define RT5665_L_VOL_MASK (0x3f << 8)
#define RT5665_L_VOL_SFT 8
#define RT5665_R_VOL_MASK (0x3f)
#define RT5665_R_VOL_SFT 0
/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
#define RT5665_G_HP (0xf << 8)
#define RT5665_G_HP_SFT 8
#define RT5665_G_STO_DA_DMIX (0xf)
#define RT5665_G_STO_DA_SFT 0
/* CBJ Control (0x000b) */
#define RT5665_BST_CBJ_MASK (0xf << 8)
#define RT5665_BST_CBJ_SFT 8
/* IN1/IN2 Control (0x000c) */
#define RT5665_IN1_DF_MASK (0x1 << 15)
#define RT5665_IN1_DF 15
#define RT5665_BST1_MASK (0x7f << 8)
#define RT5665_BST1_SFT 8
#define RT5665_IN2_DF_MASK (0x1 << 7)
#define RT5665_IN2_DF 7
#define RT5665_BST2_MASK (0x7f)
#define RT5665_BST2_SFT 0
/* IN3/IN4 Control (0x000d) */
#define RT5665_IN3_DF_MASK (0x1 << 15)
#define RT5665_IN3_DF 15
#define RT5665_BST3_MASK (0x7f << 8)
#define RT5665_BST3_SFT 8
#define RT5665_IN4_DF_MASK (0x1 << 7)
#define RT5665_IN4_DF 7
#define RT5665_BST4_MASK (0x7f)
#define RT5665_BST4_SFT 0
/* INL and INR Volume Control (0x000f) */
#define RT5665_INL_VOL_MASK (0x1f << 8)
#define RT5665_INL_VOL_SFT 8
#define RT5665_INR_VOL_MASK (0x1f)
#define RT5665_INR_VOL_SFT 0
/* Embeeded Jack and Type Detection Control 1 (0x0010) */
#define RT5665_EMB_JD_EN (0x1 << 15)
#define RT5665_EMB_JD_EN_SFT 15
#define RT5665_JD_MODE (0x1 << 13)
#define RT5665_JD_MODE_SFT 13
#define RT5665_POLA_EXT_JD_MASK (0x1 << 11)
#define RT5665_POLA_EXT_JD_LOW (0x1 << 11)
#define RT5665_POLA_EXT_JD_HIGH (0x0 << 11)
#define RT5665_EXT_JD_DIG (0x1 << 9)
#define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
#define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
#define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
#define RT5665_VREF_POW_MASK (0x1 << 6)
#define RT5665_VREF_POW_FSM (0x0 << 6)
#define RT5665_VREF_POW_REG (0x1 << 6)
#define RT5665_MB1_PATH_MASK (0x1 << 5)
#define RT5665_CTRL_MB1_REG (0x1 << 5)
#define RT5665_CTRL_MB1_FSM (0x0 << 5)
#define RT5665_MB2_PATH_MASK (0x1 << 4)
#define RT5665_CTRL_MB2_REG (0x1 << 4)
#define RT5665_CTRL_MB2_FSM (0x0 << 4)
#define RT5665_TRIG_JD_MASK (0x1 << 3)
#define RT5665_TRIG_JD_HIGH (0x1 << 3)
#define RT5665_TRIG_JD_LOW (0x0 << 3)
/* Embeeded Jack and Type Detection Control 2 (0x0011) */
#define RT5665_EXT_JD_SRC (0x7 << 4)
#define RT5665_EXT_JD_SRC_SFT 4
#define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
#define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
#define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4)
#define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)
#define RT5665_EXT_JD_SRC_JD2 (0x4 << 4)
#define RT5665_EXT_JD_SRC_JD3 (0x5 << 4)
#define RT5665_EXT_JD_SRC_MANUAL (0x6 << 4)
/* Combo Jack and Type Detection Control 4 (0x0013) */
#define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
#define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
#define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
#define RT5665_CBJ_JD_TEST_MASK (0x1 << 6)
#define RT5665_CBJ_JD_TEST_NORM (0x0 << 6)
#define RT5665_CBJ_JD_TEST_MODE (0x1 << 6)
/* Slience Detection Control (0x0015) */
#define RT5665_SIL_DET_MASK (0x1 << 15)
#define RT5665_SIL_DET_DIS (0x0 << 15)
#define RT5665_SIL_DET_EN (0x1 << 15)
/* DAC2 Control (0x0017) */
#define RT5665_M_DAC2_L_VOL (0x1 << 13)
#define RT5665_M_DAC2_L_VOL_SFT 13
#define RT5665_M_DAC2_R_VOL (0x1 << 12)
#define RT5665_M_DAC2_R_VOL_SFT 12
#define RT5665_DAC_L2_SEL_MASK (0x7 << 4)
#define RT5665_DAC_L2_SEL_SFT 4
#define RT5665_DAC_R2_SEL_MASK (0x7 << 0)
#define RT5665_DAC_R2_SEL_SFT 0
/* Sidetone Control (0x0018) */
#define RT5665_ST_SEL_MASK (0x7 << 9)
#define RT5665_ST_SEL_SFT 9
#define RT5665_ST_EN (0x1 << 6)
#define RT5665_ST_EN_SFT 6
/* DAC1 Digital Volume (0x0019) */
#define RT5665_DAC_L1_VOL_MASK (0xff << 8)
#define RT5665_DAC_L1_VOL_SFT 8
#define RT5665_DAC_R1_VOL_MASK (0xff)
#define RT5665_DAC_R1_VOL_SFT 0
/* DAC2 Digital Volume (0x001a) */
#define RT5665_DAC_L2_VOL_MASK (0xff << 8)
#define RT5665_DAC_L2_VOL_SFT 8
#define RT5665_DAC_R2_VOL_MASK (0xff)
#define RT5665_DAC_R2_VOL_SFT 0
/* DAC3 Control (0x001b) */
#define RT5665_M_DAC3_L_VOL (0x1 << 13)
#define RT5665_M_DAC3_L_VOL_SFT 13
#define RT5665_M_DAC3_R_VOL (0x1 << 12)
#define RT5665_M_DAC3_R_VOL_SFT 12
#define RT5665_DAC_L3_SEL_MASK (0x7 << 4)
#define RT5665_DAC_L3_SEL_SFT 4
#define RT5665_DAC_R3_SEL_MASK (0x7 << 0)
#define RT5665_DAC_R3_SEL_SFT 0
/* ADC Digital Volume Control (0x001c) */
#define RT5665_ADC_L_VOL_MASK (0x7f << 8)
#define RT5665_ADC_L_VOL_SFT 8
#define RT5665_ADC_R_VOL_MASK (0x7f)
#define RT5665_ADC_R_VOL_SFT 0
/* Mono ADC Digital Volume Control (0x001d) */
#define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
#define RT5665_MONO_ADC_L_VOL_SFT 8
#define RT5665_MONO_ADC_R_VOL_MASK (0x7f)
#define RT5665_MONO_ADC_R_VOL_SFT 0
/* Stereo1 ADC Boost Gain Control (0x001f) */
#define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14)
#define RT5665_STO1_ADC_L_BST_SFT 14
#define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
#define RT5665_STO1_ADC_R_BST_SFT 12
/* Mono ADC Boost Gain Control (0x0020) */
#define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14)
#define RT5665_MONO_ADC_L_BST_SFT 14
#define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
#define RT5665_MONO_ADC_R_BST_SFT 12
/* Stereo1 ADC Boost Gain Control (0x001f) */
#define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14)
#define RT5665_STO2_ADC_L_BST_SFT 14
#define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
#define RT5665_STO2_ADC_R_BST_SFT 12
/* Stereo1 ADC Mixer Control (0x0026) */
#define RT5665_M_STO1_ADC_L1 (0x1 << 15)
#define RT5665_M_STO1_ADC_L1_SFT 15
#define RT5665_M_STO1_ADC_L2 (0x1 << 14)
#define RT5665_M_STO1_ADC_L2_SFT 14
#define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)
#define RT5665_STO1_ADC1L_SRC_SFT 13
#define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)
#define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13)
#define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
#define RT5665_STO1_ADC2L_SRC_SFT 12
#define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10)
#define RT5665_STO1_ADCL_SRC_SFT 10
#define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)
#define RT5665_STO1_DD_L_SRC_SFT 9
#define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
#define RT5665_STO1_DMIC_SRC_SFT 8
#define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
#define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
#define RT5665_M_STO1_ADC_R1 (0x1 << 7)
#define RT5665_M_STO1_ADC_R1_SFT 7
#define RT5665_M_STO1_ADC_R2 (0x1 << 6)
#define RT5665_M_STO1_ADC_R2_SFT 6
#define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5)
#define RT5665_STO1_ADC1R_SRC_SFT 5
#define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4)
#define RT5665_STO1_ADC2R_SRC_SFT 4
#define RT5665_STO1_ADCR_SRC_MASK (0x3 << 2)
#define RT5665_STO1_ADCR_SRC_SFT 2
#define RT5665_STO1_DD_R_SRC_MASK (0x3)
#define RT5665_STO1_DD_R_SRC_SFT 0
/* Mono1 ADC Mixer control (0x0027) */
#define RT5665_M_MONO_ADC_L1 (0x1 << 15)
#define RT5665_M_MONO_ADC_L1_SFT 15
#define RT5665_M_MONO_ADC_L2 (0x1 << 14)
#define RT5665_M_MONO_ADC_L2_SFT 14
#define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)
#define RT5665_MONO_ADC_L1_SRC_SFT 13
#define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
#define RT5665_MONO_ADC_L2_SRC_SFT 12
#define RT5665_MONO_ADC_L_SRC_MASK (0x3 << 10)
#define RT5665_MONO_ADC_L_SRC_SFT 10
#define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)
#define RT5665_MONO_DD_L_SRC_SFT 9
#define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
#define RT5665_MONO_DMIC_L_SRC_SFT 8
#define RT5665_M_MONO_ADC_R1 (0x1 << 7)
#define RT5665_M_MONO_ADC_R1_SFT 7
#define RT5665_M_MONO_ADC_R2 (0x1 << 6)
#define RT5665_M_MONO_ADC_R2_SFT 6
#define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5)
#define RT5665_MONO_ADC_R1_SRC_SFT 5
#define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4)
#define RT5665_MONO_ADC_R2_SRC_SFT 4
#define RT5665_MONO_ADC_R_SRC_MASK (0x3 << 2)
#define RT5665_MONO_ADC_R_SRC_SFT 2
#define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1)
#define RT5665_MONO_DD_R_SRC_SFT 1
#define RT5665_MONO_DMIC_R_SRC_MASK 0x1
#define RT5665_MONO_DMIC_R_SRC_SFT 0
/* Stereo2 ADC Mixer Control (0x0028) */
#define RT5665_M_STO2_ADC_L1 (0x1 << 15)
#define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)
#define RT5665_M_STO2_ADC_L1_SFT 15
#define RT5665_M_STO2_ADC_L2 (0x1 << 14)
#define RT5665_M_STO2_ADC_L2_SFT 14
#define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)
#define RT5665_STO2_ADC1L_SRC_SFT 13
#define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)
#define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13)
#define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
#define RT5665_STO2_ADC2L_SRC_SFT 12
#define RT5665_STO2_ADCL_SRC_MASK (0x3 << 10)
#define RT5665_STO2_ADCL_SRC_SFT 10
#define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)
#define RT5665_STO2_DD_L_SRC_SFT 9
#define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
#define RT5665_STO2_DMIC_SRC_SFT 8
#define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
#define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
#define RT5665_M_STO2_ADC_R1 (0x1 << 7)
#define RT5665_M_STO2_ADC_R1_UN (0x0 << 7)
#define RT5665_M_STO2_ADC_R1_SFT 7
#define RT5665_M_STO2_ADC_R2 (0x1 << 6)
#define RT5665_M_STO2_ADC_R2_SFT 6
#define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5)
#define RT5665_STO2_ADC1R_SRC_SFT 5
#define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4)
#define RT5665_STO2_ADC2R_SRC_SFT 4
#define RT5665_STO2_ADCR_SRC_MASK (0x3 << 2)
#define RT5665_STO2_ADCR_SRC_SFT 2
#define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1)
#define RT5665_STO2_DD_R_SRC_SFT 1
/* ADC Mixer to DAC Mixer Control (0x0029) */
#define RT5665_M_ADCMIX_L (0x1 << 15)
#define RT5665_M_ADCMIX_L_SFT 15
#define RT5665_M_DAC1_L (0x1 << 14)
#define RT5665_M_DAC1_L_SFT 14
#define RT5665_DAC1_R_SEL_MASK (0x3 << 10)
#define RT5665_DAC1_R_SEL_SFT 10
#define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
#define RT5665_DAC1_L_SEL_SFT 8
#define RT5665_M_ADCMIX_R (0x1 << 7)
#define RT5665_M_ADCMIX_R_SFT 7
#define RT5665_M_DAC1_R (0x1 << 6)
#define RT5665_M_DAC1_R_SFT 6
/* Stereo1 DAC Mixer Control (0x002a) */
#define RT5665_M_DAC_L1_STO_L (0x1 << 15)
#define RT5665_M_DAC_L1_STO_L_SFT 15
#define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14)
#define RT5665_G_DAC_L1_STO_L_SFT 14
#define RT5665_M_DAC_R1_STO_L (0x1 << 13)
#define RT5665_M_DAC_R1_STO_L_SFT 13
#define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
#define RT5665_G_DAC_R1_STO_L_SFT 12
#define RT5665_M_DAC_L2_STO_L (0x1 << 11)
#define RT5665_M_DAC_L2_STO_L_SFT 11
#define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10)
#define RT5665_G_DAC_L2_STO_L_SFT 10
#define RT5665_M_DAC_R2_STO_L (0x1 << 9)
#define RT5665_M_DAC_R2_STO_L_SFT 9
#define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
#define RT5665_G_DAC_R2_STO_L_SFT 8
#define RT5665_M_DAC_L1_STO_R (0x1 << 7)
#define RT5665_M_DAC_L1_STO_R_SFT 7
#define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6)
#define RT5665_G_DAC_L1_STO_R_SFT 6
#define RT5665_M_DAC_R1_STO_R (0x1 << 5)
#define RT5665_M_DAC_R1_STO_R_SFT 5
#define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4)
#define RT5665_G_DAC_R1_STO_R_SFT 4
#define RT5665_M_DAC_L2_STO_R (0x1 << 3)
#define RT5665_M_DAC_L2_STO_R_SFT 3
#define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2)
#define RT5665_G_DAC_L2_STO_R_SFT 2
#define RT5665_M_DAC_R2_STO_R (0x1 << 1)
#define RT5665_M_DAC_R2_STO_R_SFT 1
#define RT5665_G_DAC_R2_STO_R_MASK (0x1)
#define RT5665_G_DAC_R2_STO_R_SFT 0
/* Mono DAC Mixer Control (0x002b) */
#define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
#define RT5665_M_DAC_L1_MONO_L_SFT 15
#define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14)
#define RT5665_G_DAC_L1_MONO_L_SFT 14
#define RT5665_M_DAC_R1_MONO_L (0x1 << 13)
#define RT5665_M_DAC_R1_MONO_L_SFT 13
#define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
#define RT5665_G_DAC_R1_MONO_L_SFT 12
#define RT5665_M_DAC_L2_MONO_L (0x1 << 11)
#define RT5665_M_DAC_L2_MONO_L_SFT 11
#define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10)
#define RT5665_G_DAC_L2_MONO_L_SFT 10
#define RT5665_M_DAC_R2_MONO_L (0x1 << 9)
#define RT5665_M_DAC_R2_MONO_L_SFT 9
#define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
#define RT5665_G_DAC_R2_MONO_L_SFT 8
#define RT5665_M_DAC_L1_MONO_R (0x1 << 7)
#define RT5665_M_DAC_L1_MONO_R_SFT 7
#define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6)
#define RT5665_G_DAC_L1_MONO_R_SFT 6
#define RT5665_M_DAC_R1_MONO_R (0x1 << 5)
#define RT5665_M_DAC_R1_MONO_R_SFT 5
#define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4)
#define RT5665_G_DAC_R1_MONO_R_SFT 4
#define RT5665_M_DAC_L2_MONO_R (0x1 << 3)
#define RT5665_M_DAC_L2_MONO_R_SFT 3
#define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2)
#define RT5665_G_DAC_L2_MONO_R_SFT 2
#define RT5665_M_DAC_R2_MONO_R (0x1 << 1)
#define RT5665_M_DAC_R2_MONO_R_SFT 1
#define RT5665_G_DAC_R2_MONO_R_MASK (0x1)
#define RT5665_G_DAC_R2_MONO_R_SFT 0
/* Stereo2 DAC Mixer Control (0x002c) */
#define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
#define RT5665_M_DAC_L1_STO2_L_SFT 15
#define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14)
#define RT5665_G_DAC_L1_STO2_L_SFT 14
#define RT5665_M_DAC_L2_STO2_L (0x1 << 13)
#define RT5665_M_DAC_L2_STO2_L_SFT 13
#define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
#define RT5665_G_DAC_L2_STO2_L_SFT 12
#define RT5665_M_DAC_L3_STO2_L (0x1 << 11)
#define RT5665_M_DAC_L3_STO2_L_SFT 11
#define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10)
#define RT5665_G_DAC_L3_STO2_L_SFT 10
#define RT5665_M_ST_DAC_L1 (0x1 << 9)
#define RT5665_M_ST_DAC_L1_SFT 9
#define RT5665_M_ST_DAC_R1 (0x1 << 8)
#define RT5665_M_ST_DAC_R1_SFT 8
#define RT5665_M_DAC_R1_STO2_R (0x1 << 7)
#define RT5665_M_DAC_R1_STO2_R_SFT 7
#define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6)
#define RT5665_G_DAC_R1_STO2_R_SFT 6
#define RT5665_M_DAC_R2_STO2_R (0x1 << 5)
#define RT5665_M_DAC_R2_STO2_R_SFT 5
#define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4)
#define RT5665_G_DAC_R2_STO2_R_SFT 4
#define RT5665_M_DAC_R3_STO2_R (0x1 << 3)
#define RT5665_M_DAC_R3_STO2_R_SFT 3
#define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2)
#define RT5665_G_DAC_R3_STO2_R_SFT 2
/* Analog DAC1 Input Source Control (0x002d) */
#define RT5665_DAC_MIX_L_MASK (0x3 << 12)
#define RT5665_DAC_MIX_L_SFT 12
#define RT5665_DAC_MIX_R_MASK (0x3 << 8)
#define RT5665_DAC_MIX_R_SFT 8
#define RT5665_DAC_L1_SRC_MASK (0x3 << 4)
#define RT5665_A_DACL1_SFT 4
#define RT5665_DAC_R1_SRC_MASK (0x3)
#define RT5665_A_DACR1_SFT 0
/* Analog DAC Input Source Control (0x002e) */
#define RT5665_A_DACL2_SEL (0x1 << 4)
#define RT5665_A_DACL2_SFT 4
#define RT5665_A_DACR2_SEL (0x1 << 0)
#define RT5665_A_DACR2_SFT 0
/* Digital Interface Data Control (0x002f) */
#define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
#define RT5665_IF2_1_ADC_IN_SFT 12
#define RT5665_IF2_1_DAC_SEL_MASK (0x3 << 10)
#define RT5665_IF2_1_DAC_SEL_SFT 10
#define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
#define RT5665_IF2_1_ADC_SEL_SFT 8
#define RT5665_IF2_2_ADC_IN_MASK (0x7 << 4)
#define RT5665_IF2_2_ADC_IN_SFT 4
#define RT5665_IF2_2_DAC_SEL_MASK (0x3 << 2)
#define RT5665_IF2_2_DAC_SEL_SFT 2
#define RT5665_IF2_2_ADC_SEL_MASK (0x3 << 0)
#define RT5665_IF2_2_ADC_SEL_SFT 0
/* Digital Interface Data Control (0x0030) */
#define RT5665_IF3_ADC_IN_MASK (0x7 << 4)
#define RT5665_IF3_ADC_IN_SFT 4
#define RT5665_IF3_DAC_SEL_MASK (0x3 << 2)
#define RT5665_IF3_DAC_SEL_SFT 2
#define RT5665_IF3_ADC_SEL_MASK (0x3 << 0)
#define RT5665_IF3_ADC_SEL_SFT 0
/* PDM Output Control (0x0031) */
#define RT5665_M_PDM1_L (0x1 << 14)
#define RT5665_M_PDM1_L_SFT 14
#define RT5665_M_PDM1_R (0x1 << 12)
#define RT5665_M_PDM1_R_SFT 12
#define RT5665_PDM1_L_MASK (0x3 << 10)
#define RT5665_PDM1_L_SFT 10
#define RT5665_PDM1_R_MASK (0x3 << 8)
#define RT5665_PDM1_R_SFT 8
#define RT5665_PDM1_BUSY (0x1 << 6)
#define RT5665_PDM_PATTERN (0x1 << 5)
#define RT5665_PDM_GAIN (0x1 << 4)
#define RT5665_LRCK_PDM_PI2C (0x1 << 3)
#define RT5665_PDM_DIV_MASK (0x3)
/*S/PDIF Output Control (0x0036) */
#define RT5665_SPDIF_SEL_MASK (0x3 << 0)
#define RT5665_SPDIF_SEL_SFT 0
/* REC Left Mixer Control 2 (0x003c) */
#define RT5665_M_CBJ_RM1_L (0x1 << 7)
#define RT5665_M_CBJ_RM1_L_SFT 7
#define RT5665_M_BST1_RM1_L (0x1 << 5)
#define RT5665_M_BST1_RM1_L_SFT 5
#define RT5665_M_BST2_RM1_L (0x1 << 4)
#define RT5665_M_BST2_RM1_L_SFT 4
#define RT5665_M_BST3_RM1_L (0x1 << 3)
#define RT5665_M_BST3_RM1_L_SFT 3
#define RT5665_M_BST4_RM1_L (0x1 << 2)
#define RT5665_M_BST4_RM1_L_SFT 2
#define RT5665_M_INL_RM1_L (0x1 << 1)
#define RT5665_M_INL_RM1_L_SFT 1
#define RT5665_M_INR_RM1_L (0x1)
#define RT5665_M_INR_RM1_L_SFT 0
/* REC Right Mixer Control 2 (0x003e) */
#define RT5665_M_AEC_REF_RM1_R (0x1 << 7)
#define RT5665_M_AEC_REF_RM1_R_SFT 7
#define RT5665_M_BST1_RM1_R (0x1 << 5)
#define RT5665_M_BST1_RM1_R_SFT 5
#define RT5665_M_BST2_RM1_R (0x1 << 4)
#define RT5665_M_BST2_RM1_R_SFT 4
#define RT5665_M_BST3_RM1_R (0x1 << 3)
#define RT5665_M_BST3_RM1_R_SFT 3
#define RT5665_M_BST4_RM1_R (0x1 << 2)
#define RT5665_M_BST4_RM1_R_SFT 2
#define RT5665_M_INR_RM1_R (0x1 << 1)
#define RT5665_M_INR_RM1_R_SFT 1
#define RT5665_M_MONOVOL_RM1_R (0x1)
#define RT5665_M_MONOVOL_RM1_R_SFT 0
/* REC Mixer 2 Left Control 2 (0x0041) */
#define RT5665_M_CBJ_RM2_L (0x1 << 7)
#define RT5665_M_CBJ_RM2_L_SFT 7
#define RT5665_M_BST1_RM2_L (0x1 << 5)
#define RT5665_M_BST1_RM2_L_SFT 5
#define RT5665_M_BST2_RM2_L (0x1 << 4)
#define RT5665_M_BST2_RM2_L_SFT 4
#define RT5665_M_BST3_RM2_L (0x1 << 3)
#define RT5665_M_BST3_RM2_L_SFT 3
#define RT5665_M_BST4_RM2_L (0x1 << 2)
#define RT5665_M_BST4_RM2_L_SFT 2
#define RT5665_M_INL_RM2_L (0x1 << 1)
#define RT5665_M_INL_RM2_L_SFT 1
#define RT5665_M_INR_RM2_L (0x1)
#define RT5665_M_INR_RM2_L_SFT 0
/* REC Mixer 2 Right Control 2 (0x0043) */
#define RT5665_M_MONOVOL_RM2_R (0x1 << 7)
#define RT5665_M_MONOVOL_RM2_R_SFT 7
#define RT5665_M_BST1_RM2_R (0x1 << 5)
#define RT5665_M_BST1_RM2_R_SFT 5
#define RT5665_M_BST2_RM2_R (0x1 << 4)
#define RT5665_M_BST2_RM2_R_SFT 4
#define RT5665_M_BST3_RM2_R (0x1 << 3)
#define RT5665_M_BST3_RM2_R_SFT 3
#define RT5665_M_BST4_RM2_R (0x1 << 2)
#define RT5665_M_BST4_RM2_R_SFT 2
#define RT5665_M_INL_RM2_R (0x1 << 1)
#define RT5665_M_INL_RM2_R_SFT 1
#define RT5665_M_INR_RM2_R (0x1)
#define RT5665_M_INR_RM2_R_SFT 0
/* SPK Left Mixer Control (0x0046) */
#define RT5665_M_BST3_SM_L (0x1 << 4)
#define RT5665_M_BST3_SM_L_SFT 4
#define RT5665_M_IN_R_SM_L (0x1 << 3)
#define RT5665_M_IN_R_SM_L_SFT 3
#define RT5665_M_IN_L_SM_L (0x1 << 2)
#define RT5665_M_IN_L_SM_L_SFT 2
#define RT5665_M_BST1_SM_L (0x1 << 1)
#define RT5665_M_BST1_SM_L_SFT 1
#define RT5665_M_DAC_L2_SM_L (0x1)
#define RT5665_M_DAC_L2_SM_L_SFT 0
/* SPK Right Mixer Control (0x0047) */
#define RT5665_M_BST3_SM_R (0x1 << 4)
#define RT5665_M_BST3_SM_R_SFT 4
#define RT5665_M_IN_R_SM_R (0x1 << 3)
#define RT5665_M_IN_R_SM_R_SFT 3
#define RT5665_M_IN_L_SM_R (0x1 << 2)
#define RT5665_M_IN_L_SM_R_SFT 2
#define RT5665_M_BST4_SM_R (0x1 << 1)
#define RT5665_M_BST4_SM_R_SFT 1
#define RT5665_M_DAC_R2_SM_R (0x1)
#define RT5665_M_DAC_R2_SM_R_SFT 0
/* SPO Amp Input and Gain Control (0x0048) */
#define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)
#define RT5665_M_DAC_L2_SPKOMIX_SFT 13
#define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
#define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
#define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)
#define RT5665_M_DAC_R2_SPKOMIX_SFT 9
#define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
#define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
/* MONOMIX Input and Gain Control (0x004b) */
#define RT5665_G_MONOVOL_MA (0x1 << 10)
#define RT5665_G_MONOVOL_MA_SFT 10
#define RT5665_M_MONOVOL_MA (0x1 << 9)
#define RT5665_M_MONOVOL_MA_SFT 9
#define RT5665_M_DAC_L2_MA (0x1 << 8)
#define RT5665_M_DAC_L2_MA_SFT 8
#define RT5665_M_BST3_MM (0x1 << 4)
#define RT5665_M_BST3_MM_SFT 4
#define RT5665_M_BST2_MM (0x1 << 3)
#define RT5665_M_BST2_MM_SFT 3
#define RT5665_M_BST1_MM (0x1 << 2)
#define RT5665_M_BST1_MM_SFT 2
#define RT5665_M_RECMIC2L_MM (0x1 << 1)
#define RT5665_M_RECMIC2L_MM_SFT 1
#define RT5665_M_DAC_L2_MM (0x1)
#define RT5665_M_DAC_L2_MM_SFT 0
/* Output Left Mixer Control 1 (0x004d) */
#define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
#define RT5665_G_BST3_OM_L_SFT 12
#define RT5665_G_BST2_OM_L_MASK (0x7 << 9)
#define RT5665_G_BST2_OM_L_SFT 9
#define RT5665_G_BST1_OM_L_MASK (0x7 << 6)
#define RT5665_G_BST1_OM_L_SFT 6
#define RT5665_G_IN_L_OM_L_MASK (0x7 << 3)
#define RT5665_G_IN_L_OM_L_SFT 3
#define RT5665_G_DAC_L2_OM_L_MASK (0x7 << 0)
#define RT5665_G_DAC_L2_OM_L_SFT 0
/* Output Left Mixer Input Control (0x004e) */
#define RT5665_M_BST3_OM_L (0x1 << 4)
#define RT5665_M_BST3_OM_L_SFT 4
#define RT5665_M_BST2_OM_L (0x1 << 3)
#define RT5665_M_BST2_OM_L_SFT 3
#define RT5665_M_BST1_OM_L (0x1 << 2)
#define RT5665_M_BST1_OM_L_SFT 2
#define RT5665_M_IN_L_OM_L (0x1 << 1)
#define RT5665_M_IN_L_OM_L_SFT 1
#define RT5665_M_DAC_L2_OM_L (0x1)
#define RT5665_M_DAC_L2_OM_L_SFT 0
/* Output Right Mixer Input Control (0x0050) */
#define RT5665_M_BST4_OM_R (0x1 << 4)
#define RT5665_M_BST4_OM_R_SFT 4
#define RT5665_M_BST3_OM_R (0x1 << 3)
#define RT5665_M_BST3_OM_R_SFT 3
#define RT5665_M_BST2_OM_R (0x1 << 2)
#define RT5665_M_BST2_OM_R_SFT 2
#define RT5665_M_IN_R_OM_R (0x1 << 1)
#define RT5665_M_IN_R_OM_R_SFT 1
#define RT5665_M_DAC_R2_OM_R (0x1)
#define RT5665_M_DAC_R2_OM_R_SFT 0
/* LOUT Mixer Control (0x0052) */
#define RT5665_M_DAC_L2_LM (0x1 << 15)
#define RT5665_M_DAC_L2_LM_SFT 15
#define RT5665_M_DAC_R2_LM (0x1 << 14)
#define RT5665_M_DAC_R2_LM_SFT 14
#define RT5665_M_OV_L_LM (0x1 << 13)
#define RT5665_M_OV_L_LM_SFT 13
#define RT5665_M_OV_R_LM (0x1 << 12)
#define RT5665_M_OV_R_LM_SFT 12
#define RT5665_LOUT_BST_SFT 11
#define RT5665_LOUT_DF (0x1 << 11)
#define RT5665_LOUT_DF_SFT 11
/* Power Management for Digital 1 (0x0061) */
#define RT5665_PWR_I2S1_1 (0x1 << 15)
#define RT5665_PWR_I2S1_1_BIT 15
#define RT5665_PWR_I2S1_2 (0x1 << 14)
#define RT5665_PWR_I2S1_2_BIT 14
#define RT5665_PWR_I2S2_1 (0x1 << 13)
#define RT5665_PWR_I2S2_1_BIT 13
#define RT5665_PWR_I2S2_2 (0x1 << 12)
#define RT5665_PWR_I2S2_2_BIT 12
#define RT5665_PWR_DAC_L1 (0x1 << 11)
#define RT5665_PWR_DAC_L1_BIT 11
#define RT5665_PWR_DAC_R1 (0x1 << 10)
#define RT5665_PWR_DAC_R1_BIT 10
#define RT5665_PWR_I2S3 (0x1 << 9)
#define RT5665_PWR_I2S3_BIT 9
#define RT5665_PWR_LDO (0x1 << 8)
#define RT5665_PWR_LDO_BIT 8
#define RT5665_PWR_DAC_L2 (0x1 << 7)
#define RT5665_PWR_DAC_L2_BIT 7
#define RT5665_PWR_DAC_R2 (0x1 << 6)
#define RT5665_PWR_DAC_R2_BIT 6
#define RT5665_PWR_ADC_L1 (0x1 << 4)
#define RT5665_PWR_ADC_L1_BIT 4
#define RT5665_PWR_ADC_R1 (0x1 << 3)
#define RT5665_PWR_ADC_R1_BIT 3
#define RT5665_PWR_ADC_L2 (0x1 << 2)
#define RT5665_PWR_ADC_L2_BIT 2
#define RT5665_PWR_ADC_R2 (0x1 << 1)
#define RT5665_PWR_ADC_R2_BIT 1
/* Power Management for Digital 2 (0x0062) */
#define RT5665_PWR_ADC_S1F (0x1 << 15)
#define RT5665_PWR_ADC_S1F_BIT 15
#define RT5665_PWR_ADC_S2F (0x1 << 14)
#define RT5665_PWR_ADC_S2F_BIT 14
#define RT5665_PWR_ADC_MF_L (0x1 << 13)
#define RT5665_PWR_ADC_MF_L_BIT 13
#define RT5665_PWR_ADC_MF_R (0x1 << 12)
#define RT5665_PWR_ADC_MF_R_BIT 12
#define RT5665_PWR_DAC_S2F (0x1 << 11)
#define RT5665_PWR_DAC_S2F_BIT 11
#define RT5665_PWR_DAC_S1F (0x1 << 10)
#define RT5665_PWR_DAC_S1F_BIT 10
#define RT5665_PWR_DAC_MF_L (0x1 << 9)
#define RT5665_PWR_DAC_MF_L_BIT 9
#define RT5665_PWR_DAC_MF_R (0x1 << 8)
#define RT5665_PWR_DAC_MF_R_BIT 8
#define RT5665_PWR_PDM1 (0x1 << 7)
#define RT5665_PWR_PDM1_BIT 7
/* Power Management for Analog 1 (0x0063) */
#define RT5665_PWR_VREF1 (0x1 << 15)
#define RT5665_PWR_VREF1_BIT 15
#define RT5665_PWR_FV1 (0x1 << 14)
#define RT5665_PWR_FV1_BIT 14
#define RT5665_PWR_VREF2 (0x1 << 13)
#define RT5665_PWR_VREF2_BIT 13
#define RT5665_PWR_FV2 (0x1 << 12)
#define RT5665_PWR_FV2_BIT 12
#define RT5665_PWR_VREF3 (0x1 << 11)
#define RT5665_PWR_VREF3_BIT 11
#define RT5665_PWR_FV3 (0x1 << 10)
#define RT5665_PWR_FV3_BIT 10
#define RT5665_PWR_MB (0x1 << 9)
#define RT5665_PWR_MB_BIT 9
#define RT5665_PWR_LM (0x1 << 8)
#define RT5665_PWR_LM_BIT 8
#define RT5665_PWR_BG (0x1 << 7)
#define RT5665_PWR_BG_BIT 7
#define RT5665_PWR_MA (0x1 << 6)
#define RT5665_PWR_MA_BIT 6
#define RT5665_PWR_HA_L (0x1 << 5)
#define RT5665_PWR_HA_L_BIT 5
#define RT5665_PWR_HA_R (0x1 << 4)
#define RT5665_PWR_HA_R_BIT 4
#define RT5665_HP_DRIVER_MASK (0x3 << 2)
#define RT5665_HP_DRIVER_1X (0x0 << 2)
#define RT5665_HP_DRIVER_3X (0x1 << 2)
#define RT5665_HP_DRIVER_5X (0x2 << 2)
#define RT5665_LDO1_DVO_MASK (0x3)
#define RT5665_LDO1_DVO_09 (0x0)
#define RT5665_LDO1_DVO_10 (0x1)
#define RT5665_LDO1_DVO_12 (0x2)
#define RT5665_LDO1_DVO_14 (0x3)
/* Power Management for Analog 2 (0x0064) */
#define RT5665_PWR_BST1 (0x1 << 15)
#define RT5665_PWR_BST1_BIT 15
#define RT5665_PWR_BST2 (0x1 << 14)
#define RT5665_PWR_BST2_BIT 14
#define RT5665_PWR_BST3 (0x1 << 13)
#define RT5665_PWR_BST3_BIT 13
#define RT5665_PWR_BST4 (0x1 << 12)
#define RT5665_PWR_BST4_BIT 12
#define RT5665_PWR_MB1 (0x1 << 11)
#define RT5665_PWR_MB1_PWR_DOWN (0x0 << 11)
#define RT5665_PWR_MB1_BIT 11
#define RT5665_PWR_MB2 (0x1 << 10)
#define RT5665_PWR_MB2_PWR_DOWN (0x0 << 10)
#define RT5665_PWR_MB2_BIT 10
#define RT5665_PWR_MB3 (0x1 << 9)
#define RT5665_PWR_MB3_BIT 9
#define RT5665_PWR_BST1_P (0x1 << 7)
#define RT5665_PWR_BST1_P_BIT 7
#define RT5665_PWR_BST2_P (0x1 << 6)
#define RT5665_PWR_BST2_P_BIT 6
#define RT5665_PWR_BST3_P (0x1 << 5)
#define RT5665_PWR_BST3_P_BIT 5
#define RT5665_PWR_BST4_P (0x1 << 4)
#define RT5665_PWR_BST4_P_BIT 4
#define RT5665_PWR_JD1 (0x1 << 3)
#define RT5665_PWR_JD1_BIT 3
#define RT5665_PWR_JD2 (0x1 << 2)
#define RT5665_PWR_JD2_BIT 2
#define RT5665_PWR_RM1_L (0x1 << 1)
#define RT5665_PWR_RM1_L_BIT 1
#define RT5665_PWR_RM1_R (0x1)
#define RT5665_PWR_RM1_R_BIT 0
/* Power Management for Analog 3 (0x0065) */
#define RT5665_PWR_CBJ (0x1 << 9)
#define RT5665_PWR_CBJ_BIT 9
#define RT5665_PWR_BST_L (0x1 << 8)
#define RT5665_PWR_BST_L_BIT 8
#define RT5665_PWR_BST_R (0x1 << 7)
#define RT5665_PWR_BST_R_BIT 7
#define RT5665_PWR_PLL (0x1 << 6)
#define RT5665_PWR_PLL_BIT 6
#define RT5665_PWR_LDO2 (0x1 << 2)
#define RT5665_PWR_LDO2_BIT 2
#define RT5665_PWR_SVD (0x1 << 1)
#define RT5665_PWR_SVD_BIT 1
/* Power Management for Mixer (0x0066) */
#define RT5665_PWR_RM2_L (0x1 << 15)
#define RT5665_PWR_RM2_L_BIT 15
#define RT5665_PWR_RM2_R (0x1 << 14)
#define RT5665_PWR_RM2_R_BIT 14
#define RT5665_PWR_OM_L (0x1 << 13)
#define RT5665_PWR_OM_L_BIT 13
#define RT5665_PWR_OM_R (0x1 << 12)
#define RT5665_PWR_OM_R_BIT 12
#define RT5665_PWR_MM (0x1 << 11)
#define RT5665_PWR_MM_BIT 11
#define RT5665_PWR_AEC_REF (0x1 << 6)
#define RT5665_PWR_AEC_REF_BIT 6
#define RT5665_PWR_STO1_DAC_L (0x1 << 5)
#define RT5665_PWR_STO1_DAC_L_BIT 5
#define RT5665_PWR_STO1_DAC_R (0x1 << 4)
#define RT5665_PWR_STO1_DAC_R_BIT 4
#define RT5665_PWR_MONO_DAC_L (0x1 << 3)
#define RT5665_PWR_MONO_DAC_L_BIT 3
#define RT5665_PWR_MONO_DAC_R (0x1 << 2)
#define RT5665_PWR_MONO_DAC_R_BIT 2
#define RT5665_PWR_STO2_DAC_L (0x1 << 1)
#define RT5665_PWR_STO2_DAC_L_BIT 1
#define RT5665_PWR_STO2_DAC_R (0x1)
#define RT5665_PWR_STO2_DAC_R_BIT 0
/* Power Management for Volume (0x0067) */
#define RT5665_PWR_OV_L (0x1 << 13)
#define RT5665_PWR_OV_L_BIT 13
#define RT5665_PWR_OV_R (0x1 << 12)
#define RT5665_PWR_OV_R_BIT 12
#define RT5665_PWR_IN_L (0x1 << 9)
#define RT5665_PWR_IN_L_BIT 9
#define RT5665_PWR_IN_R (0x1 << 8)
#define RT5665_PWR_IN_R_BIT 8
#define RT5665_PWR_MV (0x1 << 7)
#define RT5665_PWR_MV_BIT 7
#define RT5665_PWR_MIC_DET (0x1 << 5)
#define RT5665_PWR_MIC_DET_BIT 5
/* (0x006b) */
#define RT5665_SYS_CLK_DET 15
#define RT5665_HP_CLK_DET 14
#define RT5665_MONO_CLK_DET 13
#define RT5665_LOUT_CLK_DET 12
#define RT5665_POW_CLK_DET 0
/* Digital Microphone Control 1 (0x006e) */
#define RT5665_DMIC_1_EN_MASK (0x1 << 15)
#define RT5665_DMIC_1_EN_SFT 15
#define RT5665_DMIC_1_DIS (0x0 << 15)
#define RT5665_DMIC_1_EN (0x1 << 15)
#define RT5665_DMIC_2_EN_MASK (0x1 << 14)
#define RT5665_DMIC_2_EN_SFT 14
#define RT5665_DMIC_2_DIS (0x0 << 14)
#define RT5665_DMIC_2_EN (0x1 << 14)
#define RT5665_DMIC_2_DP_MASK (0x1 << 9)
#define RT5665_DMIC_2_DP_SFT 9
#define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9)
#define RT5665_DMIC_2_DP_IN2P (0x1 << 9)
#define RT5665_DMIC_CLK_MASK (0x7 << 5)
#define RT5665_DMIC_CLK_SFT 5
#define RT5665_DMIC_1_DP_MASK (0x1 << 1)
#define RT5665_DMIC_1_DP_SFT 1
#define RT5665_DMIC_1_DP_GPIO4 (0x0 << 1)
#define RT5665_DMIC_1_DP_IN2N (0x1 << 1)
/* Digital Microphone Control 1 (0x006f) */
#define RT5665_DMIC_2L_LH_MASK (0x1 << 3)
#define RT5665_DMIC_2L_LH_SFT 3
#define RT5665_DMIC_2L_LH_RISING (0x0 << 3)
#define RT5665_DMIC_2L_LH_FALLING (0x1 << 3)
#define RT5665_DMIC_2R_LH_MASK (0x1 << 2)
#define RT5665_DMIC_2R_LH_SFT 2
#define RT5665_DMIC_2R_LH_RISING (0x0 << 2)
#define RT5665_DMIC_2R_LH_FALLING (0x1 << 2)
#define RT5665_DMIC_1L_LH_MASK (0x1 << 1)
#define RT5665_DMIC_1L_LH_SFT 1
#define RT5665_DMIC_1L_LH_RISING (0x0 << 1)
#define RT5665_DMIC_1L_LH_FALLING (0x1 << 1)
#define RT5665_DMIC_1R_LH_MASK (0x1 << 0)
#define RT5665_DMIC_1R_LH_SFT 0
#define RT5665_DMIC_1R_LH_RISING (0x0)
#define RT5665_DMIC_1R_LH_FALLING (0x1)
/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
#define RT5665_I2S_MS_MASK (0x1 << 15)
#define RT5665_I2S_MS_SFT 15
#define RT5665_I2S_MS_M (0x0 << 15)
#define RT5665_I2S_MS_S (0x1 << 15)
#define RT5665_I2S_PIN_CFG_MASK (0x1 << 14)
#define RT5665_I2S_PIN_CFG_SFT 14
#define RT5665_I2S_CLK_SEL_MASK (0x1 << 11)
#define RT5665_I2S_CLK_SEL_SFT 11
#define RT5665_I2S_BP_MASK (0x1 << 8)
#define RT5665_I2S_BP_SFT 8
#define RT5665_I2S_BP_NOR (0x0 << 8)
#define RT5665_I2S_BP_INV (0x1 << 8)
#define RT5665_I2S_DL_MASK (0x3 << 4)
#define RT5665_I2S_DL_SFT 4
#define RT5665_I2S_DL_16 (0x0 << 4)
#define RT5665_I2S_DL_20 (0x1 << 4)
#define RT5665_I2S_DL_24 (0x2 << 4)
#define RT5665_I2S_DL_8 (0x3 << 4)
#define RT5665_I2S_DF_MASK (0x7)
#define RT5665_I2S_DF_SFT 0
#define RT5665_I2S_DF_I2S (0x0)
#define RT5665_I2S_DF_LEFT (0x1)
#define RT5665_I2S_DF_PCM_A (0x2)
#define RT5665_I2S_DF_PCM_B (0x3)
#define RT5665_I2S_DF_PCM_A_N (0x6)
#define RT5665_I2S_DF_PCM_B_N (0x7)
/* ADC/DAC Clock Control 1 (0x0073) */
#define RT5665_I2S_PD1_MASK (0x7 << 12)
#define RT5665_I2S_PD1_SFT 12
#define RT5665_I2S_PD1_1 (0x0 << 12)
#define RT5665_I2S_PD1_2 (0x1 << 12)
#define RT5665_I2S_PD1_3 (0x2 << 12)
#define RT5665_I2S_PD1_4 (0x3 << 12)
#define RT5665_I2S_PD1_6 (0x4 << 12)
#define RT5665_I2S_PD1_8 (0x5 << 12)
#define RT5665_I2S_PD1_12 (0x6 << 12)
#define RT5665_I2S_PD1_16 (0x7 << 12)
#define RT5665_I2S_M_PD2_MASK (0x7 << 8)
#define RT5665_I2S_M_PD2_SFT 8
#define RT5665_I2S_M_PD2_1 (0x0 << 8)
#define RT5665_I2S_M_PD2_2 (0x1 << 8)
#define RT5665_I2S_M_PD2_3 (0x2 << 8)
#define RT5665_I2S_M_PD2_4 (0x3 << 8)
#define RT5665_I2S_M_PD2_6 (0x4 << 8)
#define RT5665_I2S_M_PD2_8 (0x5 << 8)
#define RT5665_I2S_M_PD2_12 (0x6 << 8)
#define RT5665_I2S_M_PD2_16 (0x7 << 8)
#define RT5665_I2S_CLK_SRC_MASK (0x3 << 4)
#define RT5665_I2S_CLK_SRC_SFT 4
#define RT5665_I2S_CLK_SRC_MCLK (0x0 << 4)
#define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4)
#define RT5665_I2S_CLK_SRC_RCCLK (0x2 << 4)
#define RT5665_DAC_OSR_MASK (0x3 << 2)
#define RT5665_DAC_OSR_SFT 2
#define RT5665_DAC_OSR_128 (0x0 << 2)
#define RT5665_DAC_OSR_64 (0x1 << 2)
#define RT5665_DAC_OSR_32 (0x2 << 2)
#define RT5665_ADC_OSR_MASK (0x3)
#define RT5665_ADC_OSR_SFT 0
#define RT5665_ADC_OSR_128 (0x0)
#define RT5665_ADC_OSR_64 (0x1)
#define RT5665_ADC_OSR_32 (0x2)
/* ADC/DAC Clock Control 2 (0x0074) */
#define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
#define RT5665_I2S_BCLK_MS2_SFT 15
#define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)
#define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
#define RT5665_I2S_PD2_MASK (0x7 << 12)
#define RT5665_I2S_PD2_SFT 12
#define RT5665_I2S_PD2_1 (0x0 << 12)
#define RT5665_I2S_PD2_2 (0x1 << 12)
#define RT5665_I2S_PD2_3 (0x2 << 12)
#define RT5665_I2S_PD2_4 (0x3 << 12)
#define RT5665_I2S_PD2_6 (0x4 << 12)
#define RT5665_I2S_PD2_8 (0x5 << 12)
#define RT5665_I2S_PD2_12 (0x6 << 12)
#define RT5665_I2S_PD2_16 (0x7 << 12)
#define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11)
#define RT5665_I2S_BCLK_MS3_SFT 11
#define RT5665_I2S_BCLK_MS3_32 (0x0 << 11)
#define RT5665_I2S_BCLK_MS3_64 (0x1 << 11)
#define RT5665_I2S_PD3_MASK (0x7 << 8)
#define RT5665_I2S_PD3_SFT 8
#define RT5665_I2S_PD3_1 (0x0 << 8)
#define RT5665_I2S_PD3_2 (0x1 << 8)
#define RT5665_I2S_PD3_3 (0x2 << 8)
#define RT5665_I2S_PD3_4 (0x3 << 8)
#define RT5665_I2S_PD3_6 (0x4 << 8)
#define RT5665_I2S_PD3_8 (0x5 << 8)
#define RT5665_I2S_PD3_12 (0x6 << 8)
#define RT5665_I2S_PD3_16 (0x7 << 8)
#define RT5665_I2S_PD4_MASK (0x7 << 4)
#define RT5665_I2S_PD4_SFT 4
#define RT5665_I2S_PD4_1 (0x0 << 4)
#define RT5665_I2S_PD4_2 (0x1 << 4)
#define RT5665_I2S_PD4_3 (0x2 << 4)
#define RT5665_I2S_PD4_4 (0x3 << 4)
#define RT5665_I2S_PD4_6 (0x4 << 4)
#define RT5665_I2S_PD4_8 (0x5 << 4)
#define RT5665_I2S_PD4_12 (0x6 << 4)
#define RT5665_I2S_PD4_16 (0x7 << 4)
/* TDM control 1 (0x0078) */
#define RT5665_I2S1_MODE_MASK (0x1 << 15)
#define RT5665_I2S1_MODE_I2S (0x0 << 15)
#define RT5665_I2S1_MODE_TDM (0x1 << 15)
#define RT5665_TDM_IN_CH_MASK (0x3 << 10)
#define RT5665_TDM_IN_CH_2 (0x0 << 10)
#define RT5665_TDM_IN_CH_4 (0x1 << 10)
#define RT5665_TDM_IN_CH_6 (0x2 << 10)
#define RT5665_TDM_IN_CH_8 (0x3 << 10)
#define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
#define RT5665_TDM_OUT_CH_2 (0x0 << 8)
#define RT5665_TDM_OUT_CH_4 (0x1 << 8)
#define RT5665_TDM_OUT_CH_6 (0x2 << 8)
#define RT5665_TDM_OUT_CH_8 (0x3 << 8)
#define RT5665_TDM_IN_LEN_MASK (0x3 << 6)
#define RT5665_TDM_IN_LEN_16 (0x0 << 6)
#define RT5665_TDM_IN_LEN_20 (0x1 << 6)
#define RT5665_TDM_IN_LEN_24 (0x2 << 6)
#define RT5665_TDM_IN_LEN_32 (0x3 << 6)
#define RT5665_TDM_OUT_LEN_MASK (0x3 << 4)
#define RT5665_TDM_OUT_LEN_16 (0x0 << 4)
#define RT5665_TDM_OUT_LEN_20 (0x1 << 4)
#define RT5665_TDM_OUT_LEN_24 (0x2 << 4)
#define RT5665_TDM_OUT_LEN_32 (0x3 << 4)
/* TDM control 2 (0x0079) */
#define RT5665_I2S1_1_DS_ADC_SLOT01_SFT 14
#define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
#define RT5665_I2S1_1_DS_ADC_SLOT45_SFT 10
#define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
#define RT5665_I2S1_2_DS_ADC_SLOT01_SFT 6
#define RT5665_I2S1_2_DS_ADC_SLOT23_SFT 4
#define RT5665_I2S1_2_DS_ADC_SLOT45_SFT 2
#define RT5665_I2S1_2_DS_ADC_SLOT67_SFT 0
/* TDM control 3/4 (0x007a) (0x007b) */
#define RT5665_IF1_ADC1_SEL_SFT 10
#define RT5665_IF1_ADC2_SEL_SFT 9
#define RT5665_IF1_ADC3_SEL_SFT 8
#define RT5665_IF1_ADC4_SEL_SFT 7
#define RT5665_TDM_ADC_SEL_SFT 0
#define RT5665_TDM_ADC_CTRL_MASK (0x1f << 0)
#define RT5665_TDM_ADC_DATA_06 (0x6 << 0)
/* Global Clock Control (0x0080) */
#define RT5665_SCLK_SRC_MASK (0x3 << 14)
#define RT5665_SCLK_SRC_SFT 14
#define RT5665_SCLK_SRC_MCLK (0x0 << 14)
#define RT5665_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5665_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5665_PLL1_SRC_MASK (0x7 << 8)
#define RT5665_PLL1_SRC_SFT 8
#define RT5665_PLL1_SRC_MCLK (0x0 << 8)
#define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
#define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
#define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
#define RT5665_PLL1_PD_MASK (0x7 << 4)
#define RT5665_PLL1_PD_SFT 4
#define RT5665_PLL_INP_MAX 40000000
#define RT5665_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x0081) */
#define RT5665_PLL_N_MAX 0x001ff
#define RT5665_PLL_N_MASK (RT5665_PLL_N_MAX << 7)
#define RT5665_PLL_N_SFT 7
#define RT5665_PLL_K_MAX 0x001f
#define RT5665_PLL_K_MASK (RT5665_PLL_K_MAX)
#define RT5665_PLL_K_SFT 0
/* PLL M/N/K Code Control 2 (0x0082) */
#define RT5665_PLL_M_MAX 0x00f
#define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
#define RT5665_PLL_M_SFT 12
#define RT5665_PLL_M_BP (0x1 << 11)
#define RT5665_PLL_M_BP_SFT 11
#define RT5665_PLL_K_BP (0x1 << 10)
#define RT5665_PLL_K_BP_SFT 10
/* PLL tracking mode 1 (0x0083) */
#define RT5665_I2S3_ASRC_MASK (0x1 << 15)
#define RT5665_I2S3_ASRC_SFT 15
#define RT5665_I2S2_ASRC_MASK (0x1 << 14)
#define RT5665_I2S2_ASRC_SFT 14
#define RT5665_I2S1_ASRC_MASK (0x1 << 13)
#define RT5665_I2S1_ASRC_SFT 13
#define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
#define RT5665_DAC_STO1_ASRC_SFT 12
#define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11)
#define RT5665_DAC_STO2_ASRC_SFT 11
#define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10)
#define RT5665_DAC_MONO_L_ASRC_SFT 10
#define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)
#define RT5665_DAC_MONO_R_ASRC_SFT 9
#define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
#define RT5665_DMIC_STO1_ASRC_SFT 8
#define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7)
#define RT5665_DMIC_STO2_ASRC_SFT 7
#define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6)
#define RT5665_DMIC_MONO_L_ASRC_SFT 6
#define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5)
#define RT5665_DMIC_MONO_R_ASRC_SFT 5
#define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4)
#define RT5665_ADC_STO1_ASRC_SFT 4
#define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3)
#define RT5665_ADC_STO2_ASRC_SFT 3
#define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2)
#define RT5665_ADC_MONO_L_ASRC_SFT 2
#define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1)
#define RT5665_ADC_MONO_R_ASRC_SFT 1
/* PLL tracking mode 2 (0x0084)*/
#define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
#define RT5665_DA_STO1_CLK_SEL_SFT 12
#define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
#define RT5665_DA_STO2_CLK_SEL_SFT 8
#define RT5665_DA_MONOL_CLK_SEL_MASK (0x7 << 4)
#define RT5665_DA_MONOL_CLK_SEL_SFT 4
#define RT5665_DA_MONOR_CLK_SEL_MASK (0x7)
#define RT5665_DA_MONOR_CLK_SEL_SFT 0
/* PLL tracking mode 3 (0x0085)*/
#define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
#define RT5665_AD_STO1_CLK_SEL_SFT 12
#define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
#define RT5665_AD_STO2_CLK_SEL_SFT 8
#define RT5665_AD_MONOL_CLK_SEL_MASK (0x7 << 4)
#define RT5665_AD_MONOL_CLK_SEL_SFT 4
#define RT5665_AD_MONOR_CLK_SEL_MASK (0x7)
#define RT5665_AD_MONOR_CLK_SEL_SFT 0
/* ASRC Control 4 (0x0086) */
#define RT5665_I2S1_RATE_MASK (0xf << 12)
#define RT5665_I2S1_RATE_SFT 12
#define RT5665_I2S2_RATE_MASK (0xf << 8)
#define RT5665_I2S2_RATE_SFT 8
#define RT5665_I2S3_RATE_MASK (0xf << 4)
#define RT5665_I2S3_RATE_SFT 4
/* Depop Mode Control 1 (0x008e) */
#define RT5665_PUMP_EN (0x1 << 3)
/* Depop Mode Control 2 (0x8f) */
#define RT5665_DEPOP_MASK (0x1 << 13)
#define RT5665_DEPOP_SFT 13
#define RT5665_DEPOP_AUTO (0x0 << 13)
#define RT5665_DEPOP_MAN (0x1 << 13)
#define RT5665_RAMP_MASK (0x1 << 12)
#define RT5665_RAMP_SFT 12
#define RT5665_RAMP_DIS (0x0 << 12)
#define RT5665_RAMP_EN (0x1 << 12)
#define RT5665_BPS_MASK (0x1 << 11)
#define RT5665_BPS_SFT 11
#define RT5665_BPS_DIS (0x0 << 11)
#define RT5665_BPS_EN (0x1 << 11)
#define RT5665_FAST_UPDN_MASK (0x1 << 10)
#define RT5665_FAST_UPDN_SFT 10
#define RT5665_FAST_UPDN_DIS (0x0 << 10)
#define RT5665_FAST_UPDN_EN (0x1 << 10)
#define RT5665_MRES_MASK (0x3 << 8)
#define RT5665_MRES_SFT 8
#define RT5665_MRES_15MO (0x0 << 8)
#define RT5665_MRES_25MO (0x1 << 8)
#define RT5665_MRES_35MO (0x2 << 8)
#define RT5665_MRES_45MO (0x3 << 8)
#define RT5665_VLO_MASK (0x1 << 7)
#define RT5665_VLO_SFT 7
#define RT5665_VLO_3V (0x0 << 7)
#define RT5665_VLO_32V (0x1 << 7)
#define RT5665_DIG_DP_MASK (0x1 << 6)
#define RT5665_DIG_DP_SFT 6
#define RT5665_DIG_DP_DIS (0x0 << 6)
#define RT5665_DIG_DP_EN (0x1 << 6)
#define RT5665_DP_TH_MASK (0x3 << 4)
#define RT5665_DP_TH_SFT 4
/* Depop Mode Control 3 (0x90) */
#define RT5665_CP_SYS_MASK (0x7 << 12)
#define RT5665_CP_SYS_SFT 12
#define RT5665_CP_FQ1_MASK (0x7 << 8)
#define RT5665_CP_FQ1_SFT 8
#define RT5665_CP_FQ2_MASK (0x7 << 4)
#define RT5665_CP_FQ2_SFT 4
#define RT5665_CP_FQ3_MASK (0x7)
#define RT5665_CP_FQ3_SFT 0
#define RT5665_CP_FQ_1_5_KHZ 0
#define RT5665_CP_FQ_3_KHZ 1
#define RT5665_CP_FQ_6_KHZ 2
#define RT5665_CP_FQ_12_KHZ 3
#define RT5665_CP_FQ_24_KHZ 4
#define RT5665_CP_FQ_48_KHZ 5
#define RT5665_CP_FQ_96_KHZ 6
#define RT5665_CP_FQ_192_KHZ 7
/* HPOUT charge pump 1 (0x0091) */
#define RT5665_OSW_L_MASK (0x1 << 11)
#define RT5665_OSW_L_SFT 11
#define RT5665_OSW_L_DIS (0x0 << 11)
#define RT5665_OSW_L_EN (0x1 << 11)
#define RT5665_OSW_R_MASK (0x1 << 10)
#define RT5665_OSW_R_SFT 10
#define RT5665_OSW_R_DIS (0x0 << 10)
#define RT5665_OSW_R_EN (0x1 << 10)
#define RT5665_PM_HP_MASK (0x3 << 8)
#define RT5665_PM_HP_SFT 8
#define RT5665_PM_HP_LV (0x0 << 8)
#define RT5665_PM_HP_MV (0x1 << 8)
#define RT5665_PM_HP_HV (0x2 << 8)
#define RT5665_IB_HP_MASK (0x3 << 6)
#define RT5665_IB_HP_SFT 6
#define RT5665_IB_HP_125IL (0x0 << 6)
#define RT5665_IB_HP_25IL (0x1 << 6)
#define RT5665_IB_HP_5IL (0x2 << 6)
#define RT5665_IB_HP_1IL (0x3 << 6)
/* PV detection and SPK gain control (0x92) */
#define RT5665_PVDD_DET_MASK (0x1 << 15)
#define RT5665_PVDD_DET_SFT 15
#define RT5665_PVDD_DET_DIS (0x0 << 15)
#define RT5665_PVDD_DET_EN (0x1 << 15)
#define RT5665_SPK_AG_MASK (0x1 << 14)
#define RT5665_SPK_AG_SFT 14
#define RT5665_SPK_AG_DIS (0x0 << 14)
#define RT5665_SPK_AG_EN (0x1 << 14)
/* Micbias Control1 (0x93) */
#define RT5665_MIC1_BS_MASK (0x1 << 15)
#define RT5665_MIC1_BS_SFT 15
#define RT5665_MIC1_BS_9AV (0x0 << 15)
#define RT5665_MIC1_BS_75AV (0x1 << 15)
#define RT5665_MIC2_BS_MASK (0x1 << 14)
#define RT5665_MIC2_BS_SFT 14
#define RT5665_MIC2_BS_9AV (0x0 << 14)
#define RT5665_MIC2_BS_75AV (0x1 << 14)
#define RT5665_MIC1_CLK_MASK (0x1 << 13)
#define RT5665_MIC1_CLK_SFT 13
#define RT5665_MIC1_CLK_DIS (0x0 << 13)
#define RT5665_MIC1_CLK_EN (0x1 << 13)
#define RT5665_MIC2_CLK_MASK (0x1 << 12)
#define RT5665_MIC2_CLK_SFT 12
#define RT5665_MIC2_CLK_DIS (0x0 << 12)
#define RT5665_MIC2_CLK_EN (0x1 << 12)
#define RT5665_MIC1_OVCD_MASK (0x1 << 11)
#define RT5665_MIC1_OVCD_SFT 11
#define RT5665_MIC1_OVCD_DIS (0x0 << 11)
#define RT5665_MIC1_OVCD_EN (0x1 << 11)
#define RT5665_MIC1_OVTH_MASK (0x3 << 9)
#define RT5665_MIC1_OVTH_SFT 9
#define RT5665_MIC1_OVTH_600UA (0x0 << 9)
#define RT5665_MIC1_OVTH_1500UA (0x1 << 9)
#define RT5665_MIC1_OVTH_2000UA (0x2 << 9)
#define RT5665_MIC2_OVCD_MASK (0x1 << 8)
#define RT5665_MIC2_OVCD_SFT 8
#define RT5665_MIC2_OVCD_DIS (0x0 << 8)
#define RT5665_MIC2_OVCD_EN (0x1 << 8)
#define RT5665_MIC2_OVTH_MASK (0x3 << 6)
#define RT5665_MIC2_OVTH_SFT 6
#define RT5665_MIC2_OVTH_600UA (0x0 << 6)
#define RT5665_MIC2_OVTH_1500UA (0x1 << 6)
#define RT5665_MIC2_OVTH_2000UA (0x2 << 6)
#define RT5665_PWR_MB_MASK (0x1 << 5)
#define RT5665_PWR_MB_SFT 5
#define RT5665_PWR_MB_PD (0x0 << 5)
#define RT5665_PWR_MB_PU (0x1 << 5)
/* Micbias Control2 (0x94) */
#define RT5665_PWR_CLK25M_MASK (0x1 << 9)
#define RT5665_PWR_CLK25M_SFT 9
#define RT5665_PWR_CLK25M_PD (0x0 << 9)
#define RT5665_PWR_CLK25M_PU (0x1 << 9)
#define RT5665_PWR_CLK1M_MASK (0x1 << 8)
#define RT5665_PWR_CLK1M_SFT 8
#define RT5665_PWR_CLK1M_PD (0x0 << 8)
#define RT5665_PWR_CLK1M_PU (0x1 << 8)
/* EQ Control 1 (0x00b0) */
#define RT5665_EQ_SRC_DAC (0x0 << 15)
#define RT5665_EQ_SRC_ADC (0x1 << 15)
#define RT5665_EQ_UPD (0x1 << 14)
#define RT5665_EQ_UPD_BIT 14
#define RT5665_EQ_CD_MASK (0x1 << 13)
#define RT5665_EQ_CD_SFT 13
#define RT5665_EQ_CD_DIS (0x0 << 13)
#define RT5665_EQ_CD_EN (0x1 << 13)
#define RT5665_EQ_DITH_MASK (0x3 << 8)
#define RT5665_EQ_DITH_SFT 8
#define RT5665_EQ_DITH_NOR (0x0 << 8)
#define RT5665_EQ_DITH_LSB (0x1 << 8)
#define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
#define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
/* IRQ Control 1 (0x00b7) */
#define RT5665_JD1_1_EN_MASK (0x1 << 15)
#define RT5665_JD1_1_EN_SFT 15
#define RT5665_JD1_1_DIS (0x0 << 15)
#define RT5665_JD1_1_EN (0x1 << 15)
#define RT5665_JD1_2_EN_MASK (0x1 << 12)
#define RT5665_JD1_2_EN_SFT 12
#define RT5665_JD1_2_DIS (0x0 << 12)
#define RT5665_JD1_2_EN (0x1 << 12)
/* IRQ Control 2 (0x00b8) */
#define RT5665_IL_IRQ_MASK (0x1 << 6)
#define RT5665_IL_IRQ_DIS (0x0 << 6)
#define RT5665_IL_IRQ_EN (0x1 << 6)
/* IRQ Control 5 (0x00ba) */
#define RT5665_IRQ_JD_EN (0x1 << 3)
#define RT5665_IRQ_JD_EN_SFT 3
/* GPIO Control 1 (0x00c0) */
#define RT5665_GP1_PIN_MASK (0x1 << 15)
#define RT5665_GP1_PIN_SFT 15
#define RT5665_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5665_GP1_PIN_IRQ (0x1 << 15)
#define RT5665_GP2_PIN_MASK (0x3 << 13)
#define RT5665_GP2_PIN_SFT 13
#define RT5665_GP2_PIN_GPIO2 (0x0 << 13)
#define RT5665_GP2_PIN_BCLK2 (0x1 << 13)
#define RT5665_GP2_PIN_PDM_SCL (0x2 << 13)
#define RT5665_GP3_PIN_MASK (0x3 << 11)
#define RT5665_GP3_PIN_SFT 11
#define RT5665_GP3_PIN_GPIO3 (0x0 << 11)
#define RT5665_GP3_PIN_LRCK2 (0x1 << 11)
#define RT5665_GP3_PIN_PDM_SDA (0x2 << 11)
#define RT5665_GP4_PIN_MASK (0x3 << 9)
#define RT5665_GP4_PIN_SFT 9
#define RT5665_GP4_PIN_GPIO4 (0x0 << 9)
#define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)
#define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9)
#define RT5665_GP5_PIN_MASK (0x3 << 7)
#define RT5665_GP5_PIN_SFT 7
#define RT5665_GP5_PIN_GPIO5 (0x0 << 7)
#define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7)
#define RT5665_GP5_PIN_DMIC2_SDA (0x2 << 7)
#define RT5665_GP6_PIN_MASK (0x3 << 5)
#define RT5665_GP6_PIN_SFT 5
#define RT5665_GP6_PIN_GPIO6 (0x0 << 5)
#define RT5665_GP6_PIN_BCLK3 (0x0 << 5)
#define RT5665_GP6_PIN_PDM_SCL (0x1 << 5)
#define RT5665_GP7_PIN_MASK (0x3 << 3)
#define RT5665_GP7_PIN_SFT 3
#define RT5665_GP7_PIN_GPIO7 (0x0 << 3)
#define RT5665_GP7_PIN_LRCK3 (0x1 << 3)
#define RT5665_GP7_PIN_PDM_SDA (0x2 << 3)
#define RT5665_GP8_PIN_MASK (0x3 << 1)
#define RT5665_GP8_PIN_SFT 1
#define RT5665_GP8_PIN_GPIO8 (0x0 << 1)
#define RT5665_GP8_PIN_DACDAT3 (0x1 << 1)
#define RT5665_GP8_PIN_DMIC2_SCL (0x2 << 1)
#define RT5665_GP8_PIN_DACDAT2_2 (0x3 << 1)
/* GPIO Control 2 (0x00c1)*/
#define RT5665_GP9_PIN_MASK (0x3 << 14)
#define RT5665_GP9_PIN_SFT 14
#define RT5665_GP9_PIN_GPIO9 (0x0 << 14)
#define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14)
#define RT5665_GP9_PIN_DMIC1_SCL (0x2 << 14)
#define RT5665_GP9_PIN_ADCDAT2_2 (0x3 << 14)
#define RT5665_GP10_PIN_MASK (0x3 << 12)
#define RT5665_GP10_PIN_SFT 12
#define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
#define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
#define RT5665_GP10_PIN_LPD (0x2 << 12)
#define RT5665_GP1_PF_MASK (0x1 << 11)
#define RT5665_GP1_PF_IN (0x0 << 11)
#define RT5665_GP1_PF_OUT (0x1 << 11)
#define RT5665_GP1_OUT_MASK (0x1 << 10)
#define RT5665_GP1_OUT_H (0x0 << 10)
#define RT5665_GP1_OUT_L (0x1 << 10)
#define RT5665_GP2_PF_MASK (0x1 << 9)
#define RT5665_GP2_PF_IN (0x0 << 9)
#define RT5665_GP2_PF_OUT (0x1 << 9)
#define RT5665_GP2_OUT_MASK (0x1 << 8)
#define RT5665_GP2_OUT_H (0x0 << 8)
#define RT5665_GP2_OUT_L (0x1 << 8)
#define RT5665_GP3_PF_MASK (0x1 << 7)
#define RT5665_GP3_PF_IN (0x0 << 7)
#define RT5665_GP3_PF_OUT (0x1 << 7)
#define RT5665_GP3_OUT_MASK (0x1 << 6)
#define RT5665_GP3_OUT_H (0x0 << 6)
#define RT5665_GP3_OUT_L (0x1 << 6)
#define RT5665_GP4_PF_MASK (0x1 << 5)
#define RT5665_GP4_PF_IN (0x0 << 5)
#define RT5665_GP4_PF_OUT (0x1 << 5)
#define RT5665_GP4_OUT_MASK (0x1 << 4)
#define RT5665_GP4_OUT_H (0x0 << 4)
#define RT5665_GP4_OUT_L (0x1 << 4)
#define RT5665_GP5_PF_MASK (0x1 << 3)
#define RT5665_GP5_PF_IN (0x0 << 3)
#define RT5665_GP5_PF_OUT (0x1 << 3)
#define RT5665_GP5_OUT_MASK (0x1 << 2)
#define RT5665_GP5_OUT_H (0x0 << 2)
#define RT5665_GP5_OUT_L (0x1 << 2)
#define RT5665_GP6_PF_MASK (0x1 << 1)
#define RT5665_GP6_PF_IN (0x0 << 1)
#define RT5665_GP6_PF_OUT (0x1 << 1)
#define RT5665_GP6_OUT_MASK (0x1)
#define RT5665_GP6_OUT_H (0x0)
#define RT5665_GP6_OUT_L (0x1)
/* GPIO Control 3 (0x00c2) */
#define RT5665_GP7_PF_MASK (0x1 << 15)
#define RT5665_GP7_PF_IN (0x0 << 15)
#define RT5665_GP7_PF_OUT (0x1 << 15)
#define RT5665_GP7_OUT_MASK (0x1 << 14)
#define RT5665_GP7_OUT_H (0x0 << 14)
#define RT5665_GP7_OUT_L (0x1 << 14)
#define RT5665_GP8_PF_MASK (0x1 << 13)
#define RT5665_GP8_PF_IN (0x0 << 13)
#define RT5665_GP8_PF_OUT (0x1 << 13)
#define RT5665_GP8_OUT_MASK (0x1 << 12)
#define RT5665_GP8_OUT_H (0x0 << 12)
#define RT5665_GP8_OUT_L (0x1 << 12)
#define RT5665_GP9_PF_MASK (0x1 << 11)
#define RT5665_GP9_PF_IN (0x0 << 11)
#define RT5665_GP9_PF_OUT (0x1 << 11)
#define RT5665_GP9_OUT_MASK (0x1 << 10)
#define RT5665_GP9_OUT_H (0x0 << 10)
#define RT5665_GP9_OUT_L (0x1 << 10)
#define RT5665_GP10_PF_MASK (0x1 << 9)
#define RT5665_GP10_PF_IN (0x0 << 9)
#define RT5665_GP10_PF_OUT (0x1 << 9)
#define RT5665_GP10_OUT_MASK (0x1 << 8)
#define RT5665_GP10_OUT_H (0x0 << 8)
#define RT5665_GP10_OUT_L (0x1 << 8)
#define RT5665_GP11_PF_MASK (0x1 << 7)
#define RT5665_GP11_PF_IN (0x0 << 7)
#define RT5665_GP11_PF_OUT (0x1 << 7)
#define RT5665_GP11_OUT_MASK (0x1 << 6)
#define RT5665_GP11_OUT_H (0x0 << 6)
#define RT5665_GP11_OUT_L (0x1 << 6)
/* Soft volume and zero cross control 1 (0x00d9) */
#define RT5665_SV_MASK (0x1 << 15)
#define RT5665_SV_SFT 15
#define RT5665_SV_DIS (0x0 << 15)
#define RT5665_SV_EN (0x1 << 15)
#define RT5665_OUT_SV_MASK (0x1 << 13)
#define RT5665_OUT_SV_SFT 13
#define RT5665_OUT_SV_DIS (0x0 << 13)
#define RT5665_OUT_SV_EN (0x1 << 13)
#define RT5665_HP_SV_MASK (0x1 << 12)
#define RT5665_HP_SV_SFT 12
#define RT5665_HP_SV_DIS (0x0 << 12)
#define RT5665_HP_SV_EN (0x1 << 12)
#define RT5665_ZCD_DIG_MASK (0x1 << 11)
#define RT5665_ZCD_DIG_SFT 11
#define RT5665_ZCD_DIG_DIS (0x0 << 11)
#define RT5665_ZCD_DIG_EN (0x1 << 11)
#define RT5665_ZCD_MASK (0x1 << 10)
#define RT5665_ZCD_SFT 10
#define RT5665_ZCD_PD (0x0 << 10)
#define RT5665_ZCD_PU (0x1 << 10)
#define RT5665_SV_DLY_MASK (0xf)
#define RT5665_SV_DLY_SFT 0
/* Soft volume and zero cross control 2 (0x00da) */
#define RT5665_ZCD_HP_MASK (0x1 << 15)
#define RT5665_ZCD_HP_SFT 15
#define RT5665_ZCD_HP_DIS (0x0 << 15)
#define RT5665_ZCD_HP_EN (0x1 << 15)
/* 4 Button Inline Command Control 2 (0x00e0) */
#define RT5665_4BTN_IL_MASK (0x1 << 15)
#define RT5665_4BTN_IL_EN (0x1 << 15)
#define RT5665_4BTN_IL_DIS (0x0 << 15)
#define RT5665_4BTN_IL_RST_MASK (0x1 << 14)
#define RT5665_4BTN_IL_NOR (0x1 << 14)
#define RT5665_4BTN_IL_RST (0x0 << 14)
/* Analog JD Control 1 (0x00f0) */
#define RT5665_JD1_MODE_MASK (0x3 << 0)
#define RT5665_JD1_MODE_0 (0x0 << 0)
#define RT5665_JD1_MODE_1 (0x1 << 0)
#define RT5665_JD1_MODE_2 (0x2 << 0)
/* Jack Detect Control 3 (0x00f8) */
#define RT5665_JD_TRI_HPO_SEL_MASK (0x7)
#define RT5665_JD_TRI_HPO_SEL_SFT (0)
#define RT5665_JD_HPO_GPIO_JD1 (0x0)
#define RT5665_JD_HPO_JD1_1 (0x1)
#define RT5665_JD_HPO_JD1_2 (0x2)
#define RT5665_JD_HPO_JD2 (0x3)
#define RT5665_JD_HPO_GPIO_JD2 (0x4)
#define RT5665_JD_HPO_JD3 (0x5)
#define RT5665_JD_HPO_JD_D (0x6)
/* Digital Misc Control (0x00fa) */
#define RT5665_AM_MASK (0x1 << 7)
#define RT5665_AM_EN (0x1 << 7)
#define RT5665_AM_DIS (0x1 << 7)
#define RT5665_DIG_GATE_CTRL 0x1
#define RT5665_DIG_GATE_CTRL_SFT (0)
/* Chopper and Clock control for ADC (0x011c)*/
#define RT5665_M_RF_DIG_MASK (0x1 << 12)
#define RT5665_M_RF_DIG_SFT 12
#define RT5665_M_RI_DIG (0x1 << 11)
/* Chopper and Clock control for DAC (0x013a)*/
#define RT5665_CKXEN_DAC1_MASK (0x1 << 13)
#define RT5665_CKXEN_DAC1_SFT 13
#define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
#define RT5665_CKGEN_DAC1_SFT 12
#define RT5665_CKXEN_DAC2_MASK (0x1 << 5)
#define RT5665_CKXEN_DAC2_SFT 5
#define RT5665_CKGEN_DAC2_MASK (0x1 << 4)
#define RT5665_CKGEN_DAC2_SFT 4
/* Chopper and Clock control for ADC (0x013b)*/
#define RT5665_CKXEN_ADC1_MASK (0x1 << 13)
#define RT5665_CKXEN_ADC1_SFT 13
#define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
#define RT5665_CKGEN_ADC1_SFT 12
#define RT5665_CKXEN_ADC2_MASK (0x1 << 5)
#define RT5665_CKXEN_ADC2_SFT 5
#define RT5665_CKGEN_ADC2_MASK (0x1 << 4)
#define RT5665_CKGEN_ADC2_SFT 4
/* Volume test (0x013f)*/
#define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
#define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
#define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)
/* Test Mode Control 1 (0x0145) */
#define RT5665_AD2DA_LB_MASK (0x1 << 9)
#define RT5665_AD2DA_LB_SFT 9
/* Stereo Noise Gate Control 1 (0x0160) */
#define RT5665_NG2_EN_MASK (0x1 << 15)
#define RT5665_NG2_EN (0x1 << 15)
#define RT5665_NG2_DIS (0x0 << 15)
/* Stereo1 DAC Silence Detection Control (0x0190) */
#define RT5665_DEB_STO_DAC_MASK (0x7 << 4)
#define RT5665_DEB_80_MS (0x0 << 4)
/* SAR ADC Inline Command Control 1 (0x0210) */
#define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
#define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
#define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)
#define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14)
#define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14)
#define RT5665_SAR_BUTDET_POW_NORM (0x0 << 14)
#define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)
#define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)
#define RT5665_SAR_BUTDET_RST (0x0 << 13)
#define RT5665_SAR_POW_MASK (0x1 << 12)
#define RT5665_SAR_POW_EN (0x1 << 12)
#define RT5665_SAR_POW_DIS (0x0 << 12)
#define RT5665_SAR_RST_MASK (0x1 << 11)
#define RT5665_SAR_RST_NORMAL (0x1 << 11)
#define RT5665_SAR_RST (0x0 << 11)
#define RT5665_SAR_BYPASS_MASK (0x1 << 10)
#define RT5665_SAR_BYPASS_EN (0x1 << 10)
#define RT5665_SAR_BYPASS_DIS (0x0 << 10)
#define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)
#define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)
#define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9)
#define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
#define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
#define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)
#define RT5665_SAR_SEL_MODE_MASK (0x1 << 7)
#define RT5665_SAR_SEL_MODE_CMP (0x1 << 7)
#define RT5665_SAR_SEL_MODE_ADC (0x0 << 7)
#define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
#define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
#define RT5665_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
#define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4)
#define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
#define RT5665_SAR_SEL_SIGNAL_MANU (0x0 << 4)
/* System Clock Source */
enum {
RT5665_SCLK_S_MCLK,
RT5665_SCLK_S_PLL1,
RT5665_SCLK_S_RCCLK,
};
/* PLL1 Source */
enum {
RT5665_PLL1_S_MCLK,
RT5665_PLL1_S_BCLK1,
RT5665_PLL1_S_BCLK2,
RT5665_PLL1_S_BCLK3,
RT5665_PLL1_S_BCLK4,
};
enum {
RT5665_AIF1_1,
RT5665_AIF1_2,
RT5665_AIF2_1,
RT5665_AIF2_2,
RT5665_AIF3,
RT5665_AIFS
};
enum {
CODEC_5665,
CODEC_5666,
CODEC_5668,
};
/* filter mask */
enum {
RT5665_DA_STEREO1_FILTER = 0x1,
RT5665_DA_STEREO2_FILTER = (0x1 << 1),
RT5665_DA_MONO_L_FILTER = (0x1 << 2),
RT5665_DA_MONO_R_FILTER = (0x1 << 3),
RT5665_AD_STEREO1_FILTER = (0x1 << 4),
RT5665_AD_STEREO2_FILTER = (0x1 << 5),
RT5665_AD_MONO_L_FILTER = (0x1 << 6),
RT5665_AD_MONO_R_FILTER = (0x1 << 7),
};
enum {
RT5665_CLK_SEL_SYS,
RT5665_CLK_SEL_I2S1_ASRC,
RT5665_CLK_SEL_I2S2_ASRC,
RT5665_CLK_SEL_I2S3_ASRC,
RT5665_CLK_SEL_SYS2,
RT5665_CLK_SEL_SYS3,
RT5665_CLK_SEL_SYS4,
};
int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
unsigned int filter_mask, unsigned int clk_src);
int rt5665_set_jack_detect(struct snd_soc_codec *codec,
struct snd_soc_jack *hs_jack);
#endif /* __RT5665_H__ */
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