Commit b4183e30 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie

drm/radeon/kms: fix vram start calculation on ontario (v2)

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent ca9693a1
...@@ -1134,6 +1134,12 @@ static void evergreen_mc_program(struct radeon_device *rdev) ...@@ -1134,6 +1134,12 @@ static void evergreen_mc_program(struct radeon_device *rdev)
rdev->mc.vram_end >> 12); rdev->mc.vram_end >> 12);
} }
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
if (rdev->flags & RADEON_IS_IGP) {
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
WREG32(MC_FUS_VM_FB_OFFSET, tmp);
}
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
WREG32(MC_VM_FB_LOCATION, tmp); WREG32(MC_VM_FB_LOCATION, tmp);
......
...@@ -202,6 +202,7 @@ ...@@ -202,6 +202,7 @@
#define MC_VM_AGP_BOT 0x202C #define MC_VM_AGP_BOT 0x202C
#define MC_VM_AGP_BASE 0x2030 #define MC_VM_AGP_BASE 0x2030
#define MC_VM_FB_LOCATION 0x2024 #define MC_VM_FB_LOCATION 0x2024
#define MC_FUS_VM_FB_OFFSET 0x2898
#define MC_VM_MB_L1_TLB0_CNTL 0x2234 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
#define MC_VM_MB_L1_TLB1_CNTL 0x2238 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
#define MC_VM_MB_L1_TLB2_CNTL 0x223C #define MC_VM_MB_L1_TLB2_CNTL 0x223C
......
...@@ -271,12 +271,6 @@ static void rv770_mc_program(struct radeon_device *rdev) ...@@ -271,12 +271,6 @@ static void rv770_mc_program(struct radeon_device *rdev)
rdev->mc.vram_end >> 12); rdev->mc.vram_end >> 12);
} }
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
if (rdev->flags & RADEON_IS_IGP) {
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
WREG32(MC_FUS_VM_FB_OFFSET, tmp);
}
tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
WREG32(MC_VM_FB_LOCATION, tmp); WREG32(MC_VM_FB_LOCATION, tmp);
...@@ -1074,12 +1068,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) ...@@ -1074,12 +1068,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
mc->mc_vram_size >> 20, mc->vram_start, mc->mc_vram_size >> 20, mc->vram_start,
mc->vram_end, mc->real_vram_size >> 20); mc->vram_end, mc->real_vram_size >> 20);
} else { } else {
u64 base = 0; radeon_vram_location(rdev, &rdev->mc, 0);
if (rdev->flags & RADEON_IS_IGP) {
base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
base |= RREG32(MC_FUS_VM_FB_OFFSET) & 0x00F00000;
}
radeon_vram_location(rdev, &rdev->mc, base);
rdev->mc.gtt_base_align = 0; rdev->mc.gtt_base_align = 0;
radeon_gtt_location(rdev, mc); radeon_gtt_location(rdev, mc);
} }
......
...@@ -158,7 +158,6 @@ ...@@ -158,7 +158,6 @@
#define MC_VM_AGP_BOT 0x202C #define MC_VM_AGP_BOT 0x202C
#define MC_VM_AGP_BASE 0x2030 #define MC_VM_AGP_BASE 0x2030
#define MC_VM_FB_LOCATION 0x2024 #define MC_VM_FB_LOCATION 0x2024
#define MC_FUS_VM_FB_OFFSET 0x2898
#define MC_VM_MB_L1_TLB0_CNTL 0x2234 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
#define MC_VM_MB_L1_TLB1_CNTL 0x2238 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
#define MC_VM_MB_L1_TLB2_CNTL 0x223C #define MC_VM_MB_L1_TLB2_CNTL 0x223C
......
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