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Commit b4a993e7 authored by Matthew Wilcox's avatar Matthew Wilcox Committed by Linus Torvalds
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[PATCH] Update PA-RISC IOMMU code 

 - The pdc_io_reset_devices() call necessary for USB keyboard kills the
   serial console.  Use a test that seems to work for both.
 - Don't bounce >4G buffers on machines with IOMMU
 - Remove ASSERT code and cleanup iomem * related warnings
 - Fix comment that was pointing to the old file location
 - Expand comment about PDC reset to describe broken GFX+USB console at
   powerup by direct linux to serial console
 - Fix all ioremap abuse noticed by CONFIG_DEBUG_IOREMAP on an N4000
 - Remove casts from "READ_REG" and "WRITE_REG" macro
 - Set D4 and DD bits in IOC_CTRL
 - Allow all memory in machine to be in-flight DMA at once, up to 4GB
Signed-off-by: default avatarGrant Grundler <grundler@parisc-linux.org>
Signed-off-by: default avatarMatthew Wilcox <willy@parisc-linux.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent d8f08b67
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Showing with 141 additions and 189 deletions
drivers/parisc/sba_iommu.c
View file @ b4a993e7
......@@ -58,7 +58,6 @@ extern struct proc_dir_entry * proc_mckinley_root;
** Don't even think about messing with it unless you have
** plenty of 710's to sacrifice to the computer gods. :^)
*/
#undef DEBUG_SBA_ASSERT
#undef DEBUG_SBA_INIT
#undef DEBUG_SBA_RUN
#undef DEBUG_SBA_RUN_SG
......@@ -92,19 +91,6 @@ extern struct proc_dir_entry * proc_mckinley_root;
#define DBG_RES(x...)
#endif
#ifdef DEBUG_SBA_ASSERT
#undef ASSERT
#define ASSERT(expr) \
if(!(expr)) { \
printk("\n%s:%d: Assertion " #expr " failed!\n", \
__FILE__, __LINE__); \
panic(#expr); \
}
#else
#define ASSERT(expr)
#endif
#if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
/* "low end" PA8800 machines use ZX1 chipset */
#define ZX1_SUPPORT
......@@ -125,39 +111,24 @@ extern struct proc_dir_entry * proc_mckinley_root;
#define DEFAULT_DMA_HINT_REG 0
#define ASTRO_RUNWAY_PORT 0x582
#define ASTRO_ROPES_PORT 0x780
#define IKE_MERCED_PORT 0x803
#define IKE_ROPES_PORT 0x781
#define REO_MERCED_PORT 0x804
#define REO_ROPES_PORT 0x782
#define REOG_MERCED_PORT 0x805
#define REOG_ROPES_PORT 0x783
#define PLUTO_MCKINLEY_PORT 0x880
#define PLUTO_ROPES_PORT 0x784
#define SBA_FUNC_ID 0x0000 /* function id */
#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
#define IS_ASTRO(id) \
(((id)->hversion == ASTRO_RUNWAY_PORT) || ((id)->hversion == ASTRO_ROPES_PORT))
#define IS_IKE(id) \
(((id)->hversion == IKE_MERCED_PORT) || ((id)->hversion == IKE_ROPES_PORT))
#define IS_PLUTO(id) \
(((id)->hversion == PLUTO_MCKINLEY_PORT) || ((id)->hversion == PLUTO_ROPES_PORT))
#define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
#define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
#define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
#define ASTRO_IOC_OFFSET 0x20000
/* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
#define IKE_IOC_OFFSET(p) ((p+2)*SBA_FUNC_SIZE)
#define PLUTO_IOC_OFFSET 0x1000
#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
/* Ike's IOC's occupy functions 2 and 3 */
#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
#define IOC_CTRL 0x8 /* IOC_CTRL offset */
#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
......@@ -165,6 +136,8 @@ extern struct proc_dir_entry * proc_mckinley_root;
#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
#define IOC_CTRL_RM (1 << 8) /* Real Mode */
#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
......@@ -246,9 +219,9 @@ extern struct proc_dir_entry * proc_mckinley_root;
struct ioc {
unsigned long ioc_hpa; /* I/O MMU base address */
char *res_map; /* resource map, bit == pdir entry */
u64 *pdir_base; /* physical base address */
void __iomem *ioc_hpa; /* I/O MMU base address */
char *res_map; /* resource map, bit == pdir entry */
u64 *pdir_base; /* physical base address */
unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
#ifdef ZX1_SUPPORT
......@@ -295,7 +268,7 @@ struct sba_device {
struct parisc_device *dev; /* dev found in bus walk */
struct parisc_device_id *iodc; /* data about dev from firmware */
const char *name;
unsigned long sba_hpa; /* base address */
void __iomem *sba_hpa; /* base address */
spinlock_t sba_lock;
unsigned int flags; /* state/functionality enabled */
unsigned int hw_rev; /* HW revision of chip */
......@@ -312,9 +285,6 @@ static struct sba_device *sba_list;
static unsigned long ioc_needs_fdc = 0;
/* Ratio of Host MEM to IOV Space size */
static unsigned long sba_mem_ratio = 8;
/* global count of IOMMUs in the system */
static unsigned int global_ioc_cnt = 0;
......@@ -364,9 +334,9 @@ static int reserve_sba_gart = 1;
* IO Adapter (aka Bus Converter).
*/
static void
sba_dump_ranges(unsigned long hpa)
sba_dump_ranges(void __iomem *hpa)
{
DBG_INIT("SBA at 0x%lx\n", hpa);
DBG_INIT("SBA at 0x%p\n", hpa);
DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
......@@ -382,10 +352,9 @@ sba_dump_ranges(unsigned long hpa)
*
* Print the size/location of the IO MMU PDIR.
*/
static void
sba_dump_tlb(unsigned long hpa)
static void sba_dump_tlb(void __iomem *hpa)
{
DBG_INIT("IO TLB at 0x%lx\n", hpa);
DBG_INIT("IO TLB at 0x%p\n", hpa);
DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
......@@ -547,8 +516,6 @@ sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
unsigned long pide = ~0UL;
ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
ASSERT(res_ptr < res_end);
if (bits_wanted > (BITS_PER_LONG/2)) {
/* Search word at a time - no mask needed */
for(; res_ptr < res_end; ++res_ptr) {
......@@ -583,8 +550,8 @@ sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
while(res_ptr < res_end)
{
DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
BUG_ON(0 == mask);
if(0 == ((*res_ptr) & mask)) {
WARN_ON(mask == 0);
if(((*res_ptr) & mask) == 0) {
*res_ptr |= mask; /* mark resources busy! */
pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
pide <<= 3; /* convert to bit address */
......@@ -593,7 +560,7 @@ sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
}
mask >>= o;
bitshiftcnt += o;
if (0 == mask) {
if (mask == 0) {
mask = RESMAP_MASK(bits_wanted);
bitshiftcnt=0;
res_ptr++;
......@@ -631,21 +598,11 @@ sba_alloc_range(struct ioc *ioc, size_t size)
#endif
unsigned long pide;
ASSERT(pages_needed);
ASSERT((pages_needed * IOVP_SIZE) <= DMA_CHUNK_SIZE);
ASSERT(pages_needed <= BITS_PER_LONG);
ASSERT(0 == (size & ~IOVP_MASK));
/*
** "seek and ye shall find"...praying never hurts either...
** ggg sacrifices another 710 to the computer gods.
*/
pide = sba_search_bitmap(ioc, pages_needed);
if (pide >= (ioc->res_size << 3)) {
pide = sba_search_bitmap(ioc, pages_needed);
if (pide >= (ioc->res_size << 3))
panic("%s: I/O MMU @ %lx is out of mapping resources\n",
panic("%s: I/O MMU @ %p is out of mapping resources\n",
__FILE__, ioc->ioc_hpa);
}
......@@ -707,11 +664,6 @@ sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
ioc->used_pages -= bits_not_wanted;
#endif
ASSERT(m != 0);
ASSERT(bits_not_wanted);
ASSERT((bits_not_wanted * IOVP_SIZE) <= DMA_CHUNK_SIZE);
ASSERT(bits_not_wanted <= BITS_PER_LONG);
ASSERT((*res_ptr & m) == m); /* verify same bits are set */
*res_ptr &= ~m;
}
......@@ -732,8 +684,9 @@ typedef unsigned long space_t;
/**
* sba_io_pdir_entry - fill in one IO PDIR entry
* @pdir_ptr: pointer to IO PDIR entry
* @sid: process Space ID
* @sid: process Space ID - currently only support KERNEL_SPACE
* @vba: Virtual CPU address of buffer to map
* @hint: DMA hint set to use for this mapping
*
* SBA Mapping Routine
*
......@@ -768,7 +721,6 @@ typedef unsigned long space_t;
* IOMMU uses little endian for the pdir.
*/
void SBA_INLINE
sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
unsigned long hint)
......@@ -776,12 +728,6 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
u64 pa; /* physical address */
register unsigned ci; /* coherent index */
/* We currently only support kernel addresses.
* fdc instr below will need to reload sr1 with KERNEL_SPACE
* once we try to support direct DMA to user space.
*/
ASSERT(sid == KERNEL_SPACE);
pa = virt_to_phys(vba);
pa &= IOVP_MASK;
......@@ -830,10 +776,6 @@ sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
*/
int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
/* Must be non-zero and rounded up */
ASSERT(byte_cnt > 0);
ASSERT(0 == (byte_cnt & ~IOVP_MASK));
#ifdef ASSERT_PDIR_SANITY
/* Assert first pdir entry is set */
if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
......@@ -843,8 +785,6 @@ sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
if (byte_cnt <= IOVP_SIZE)
{
ASSERT( off < ioc->pdir_size);
iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
/*
......@@ -858,11 +798,7 @@ sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
u32 t = get_order(byte_cnt) + PAGE_SHIFT;
iovp |= t;
ASSERT(t <= 31); /* 2GB! Max value of "size" field */
do {
/* verify this pdir entry is enabled */
ASSERT(0x80 == (((u8 *) ioc->pdir_base)[off] & 0x80));
/* clear I/O Pdir entry "valid" bit first */
((u8 *)(ioc->pdir_base))[off] = 0;
off += sizeof(u64);
......@@ -880,17 +816,21 @@ sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
*
* See Documentation/DMA-mapping.txt
*/
static int
sba_dma_supported( struct device *dev, u64 mask)
static int sba_dma_supported( struct device *dev, u64 mask)
{
struct ioc *ioc;
if (dev == NULL) {
printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
BUG();
return(0);
}
/* only support 32-bit PCI devices - no DAC support (yet) */
return((int) (mask == 0xffffffffUL));
ioc = GET_IOC(dev);
/* check if mask is > than the largest IO Virt Address */
return((int) (mask >= (ioc->ibase +
(ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
}
......@@ -914,11 +854,7 @@ sba_map_single(struct device *dev, void *addr, size_t size,
u64 *pdir_start;
int pide;
ASSERT(size > 0);
ASSERT(size <= DMA_CHUNK_SIZE);
ioc = GET_IOC(dev);
ASSERT(ioc);
/* save offset bits */
offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
......@@ -944,7 +880,6 @@ sba_map_single(struct device *dev, void *addr, size_t size,
pdir_start = &(ioc->pdir_base[pide]);
while (size > 0) {
ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
......@@ -992,14 +927,10 @@ sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
unsigned long flags;
dma_addr_t offset;
ioc = GET_IOC(dev);
ASSERT(ioc);
DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
ioc = GET_IOC(dev);
offset = iova & ~IOVP_MASK;
DBG_RUN("%s() iovp 0x%lx/%x\n",
__FUNCTION__, (long) iova, size);
iova ^= offset; /* clear offset bits */
size += offset;
size = ROUNDUP(size, IOVP_SIZE);
......@@ -1131,7 +1062,6 @@ sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
ioc = GET_IOC(dev);
ASSERT(ioc);
/* Fast path single entry scatterlists. */
if (nents == 1) {
......@@ -1186,7 +1116,6 @@ sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
spin_unlock_irqrestore(&ioc->res_lock, flags);
ASSERT(coalesced == filled);
DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
return filled;
......@@ -1215,7 +1144,6 @@ sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
__FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
ioc = GET_IOC(dev);
ASSERT(ioc);
#ifdef SBA_COLLECT_STATS
ioc->usg_calls++;
......@@ -1394,16 +1322,27 @@ sba_alloc_pdir(unsigned int pdir_size)
return (void *) pdir_base;
}
static void
sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
/* setup Mercury or Elroy IBASE/IMASK registers. */
static void setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
/* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
/* lba_set_iregs() is in drivers/parisc/lba_pci.c */
extern void lba_set_iregs(struct parisc_device *, u32, u32);
struct device *dev;
list_for_each_entry(dev, &sba->dev.children, node) {
struct parisc_device *lba = to_parisc_device(dev);
int rope_num = (lba->hpa >> 13) & 0xf;
if (rope_num >> 3 == ioc_num)
lba_set_iregs(lba, ioc->ibase, ioc->imask);
}
}
static void
sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
u32 iova_space_mask;
u32 iova_space_size;
int iov_order, tcnfg;
struct parisc_device *lba;
#if SBA_AGP_SUPPORT
int agp_found = 0;
#endif
......@@ -1449,7 +1388,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
ioc->hint_shift_pdir, ioc->hint_mask_pdir);
#endif
ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
/* build IMASK for IOC and Elroy */
......@@ -1461,14 +1400,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
#endif
sba_dump_tlb(ioc->ioc_hpa);
/*
** setup Mercury IBASE/IMASK registers as well.
*/
for (lba = sba->child; lba; lba = lba->sibling) {
int rope_num = (lba->hpa >> 13) & 0xf;
if (rope_num >> 3 == ioc_num)
lba_set_iregs(lba, ioc->ibase, ioc->imask);
}
setup_ibase_imask(sba, ioc, ioc_num);
WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
......@@ -1534,13 +1466,8 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
static void
sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
/* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
extern void lba_set_iregs(struct parisc_device *, u32, u32);
u32 iova_space_size, iova_space_mask;
int pdir_size, iov_order;
unsigned long physmem;
struct parisc_device *lba;
unsigned int pdir_size, iov_order;
/*
** Determine IOVA Space size from memory size.
......@@ -1556,16 +1483,15 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
** for DMA hints - ergo only 30 bits max.
*/
physmem = num_physpages << PAGE_SHIFT;
iova_space_size = (u32) (physmem/(sba_mem_ratio*global_ioc_cnt));
iova_space_size = (u32) (num_physpages/global_ioc_cnt);
/* limit IOVA space size to 1MB-1GB */
if (iova_space_size < 1024*1024) {
iova_space_size = 1024*1024;
if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
iova_space_size = 1 << (20 - PAGE_SHIFT);
}
#ifdef __LP64__
else if (iova_space_size > 512*1024*1024) {
iova_space_size = 512*1024*1024;
else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
iova_space_size = 1 << (30 - PAGE_SHIFT);
}
#endif
......@@ -1574,21 +1500,19 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
** thus, pdir/res_map will also be log2().
** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
*/
iov_order = get_order(iova_space_size >> (IOVP_SHIFT-PAGE_SHIFT));
ASSERT(iov_order <= (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */
ASSERT(iov_order >= (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */
iova_space_size = 1 << (iov_order + IOVP_SHIFT);
ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
iov_order = get_order(iova_space_size << PAGE_SHIFT);
ASSERT(pdir_size < 4*1024*1024); /* max pdir size == 2MB */
/* iova_space_size is now bytes, not pages */
iova_space_size = 1 << (iov_order + PAGE_SHIFT);
/* Verify it's a power of two */
ASSERT((1 << get_order(pdir_size)) == (pdir_size >> PAGE_SHIFT));
ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
DBG_INIT("%s() hpa 0x%lx mem %dMB IOV %dMB (%d bits) PDIR size 0x%0x\n",
__FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20),
iova_space_size>>20, iov_order + PAGE_SHIFT, pdir_size);
DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
__FUNCTION__,
ioc->ioc_hpa,
(unsigned long) num_physpages >> (20 - PAGE_SHIFT),
iova_space_size>>20,
iov_order + PAGE_SHIFT);
ioc->pdir_base = sba_alloc_pdir(pdir_size);
......@@ -1604,7 +1528,6 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
ioc->hint_shift_pdir, ioc->hint_mask_pdir);
#endif
ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
/* build IMASK for IOC and Elroy */
......@@ -1630,14 +1553,7 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
** can't reprogram them the way drivers want.
*/
/*
** setup Elroy IBASE/IMASK registers as well.
*/
for (lba = sba->child; lba; lba = lba->sibling) {
int rope_num = (lba->hpa >> 13) & 0xf;
if (rope_num >> 3 == ioc_num)
lba_set_iregs(lba, ioc->ibase, ioc->imask);
}
setup_ibase_imask(sba, ioc, ioc_num);
/*
** Program the IOC's ibase and enable IOVA translation
......@@ -1672,8 +1588,12 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
**
**************************************************************************/
static void
sba_hw_init(struct sba_device *sba_dev)
static void __iomem *ioc_remap(struct sba_device *sba_dev, int offset)
{
return ioremap(sba_dev->dev->hpa + offset, SBA_FUNC_SIZE);
}
static void sba_hw_init(struct sba_device *sba_dev)
{
int i;
int num_ioc;
......@@ -1682,24 +1602,55 @@ sba_hw_init(struct sba_device *sba_dev)
if (!is_pdc_pat()) {
/* Shutdown the USB controller on Astro-based workstations.
** Once we reprogram the IOMMU, the next DMA performed by
** USB will HPMC the box.
** USB will HPMC the box. USB is only enabled if a
** keyboard is present and found.
**
** With serial console, j6k v5.0 firmware says:
** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
**
** FIXME: Using GFX+USB console at power up but direct
** linux to serial console is still broken.
** USB could generate DMA so we must reset USB.
** The proper sequence would be:
** o block console output
** o reset USB device
** o reprogram serial port
** o unblock console output
*/
pdc_io_reset_devices();
if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
pdc_io_reset_devices();
}
/*
** XXX May need something more sophisticated to deal
** with DMA from LAN. Maybe use page zero boot device
** as a handle to talk to PDC about which device to
** shutdown. This also needs to work for is_pdc_pat().
*/
}
#if 0
printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
/*
** Need to deal with DMA from LAN.
** Maybe use page zero boot device as a handle to talk
** to PDC about which device to shutdown.
**
** Netbooting, j6k v5.0 firmware says:
** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
** ARGH! invalid class.
*/
if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
&& (PAGE0->mem_boot.cl_class != CL_SEQU)) {
pdc_io_reset();
}
#endif
if (!IS_PLUTO(sba_dev->iodc)) {
ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
__FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
ioc_ctl |= IOC_CTRL_TC; /* Astro: firmware enables this */
ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
/* j6700 v1.6 firmware sets 0x294f */
/* A500 firmware sets 0x4d */
WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
......@@ -1712,7 +1663,7 @@ sba_hw_init(struct sba_device *sba_dev)
if (IS_ASTRO(sba_dev->iodc)) {
int err;
/* PAT_PDC (L-class) also reports the same goofy base */
sba_dev->ioc[0].ioc_hpa = ASTRO_IOC_OFFSET;
sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
num_ioc = 1;
sba_dev->chip_resv.name = "Astro Intr Ack";
......@@ -1730,32 +1681,32 @@ sba_hw_init(struct sba_device *sba_dev)
* corrected when we add it with IKE's IOC offset.
* Doesnt look clean, but fewer code.
*/
sba_dev->ioc[0].ioc_hpa = -PLUTO_IOC_OFFSET;
sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
num_ioc = 1;
sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
BUG_ON(err < 0);
WARN_ON(err < 0);
sba_dev->iommu_resv.name = "IOVA Space";
sba_dev->iommu_resv.start = 0x40000000UL;
sba_dev->iommu_resv.end = 0x50000000UL - 1;
err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
BUG_ON(err < 0);
WARN_ON(err < 0);
} else {
/* IS_IKE (ie N-class, L3000, L1500) */
sba_dev->ioc[0].ioc_hpa = sba_dev->ioc[1].ioc_hpa = 0;
sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
num_ioc = 2;
/* TODO - LOOKUP Ike/Stretch chipset mem map */
}
/* XXX: What about Reo? */
sba_dev->num_ioc = num_ioc;
for (i = 0; i < num_ioc; i++) {
sba_dev->ioc[i].ioc_hpa += sba_dev->sba_hpa + IKE_IOC_OFFSET(i);
/*
** Make sure the box crashes if we get any errors on a rope.
*/
......@@ -1771,6 +1722,16 @@ sba_hw_init(struct sba_device *sba_dev)
/* flush out the writes */
READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
i,
READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
);
DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
);
if (IS_PLUTO(sba_dev->iodc)) {
sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
} else {
......@@ -1984,16 +1945,6 @@ static struct parisc_device_id sba_tbl[] = {
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
{ HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
/* These two entries commented out because we don't find them in a
* buswalk yet. If/when we do, they would cause us to think we had
* many more SBAs then we really do.
* { HPHW_BCPORT, HVERSION_REV_ANY_ID, ASTRO_ROPES_PORT, 0xc },
* { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_ROPES_PORT, 0xc },
*/
/* We shall also comment out Pluto Ropes Port since bus walk doesnt
* report it yet.
* { HPHW_BCPORT, HVERSION_REV_ANY_ID, PLUTO_ROPES_PORT, 0xc },
*/
{ 0, }
};
......@@ -2017,18 +1968,19 @@ sba_driver_callback(struct parisc_device *dev)
u32 func_class;
int i;
char *version;
void __iomem *sba_addr = ioremap(dev->hpa, SBA_FUNC_SIZE);
sba_dump_ranges(dev->hpa);
sba_dump_ranges(sba_addr);
/* Read HW Rev First */
func_class = READ_REG(dev->hpa + SBA_FCLASS);
func_class = READ_REG(sba_addr + SBA_FCLASS);
if (IS_ASTRO(&dev->id)) {
unsigned long fclass;
static char astro_rev[]="Astro ?.?";
/* Astro is broken...Read HW Rev First */
fclass = READ_REG(dev->hpa);
fclass = READ_REG(sba_addr);
astro_rev[6] = '1' + (char) (fclass & 0x7);
astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
......@@ -2061,12 +2013,12 @@ sba_driver_callback(struct parisc_device *dev)
MODULE_NAME, version, dev->hpa);
sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
if (NULL == sba_dev) {
if (!sba_dev) {
printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
return(1);
return -ENOMEM;
}
dev->sysdata = (void *) sba_dev;
parisc_set_drvdata(dev, sba_dev);
memset(sba_dev, 0, sizeof(struct sba_device));
for(i=0; i<MAX_IOC; i++)
......@@ -2076,7 +2028,7 @@ sba_driver_callback(struct parisc_device *dev)
sba_dev->hw_rev = func_class;
sba_dev->iodc = &dev->id;
sba_dev->name = dev->name;
sba_dev->sba_hpa = dev->hpa; /* faster access */
sba_dev->sba_hpa = sba_addr;
sba_get_pat_resources(sba_dev);
sba_hw_init(sba_dev);
......@@ -2100,7 +2052,7 @@ sba_driver_callback(struct parisc_device *dev)
#endif
parisc_vmerge_boundary = IOVP_SIZE;
parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
parisc_has_iommu();
return 0;
}
......@@ -2129,7 +2081,7 @@ void * sba_get_iommu(struct parisc_device *pci_hba)
char t = sba_dev->id.hw_type;
int iocnum = (pci_hba->hw_path >> 3); /* rope # */
BUG_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
return &(sba->ioc[iocnum]);
}
......@@ -2159,7 +2111,7 @@ void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
/* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
for (i=0; i<4; i++) {
int base, size;
unsigned long reg = sba->sba_hpa + i*0x18;
void __iomem *reg = sba->sba_hpa + i*0x18;
base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
if ((base & 1) == 0)
......
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