irqchip/gic-v3: Work around affinity issues on ASR8601
The ASR8601 SoC combines ARMv8.2 CPUs from ARM with a GIC-500, also from ARM. However, the two are incompatible as the former expose an affinity in the form of (cluster, core, thread), while the latter can only deal with (cluster, core). If nothing is done, the GIC simply cannot route interrupts to the CPUs. Implement a workaround that shifts the affinity down by a level, ensuring the delivery of interrupts despite the implementation mismatch. Signed-off-by: zhengyan <zhengyan@asrmicro.com> [maz: rewrote commit message, reimplemented the workaround in a manageable way] Signed-off-by: Marc Zyngier <maz@kernel.org>
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