Commit b4e3c935 authored by Chris Wilson's avatar Chris Wilson

drm/i915: Save/restore irq state for vlv_residency_raw()

Since commit 6060b6ae ("drm/i915/pmu: Add RC6 residency metrics"),
vlv_residency_raw() may be called from an irq-disabled context (via perf
event sampling on remote cpu). As such, we can no longer assume that we
are called from process context and must save/restore the irq state for
the spinlock.

Fixes: 6060b6ae ("drm/i915/pmu: Add RC6 residency metrics")
Testcase: igt/perf_pmu/other-init-3
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171122222510.22627-1-chris@chris-wilson.co.ukReviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent ee48700d
...@@ -9396,12 +9396,13 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, ...@@ -9396,12 +9396,13 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
const i915_reg_t reg) const i915_reg_t reg)
{ {
u32 lower, upper, tmp; u32 lower, upper, tmp;
unsigned long flags;
int loop = 2; int loop = 2;
/* The register accessed do not need forcewake. We borrow /* The register accessed do not need forcewake. We borrow
* uncore lock to prevent concurrent access to range reg. * uncore lock to prevent concurrent access to range reg.
*/ */
spin_lock_irq(&dev_priv->uncore.lock); spin_lock_irqsave(&dev_priv->uncore.lock, flags);
/* vlv and chv residency counters are 40 bits in width. /* vlv and chv residency counters are 40 bits in width.
* With a control bit, we can choose between upper or lower * With a control bit, we can choose between upper or lower
...@@ -9432,7 +9433,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, ...@@ -9432,7 +9433,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
* now. * now.
*/ */
spin_unlock_irq(&dev_priv->uncore.lock); spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
return lower | (u64)upper << 8; return lower | (u64)upper << 8;
} }
...@@ -9451,7 +9452,6 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, ...@@ -9451,7 +9452,6 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
mul = 1000000; mul = 1000000;
div = dev_priv->czclk_freq; div = dev_priv->czclk_freq;
time_hw = vlv_residency_raw(dev_priv, reg); time_hw = vlv_residency_raw(dev_priv, reg);
} else { } else {
/* 833.33ns units on Gen9LP, 1.28us elsewhere. */ /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
if (IS_GEN9_LP(dev_priv)) { if (IS_GEN9_LP(dev_priv)) {
......
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