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Commit b5b5340d authored by Tero Kristo's avatar Tero Kristo Committed by Tony Lindgren
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ARM: dts: omap3: fix clock node definitions to avoid build warnings 

Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for OMAP3 clock nodes:

Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 6905e94d
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Showing with 215 additions and 215 deletions
arch/arm/boot/dts/am35xx-clocks.dtsi
View file @ b5b5340d
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
emac_ick: emac_ick {
emac_ick: emac_ick@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
......@@ -16,7 +16,7 @@ emac_ick: emac_ick {
ti,bit-shift = <1>;
};
emac_fck: emac_fck {
emac_fck: emac_fck@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&rmii_ck>;
......@@ -24,7 +24,7 @@ emac_fck: emac_fck {
ti,bit-shift = <9>;
};
vpfe_ick: vpfe_ick {
vpfe_ick: vpfe_ick@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
......@@ -32,7 +32,7 @@ vpfe_ick: vpfe_ick {
ti,bit-shift = <2>;
};
vpfe_fck: vpfe_fck {
vpfe_fck: vpfe_fck@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pclk_ck>;
......@@ -40,7 +40,7 @@ vpfe_fck: vpfe_fck {
ti,bit-shift = <10>;
};
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
......@@ -48,7 +48,7 @@ hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
ti,bit-shift = <0>;
};
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
......@@ -56,7 +56,7 @@ hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
ti,bit-shift = <8>;
};
hecc_ck: hecc_ck {
hecc_ck: hecc_ck@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&sys_ck>;
......@@ -65,7 +65,7 @@ hecc_ck: hecc_ck {
};
};
&cm_clocks {
ipss_ick: ipss_ick {
ipss_ick: ipss_ick@a10 {
#clock-cells = <0>;
compatible = "ti,am35xx-interface-clock";
clocks = <&core_l3_ick>;
......@@ -85,7 +85,7 @@ pclk_ck: pclk_ck {
clock-frequency = <27000000>;
};
uart4_ick_am35xx: uart4_ick_am35xx {
uart4_ick_am35xx: uart4_ick_am35xx@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -93,7 +93,7 @@ uart4_ick_am35xx: uart4_ick_am35xx {
ti,bit-shift = <23>;
};
uart4_fck_am35xx: uart4_fck_am35xx {
uart4_fck_am35xx: uart4_fck_am35xx@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......
arch/arm/boot/dts/omap3430es1-clocks.dtsi
View file @ b5b5340d
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&cm_clocks {
gfx_l3_ck: gfx_l3_ck {
gfx_l3_ck: gfx_l3_ck@b10 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
......@@ -16,7 +16,7 @@ gfx_l3_ck: gfx_l3_ck {
ti,bit-shift = <0>;
};
gfx_l3_fck: gfx_l3_fck {
gfx_l3_fck: gfx_l3_fck@b40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l3_ick>;
......@@ -33,7 +33,7 @@ gfx_l3_ick: gfx_l3_ick {
clock-div = <1>;
};
gfx_cg1_ck: gfx_cg1_ck {
gfx_cg1_ck: gfx_cg1_ck@b00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&gfx_l3_fck>;
......@@ -41,7 +41,7 @@ gfx_cg1_ck: gfx_cg1_ck {
ti,bit-shift = <1>;
};
gfx_cg2_ck: gfx_cg2_ck {
gfx_cg2_ck: gfx_cg2_ck@b00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&gfx_l3_fck>;
......@@ -49,7 +49,7 @@ gfx_cg2_ck: gfx_cg2_ck {
ti,bit-shift = <2>;
};
d2d_26m_fck: d2d_26m_fck {
d2d_26m_fck: d2d_26m_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
......@@ -57,7 +57,7 @@ d2d_26m_fck: d2d_26m_fck {
ti,bit-shift = <3>;
};
fshostusb_fck: fshostusb_fck {
fshostusb_fck: fshostusb_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -65,7 +65,7 @@ fshostusb_fck: fshostusb_fck {
ti,bit-shift = <5>;
};
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
......@@ -73,7 +73,7 @@ ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
......@@ -96,7 +96,7 @@ ssi_sst_fck: ssi_sst_fck_3430es1 {
clock-div = <2>;
};
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&core_l3_ick>;
......@@ -104,7 +104,7 @@ hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
ti,bit-shift = <4>;
};
fac_ick: fac_ick {
fac_ick: fac_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -120,7 +120,7 @@ ssi_l4_ick: ssi_l4_ick {
clock-div = <1>;
};
ssi_ick: ssi_ick_3430es1 {
ssi_ick: ssi_ick_3430es1@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&ssi_l4_ick>;
......@@ -128,7 +128,7 @@ ssi_ick: ssi_ick_3430es1 {
ti,bit-shift = <0>;
};
usb_l4_gate_ick: usb_l4_gate_ick {
usb_l4_gate_ick: usb_l4_gate_ick@a10 {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&l4_ick>;
......@@ -136,7 +136,7 @@ usb_l4_gate_ick: usb_l4_gate_ick {
reg = <0x0a10>;
};
usb_l4_div_ick: usb_l4_div_ick {
usb_l4_div_ick: usb_l4_div_ick@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&l4_ick>;
......@@ -152,7 +152,7 @@ usb_l4_ick: usb_l4_ick {
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
dss1_alwon_fck: dss1_alwon_fck_3430es1 {
dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m4x2_ck>;
......@@ -161,7 +161,7 @@ dss1_alwon_fck: dss1_alwon_fck_3430es1 {
ti,set-rate-parent;
};
dss_ick: dss_ick_3430es1 {
dss_ick: dss_ick_3430es1@e10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
......
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
View file @ b5b5340d
......@@ -16,7 +16,7 @@ security_l4_ick2: security_l4_ick2 {
clock-div = <1>;
};
aes1_ick: aes1_ick {
aes1_ick: aes1_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -24,7 +24,7 @@ aes1_ick: aes1_ick {
reg = <0x0a14>;
};
rng_ick: rng_ick {
rng_ick: rng_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -32,7 +32,7 @@ rng_ick: rng_ick {
ti,bit-shift = <2>;
};
sha11_ick: sha11_ick {
sha11_ick: sha11_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -40,7 +40,7 @@ sha11_ick: sha11_ick {
ti,bit-shift = <1>;
};
des1_ick: des1_ick {
des1_ick: des1_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -48,7 +48,7 @@ des1_ick: des1_ick {
ti,bit-shift = <0>;
};
cam_mclk: cam_mclk {
cam_mclk: cam_mclk@f00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m5x2_ck>;
......@@ -57,7 +57,7 @@ cam_mclk: cam_mclk {
ti,set-rate-parent;
};
cam_ick: cam_ick {
cam_ick: cam_ick@f10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
......@@ -65,7 +65,7 @@ cam_ick: cam_ick {
ti,bit-shift = <0>;
};
csi2_96m_fck: csi2_96m_fck {
csi2_96m_fck: csi2_96m_fck@f00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
......@@ -81,7 +81,7 @@ security_l3_ick: security_l3_ick {
clock-div = <1>;
};
pka_ick: pka_ick {
pka_ick: pka_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l3_ick>;
......@@ -89,7 +89,7 @@ pka_ick: pka_ick {
ti,bit-shift = <4>;
};
icr_ick: icr_ick {
icr_ick: icr_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -97,7 +97,7 @@ icr_ick: icr_ick {
ti,bit-shift = <29>;
};
des2_ick: des2_ick {
des2_ick: des2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -105,7 +105,7 @@ des2_ick: des2_ick {
ti,bit-shift = <26>;
};
mspro_ick: mspro_ick {
mspro_ick: mspro_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -113,7 +113,7 @@ mspro_ick: mspro_ick {
ti,bit-shift = <23>;
};
mailboxes_ick: mailboxes_ick {
mailboxes_ick: mailboxes_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -129,7 +129,7 @@ ssi_l4_ick: ssi_l4_ick {
clock-div = <1>;
};
sr1_fck: sr1_fck {
sr1_fck: sr1_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
......@@ -137,7 +137,7 @@ sr1_fck: sr1_fck {
ti,bit-shift = <6>;
};
sr2_fck: sr2_fck {
sr2_fck: sr2_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
......@@ -153,7 +153,7 @@ sr_l4_ick: sr_l4_ick {
clock-div = <1>;
};
dpll2_fck: dpll2_fck {
dpll2_fck: dpll2_fck@40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
......@@ -163,7 +163,7 @@ dpll2_fck: dpll2_fck {
ti,index-starts-at-one;
};
dpll2_ck: dpll2_ck {
dpll2_ck: dpll2_ck@4 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
......@@ -173,7 +173,7 @@ dpll2_ck: dpll2_ck {
ti,low-power-bypass;
};
dpll2_m2_ck: dpll2_m2_ck {
dpll2_m2_ck: dpll2_m2_ck@44 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll2_ck>;
......@@ -182,7 +182,7 @@ dpll2_m2_ck: dpll2_m2_ck {
ti,index-starts-at-one;
};
iva2_ck: iva2_ck {
iva2_ck: iva2_ck@0 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll2_m2_ck>;
......@@ -190,7 +190,7 @@ iva2_ck: iva2_ck {
ti,bit-shift = <0>;
};
modem_fck: modem_fck {
modem_fck: modem_fck@a00 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -198,7 +198,7 @@ modem_fck: modem_fck {
ti,bit-shift = <31>;
};
sad2d_ick: sad2d_ick {
sad2d_ick: sad2d_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
......@@ -206,7 +206,7 @@ sad2d_ick: sad2d_ick {
ti,bit-shift = <3>;
};
mad2d_ick: mad2d_ick {
mad2d_ick: mad2d_ick@a18 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
......@@ -214,7 +214,7 @@ mad2d_ick: mad2d_ick {
ti,bit-shift = <3>;
};
mspro_fck: mspro_fck {
mspro_fck: mspro_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
View file @ b5b5340d
......@@ -25,7 +25,7 @@ corex2_d5_fck: corex2_d5_fck {
};
};
&cm_clocks {
dpll5_ck: dpll5_ck {
dpll5_ck: dpll5_ck@d04 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&sys_ck>;
......@@ -34,7 +34,7 @@ dpll5_ck: dpll5_ck {
ti,lock;
};
dpll5_m2_ck: dpll5_m2_ck {
dpll5_m2_ck: dpll5_m2_ck@d50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll5_ck>;
......@@ -43,7 +43,7 @@ dpll5_m2_ck: dpll5_m2_ck {
ti,index-starts-at-one;
};
sgx_gate_fck: sgx_gate_fck {
sgx_gate_fck: sgx_gate_fck@b00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
......@@ -91,7 +91,7 @@ core_d2_ck: core_d2_ck {
clock-div = <2>;
};
sgx_mux_fck: sgx_mux_fck {
sgx_mux_fck: sgx_mux_fck@b40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
......@@ -104,7 +104,7 @@ sgx_fck: sgx_fck {
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
};
sgx_ick: sgx_ick {
sgx_ick: sgx_ick@b10 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
......@@ -112,7 +112,7 @@ sgx_ick: sgx_ick {
ti,bit-shift = <0>;
};
cpefuse_fck: cpefuse_fck {
cpefuse_fck: cpefuse_fck@a08 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
......@@ -120,7 +120,7 @@ cpefuse_fck: cpefuse_fck {
ti,bit-shift = <0>;
};
ts_fck: ts_fck {
ts_fck: ts_fck@a08 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_32k_fck>;
......@@ -128,7 +128,7 @@ ts_fck: ts_fck {
ti,bit-shift = <1>;
};
usbtll_fck: usbtll_fck {
usbtll_fck: usbtll_fck@a08 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll5_m2_ck>;
......@@ -136,7 +136,7 @@ usbtll_fck: usbtll_fck {
ti,bit-shift = <2>;
};
usbtll_ick: usbtll_ick {
usbtll_ick: usbtll_ick@a18 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -144,7 +144,7 @@ usbtll_ick: usbtll_ick {
ti,bit-shift = <2>;
};
mmchs3_ick: mmchs3_ick {
mmchs3_ick: mmchs3_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -152,7 +152,7 @@ mmchs3_ick: mmchs3_ick {
ti,bit-shift = <30>;
};
mmchs3_fck: mmchs3_fck {
mmchs3_fck: mmchs3_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -160,7 +160,7 @@ mmchs3_fck: mmchs3_fck {
ti,bit-shift = <30>;
};
dss1_alwon_fck: dss1_alwon_fck_3430es2 {
dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
......@@ -169,7 +169,7 @@ dss1_alwon_fck: dss1_alwon_fck_3430es2 {
ti,set-rate-parent;
};
dss_ick: dss_ick_3430es2 {
dss_ick: dss_ick_3430es2@e10 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
......@@ -177,7 +177,7 @@ dss_ick: dss_ick_3430es2 {
ti,bit-shift = <0>;
};
usbhost_120m_fck: usbhost_120m_fck {
usbhost_120m_fck: usbhost_120m_fck@1400 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll5_m2_ck>;
......@@ -185,7 +185,7 @@ usbhost_120m_fck: usbhost_120m_fck {
ti,bit-shift = <1>;
};
usbhost_48m_fck: usbhost_48m_fck {
usbhost_48m_fck: usbhost_48m_fck@1400 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&omap_48m_fck>;
......@@ -193,7 +193,7 @@ usbhost_48m_fck: usbhost_48m_fck {
ti,bit-shift = <0>;
};
usbhost_ick: usbhost_ick {
usbhost_ick: usbhost_ick@1410 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
......
arch/arm/boot/dts/omap36xx-clocks.dtsi
View file @ b5b5340d
......@@ -8,14 +8,14 @@
* published by the Free Software Foundation.
*/
&cm_clocks {
dpll4_ck: dpll4_ck {
dpll4_ck: dpll4_ck@d00 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-per-j-type-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
};
dpll4_m5x2_ck: dpll4_m5x2_ck {
dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m5x2_mul_ck>;
......@@ -25,7 +25,7 @@ dpll4_m5x2_ck: dpll4_m5x2_ck {
ti,set-bit-to-disable;
};
dpll4_m2x2_ck: dpll4_m2x2_ck {
dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
......@@ -34,7 +34,7 @@ dpll4_m2x2_ck: dpll4_m2x2_ck {
ti,set-bit-to-disable;
};
dpll3_m3x2_ck: dpll3_m3x2_ck {
dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll3_m3x2_mul_ck>;
......@@ -43,7 +43,7 @@ dpll3_m3x2_ck: dpll3_m3x2_ck {
ti,set-bit-to-disable;
};
dpll4_m3x2_ck: dpll4_m3x2_ck {
dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m3x2_mul_ck>;
......@@ -52,7 +52,7 @@ dpll4_m3x2_ck: dpll4_m3x2_ck {
ti,set-bit-to-disable;
};
dpll4_m6x2_ck: dpll4_m6x2_ck {
dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m6x2_mul_ck>;
......@@ -61,7 +61,7 @@ dpll4_m6x2_ck: dpll4_m6x2_ck {
ti,set-bit-to-disable;
};
uart4_fck: uart4_fck {
uart4_fck: uart4_fck@1000 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&per_48m_fck>;
......
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
View file @ b5b5340d
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&cm_clocks {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
......@@ -16,7 +16,7 @@ ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
......@@ -39,7 +39,7 @@ ssi_sst_fck: ssi_sst_fck_3430es2 {
clock-div = <2>;
};
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clocks = <&core_l3_ick>;
......@@ -55,7 +55,7 @@ ssi_l4_ick: ssi_l4_ick {
clock-div = <1>;
};
ssi_ick: ssi_ick_3430es2 {
ssi_ick: ssi_ick_3430es2@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
......@@ -63,7 +63,7 @@ ssi_ick: ssi_ick_3430es2 {
ti,bit-shift = <0>;
};
usim_gate_fck: usim_gate_fck {
usim_gate_fck: usim_gate_fck@c00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&omap_96m_fck>;
......@@ -143,7 +143,7 @@ dpll5_m2_d20_ck: dpll5_m2_d20_ck {
clock-div = <20>;
};
usim_mux_fck: usim_mux_fck {
usim_mux_fck: usim_mux_fck@c40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
......@@ -158,7 +158,7 @@ usim_fck: usim_fck {
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
};
usim_ick: usim_ick {
usim_ick: usim_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......
arch/arm/boot/dts/omap3xxx-clocks.dtsi
View file @ b5b5340d
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