Commit b5bf24b9 authored by Alan Cox's avatar Alan Cox Committed by Jeff Garzik

[PATCH] hpt37x: Check the enablebits

Helps for PATA but SATA bridged devices lie and always set all the bits
so will need the error handling fixes from Tejun.
Signed-off-by: default avatarAlan Cox <alan@redhat.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 0579e303
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
#include <linux/libata.h> #include <linux/libata.h>
#define DRV_NAME "pata_hpt37x" #define DRV_NAME "pata_hpt37x"
#define DRV_VERSION "0.5" #define DRV_VERSION "0.5.1"
struct hpt_clock { struct hpt_clock {
u8 xfer_speed; u8 xfer_speed;
...@@ -453,7 +453,13 @@ static int hpt37x_pre_reset(struct ata_port *ap) ...@@ -453,7 +453,13 @@ static int hpt37x_pre_reset(struct ata_port *ap)
{ {
u8 scr2, ata66; u8 scr2, ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct pci_dev *pdev = to_pci_dev(ap->host->dev);
static const struct pci_bits hpt37x_enable_bits[] = {
{ 0x50, 1, 0x04, 0x04 },
{ 0x54, 1, 0x04, 0x04 }
};
if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
return -ENOENT;
pci_read_config_byte(pdev, 0x5B, &scr2); pci_read_config_byte(pdev, 0x5B, &scr2);
pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
/* Cable register now active */ /* Cable register now active */
...@@ -488,10 +494,17 @@ static void hpt37x_error_handler(struct ata_port *ap) ...@@ -488,10 +494,17 @@ static void hpt37x_error_handler(struct ata_port *ap)
static int hpt374_pre_reset(struct ata_port *ap) static int hpt374_pre_reset(struct ata_port *ap)
{ {
static const struct pci_bits hpt37x_enable_bits[] = {
{ 0x50, 1, 0x04, 0x04 },
{ 0x54, 1, 0x04, 0x04 }
};
u16 mcr3, mcr6; u16 mcr3, mcr6;
u8 ata66; u8 ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev); struct pci_dev *pdev = to_pci_dev(ap->host->dev);
if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
return -ENOENT;
/* Do the extra channel work */ /* Do the extra channel work */
pci_read_config_word(pdev, 0x52, &mcr3); pci_read_config_word(pdev, 0x52, &mcr3);
pci_read_config_word(pdev, 0x56, &mcr6); pci_read_config_word(pdev, 0x56, &mcr6);
......
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