Commit b5dfc6c1 authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini

MIPS: KVM: Use tlb_write_random

When MIPS KVM needs to write a TLB entry for the guest it reads the
CP0_Random register, uses it to generate the CP_Index, and writes the
TLB entry using the TLBWI instruction (tlb_write_indexed()).

However there's an instruction for that, TLBWR (tlb_write_random()) so
use that instead.

This happens to also fix an issue with Ingenic XBurst cores where the
same TLB entry is replaced each time preventing forward progress on
stores due to alternating between TLB load misses for the instruction
fetch and TLB store misses.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: kvm@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Sanjay Lal <sanjayl@kymasys.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent facaaec1
...@@ -222,15 +222,13 @@ kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi, ...@@ -222,15 +222,13 @@ kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
return -1; return -1;
} }
if (idx < 0) {
idx = read_c0_random() % current_cpu_data.tlbsize;
write_c0_index(idx);
mtc0_tlbw_hazard();
}
write_c0_entrylo0(entrylo0); write_c0_entrylo0(entrylo0);
write_c0_entrylo1(entrylo1); write_c0_entrylo1(entrylo1);
mtc0_tlbw_hazard(); mtc0_tlbw_hazard();
if (idx < 0)
tlb_write_random();
else
tlb_write_indexed(); tlb_write_indexed();
tlbw_use_hazard(); tlbw_use_hazard();
......
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