Commit b617be33 authored by Baruch Siach's avatar Baruch Siach Committed by Mark Brown

spi: add SPI_RX_CPHA_FLIP mode bit

Some SPI devices latch MOSI bits on one clock phase, but produce valid
MISO bits on the other phase. Add SPI_RX_CPHA_FLIP mode to instruct the
controller driver to flip CPHA for Rx (MISO) only transfers.
Signed-off-by: default avatarBaruch Siach <baruch.siach@siklu.com>
Link: https://lore.kernel.org/r/a715ca92713ca02071f33dcca9960a66a03c949a.1649702729.git.baruch@tkos.co.ilSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4bbaa857
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */ #define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */
#define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ #define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */
#define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ #define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */
#define SPI_RX_CPHA_FLIP _BITUL(16) /* flip CPHA on Rx only xfer */
/* /*
* All the bits defined above should be covered by SPI_MODE_USER_MASK. * All the bits defined above should be covered by SPI_MODE_USER_MASK.
...@@ -36,6 +37,6 @@ ...@@ -36,6 +37,6 @@
* These bits must not overlap. A static assert check should make sure of that. * These bits must not overlap. A static assert check should make sure of that.
* If adding extra bits, make sure to increase the bit index below as well. * If adding extra bits, make sure to increase the bit index below as well.
*/ */
#define SPI_MODE_USER_MASK (_BITUL(16) - 1) #define SPI_MODE_USER_MASK (_BITUL(17) - 1)
#endif /* _UAPI_SPI_H */ #endif /* _UAPI_SPI_H */
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