Commit b61ea001 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin

drm/i915: Reset only affected engines when handling error capture

Pass down the engine mask to i915_clear_error_registers so only affected
engines can be reset on the Gen6/7 path.
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190607082557.31670-1-tvrtko.ursulin@linux.intel.com
parent bc7b488b
...@@ -1160,7 +1160,8 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) ...@@ -1160,7 +1160,8 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
intel_uncore_rmw(uncore, reg, 0, 0); intel_uncore_rmw(uncore, reg, 0, 0);
} }
void i915_clear_error_registers(struct drm_i915_private *i915) void i915_clear_error_registers(struct drm_i915_private *i915,
intel_engine_mask_t engine_mask)
{ {
struct intel_uncore *uncore = &i915->uncore; struct intel_uncore *uncore = &i915->uncore;
u32 eir; u32 eir;
...@@ -1193,7 +1194,7 @@ void i915_clear_error_registers(struct drm_i915_private *i915) ...@@ -1193,7 +1194,7 @@ void i915_clear_error_registers(struct drm_i915_private *i915)
struct intel_engine_cs *engine; struct intel_engine_cs *engine;
enum intel_engine_id id; enum intel_engine_id id;
for_each_engine(engine, i915, id) { for_each_engine_masked(engine, i915, engine_mask, id) {
rmw_clear(uncore, rmw_clear(uncore,
RING_FAULT_REG(engine), RING_FAULT_VALID); RING_FAULT_REG(engine), RING_FAULT_VALID);
intel_uncore_posting_read(uncore, intel_uncore_posting_read(uncore,
...@@ -1250,7 +1251,7 @@ void i915_handle_error(struct drm_i915_private *i915, ...@@ -1250,7 +1251,7 @@ void i915_handle_error(struct drm_i915_private *i915,
if (flags & I915_ERROR_CAPTURE) { if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(i915, engine_mask, msg); i915_capture_error_state(i915, engine_mask, msg);
i915_clear_error_registers(i915); i915_clear_error_registers(i915, engine_mask);
} }
/* /*
......
...@@ -25,7 +25,8 @@ void i915_handle_error(struct drm_i915_private *i915, ...@@ -25,7 +25,8 @@ void i915_handle_error(struct drm_i915_private *i915,
const char *fmt, ...); const char *fmt, ...);
#define I915_ERROR_CAPTURE BIT(0) #define I915_ERROR_CAPTURE BIT(0)
void i915_clear_error_registers(struct drm_i915_private *i915); void i915_clear_error_registers(struct drm_i915_private *i915,
intel_engine_mask_t engine_mask);
void i915_reset(struct drm_i915_private *i915, void i915_reset(struct drm_i915_private *i915,
intel_engine_mask_t stalled_mask, intel_engine_mask_t stalled_mask,
......
...@@ -2359,7 +2359,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) ...@@ -2359,7 +2359,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
else else
return; return;
i915_clear_error_registers(dev_priv); i915_clear_error_registers(dev_priv, ALL_ENGINES);
} }
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
......
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