Commit b7e29924 authored by Paul Cercueil's avatar Paul Cercueil Committed by Stephen Boyd

clk: ingenic: jz4740: Fix gating of UDC clock

The UDC clock is gated when the bit is cleared, not when it is set.
Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Tested-by: default avatarArtur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent bfeffd15
...@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { ...@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
.mux = { CGU_REG_CPCCR, 29, 1 }, .mux = { CGU_REG_CPCCR, 29, 1 },
.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
.gate = { CGU_REG_SCR, 6 }, .gate = { CGU_REG_SCR, 6, true },
}, },
/* Gate-only clocks */ /* Gate-only clocks */
......
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