Commit b8afb911 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Keep GMCH DPLL VGA mode always disabled

We disable the DPLL VGA mode when enabling the DPLL, but we enaable it
again when disabling the DPLL. Having VGA mode enabled even in unused
DPLLs can cause problems for CHV, so it seems wiser to always keep it
disabled. And let's just do that on all GMCH platforms to keep things
as similar as possible between them.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f936ec34
...@@ -1790,13 +1790,13 @@ static void i9xx_disable_pll(struct intel_crtc *crtc) ...@@ -1790,13 +1790,13 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
/* Make sure the pipe isn't still relying on us */ /* Make sure the pipe isn't still relying on us */
assert_pipe_disabled(dev_priv, pipe); assert_pipe_disabled(dev_priv, pipe);
I915_WRITE(DPLL(pipe), 0); I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
POSTING_READ(DPLL(pipe)); POSTING_READ(DPLL(pipe));
} }
static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{ {
u32 val = 0; u32 val;
/* Make sure the pipe isn't still relying on us */ /* Make sure the pipe isn't still relying on us */
assert_pipe_disabled(dev_priv, pipe); assert_pipe_disabled(dev_priv, pipe);
...@@ -1805,6 +1805,7 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) ...@@ -1805,6 +1805,7 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
* Leave integrated clock source and reference clock enabled for pipe B. * Leave integrated clock source and reference clock enabled for pipe B.
* The latter is needed for VGA hotplug / manual detection. * The latter is needed for VGA hotplug / manual detection.
*/ */
val = DPLL_VGA_MODE_DIS;
if (pipe == PIPE_B) if (pipe == PIPE_B)
val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
I915_WRITE(DPLL(pipe), val); I915_WRITE(DPLL(pipe), val);
...@@ -1821,7 +1822,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) ...@@ -1821,7 +1822,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
assert_pipe_disabled(dev_priv, pipe); assert_pipe_disabled(dev_priv, pipe);
/* Set PLL en = 0 */ /* Set PLL en = 0 */
val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; val = DPLL_SSC_REF_CLOCK_CHV |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
if (pipe != PIPE_A) if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV; val |= DPLL_INTEGRATED_CRI_CLK_VLV;
I915_WRITE(DPLL(pipe), val); I915_WRITE(DPLL(pipe), val);
......
...@@ -418,7 +418,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) ...@@ -418,7 +418,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
/* update the hw state for DPLL */ /* update the hw state for DPLL */
intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
DPLL_REFA_CLK_ENABLE_VLV; DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
tmp = I915_READ(DSPCLK_GATE_D); tmp = I915_READ(DSPCLK_GATE_D);
tmp |= DPOUNIT_CLOCK_GATE_DISABLE; tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
......
...@@ -882,7 +882,7 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, ...@@ -882,7 +882,7 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
* display and the reference clock for VGA * display and the reference clock for VGA
* hotplug / manual detection. * hotplug / manual detection.
*/ */
I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
...@@ -933,13 +933,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, ...@@ -933,13 +933,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
*/ */
if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
phy = DPIO_PHY0; phy = DPIO_PHY0;
I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
DPLL_REFA_CLK_ENABLE_VLV); DPLL_REFA_CLK_ENABLE_VLV);
I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
} else { } else {
phy = DPIO_PHY1; phy = DPIO_PHY1;
I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
} }
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
......
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