Commit b99ef12b authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/gr/tu11x: initial support

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 072663f8
...@@ -2608,6 +2608,7 @@ nv167_chipset = { ...@@ -2608,6 +2608,7 @@ nv167_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new, .nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
...@@ -2645,6 +2646,7 @@ nv168_chipset = { ...@@ -2645,6 +2646,7 @@ nv168_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new, .nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
......
...@@ -164,6 +164,32 @@ MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin"); ...@@ -164,6 +164,32 @@ MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin"); MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin"); MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");
static const struct gf100_gr_fwif static const struct gf100_gr_fwif
tu102_gr_fwif[] = { tu102_gr_fwif[] = {
{ 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
......
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