Commit bbd0abda authored by Paul Mackerras's avatar Paul Mackerras

powerpc: Merge 32-bit CHRP support.

SMP still needs more work but UP gets as far as starting userspace
at least.  This uses the 64-bit-style code for spinning up the cpus.
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 303d72a0
......@@ -339,7 +339,7 @@ config U3_DART
default n
config MPIC
depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP
bool
default y
......
......@@ -207,7 +207,7 @@ turn_on_mmu:
.globl __secondary_hold
__secondary_hold:
/* tell the master we're here */
stw r3,4(0)
stw r3,__secondary_hold_acknowledge@l(0)
#ifdef CONFIG_SMP
100: lwz r4,0(0)
/* wait until we're told to start */
......@@ -220,6 +220,13 @@ __secondary_hold:
b .
#endif /* CONFIG_SMP */
.globl __secondary_hold_spinloop
__secondary_hold_spinloop:
.long 0
.globl __secondary_hold_acknowledge
__secondary_hold_acknowledge:
.long -1
/*
* Exception entry code. This code runs with address translation
* turned off, i.e. using physical addresses.
......
......@@ -1155,9 +1155,18 @@ static void __init prom_initialize_tce_table(void)
*
* -- Cort
*/
extern void __secondary_hold(void);
extern unsigned long __secondary_hold_spinloop;
extern unsigned long __secondary_hold_acknowledge;
/*
* We want to reference the copy of __secondary_hold_* in the
* 0 - 0x100 address range
*/
#define LOW_ADDR(x) (((unsigned long) &(x)) & 0xff)
static void __init prom_hold_cpus(void)
{
#ifdef CONFIG_PPC64
unsigned long i;
unsigned int reg;
phandle node;
......@@ -1166,20 +1175,18 @@ static void __init prom_hold_cpus(void)
unsigned int interrupt_server[MAX_CPU_THREADS];
unsigned int cpu_threads, hw_cpu_num;
int propsize;
extern void __secondary_hold(void);
extern unsigned long __secondary_hold_spinloop;
extern unsigned long __secondary_hold_acknowledge;
struct prom_t *_prom = &RELOC(prom);
unsigned long *spinloop
= (void *) __pa(&__secondary_hold_spinloop);
= (void *) LOW_ADDR(__secondary_hold_spinloop);
unsigned long *acknowledge
= (void *) __pa(&__secondary_hold_acknowledge);
= (void *) LOW_ADDR(__secondary_hold_acknowledge);
#ifdef CONFIG_PPC64
/* __secondary_hold is actually a descriptor, not the text address */
unsigned long secondary_hold
= __pa(*PTRRELOC((unsigned long *)__secondary_hold));
#else
unsigned long secondary_hold = __pa(&__secondary_hold);
unsigned long secondary_hold = LOW_ADDR(__secondary_hold);
#endif
struct prom_t *_prom = &RELOC(prom);
prom_debug("prom_hold_cpus: start...\n");
prom_debug(" 1) spinloop = 0x%x\n", (unsigned long)spinloop);
......@@ -1197,9 +1204,8 @@ static void __init prom_hold_cpus(void)
*spinloop = 0;
#ifdef CONFIG_HMT
for (i = 0; i < NR_CPUS; i++) {
for (i = 0; i < NR_CPUS; i++)
RELOC(hmt_thread_data)[i].pir = 0xdeadbeef;
}
#endif
/* look for cpus */
for (node = 0; prom_next_node(&node); ) {
......@@ -1250,34 +1256,22 @@ static void __init prom_hold_cpus(void)
call_prom("start-cpu", 3, 0, node,
secondary_hold, reg);
for ( i = 0 ; (i < 100000000) &&
for (i = 0; (i < 100000000) &&
(*acknowledge == ((unsigned long)-1)); i++ )
mb();
if (*acknowledge == reg) {
if (*acknowledge == reg)
prom_printf("done\n");
/* We have to get every CPU out of OF,
* even if we never start it. */
if (cpuid >= NR_CPUS)
goto next;
} else {
else
prom_printf("failed: %x\n", *acknowledge);
}
}
#ifdef CONFIG_SMP
else
prom_printf("%x : boot cpu %x\n", cpuid, reg);
#endif
next:
#ifdef CONFIG_SMP
/* Init paca for secondary threads. They start later. */
for (i=1; i < cpu_threads; i++) {
cpuid++;
if (cpuid >= NR_CPUS)
continue;
}
#endif /* CONFIG_SMP */
cpuid++;
/* Reserve cpu #s for secondary threads. They start later. */
cpuid += cpu_threads;
}
#ifdef CONFIG_HMT
/* Only enable HMT on processors that provide support. */
......@@ -1311,7 +1305,6 @@ static void __init prom_hold_cpus(void)
") exceeded: ignoring extras\n");
prom_debug("prom_hold_cpus: end...\n");
#endif
}
......@@ -1940,7 +1933,6 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
unsigned long r6, unsigned long r7)
{
struct prom_t *_prom;
extern char _stext[];
unsigned long hdr;
u32 getprop_rval;
unsigned long offset = reloc_offset();
......
......@@ -56,6 +56,10 @@ extern void power4_idle(void);
boot_infos_t *boot_infos;
struct ide_machdep_calls ppc_ide_md;
/* XXX should go elsewhere */
int __irq_offset_value;
EXPORT_SYMBOL(__irq_offset_value);
/* Used with the BI_MEMSIZE bootinfo parameter to store the memory
size value reported by the boot loader. */
unsigned long boot_mem_size;
......
......@@ -5,6 +5,7 @@ ifeq ($(CONFIG_PPC64),y)
obj-$(CONFIG_PPC_PMAC) += powermac/
endif
endif
obj-$(CONFIG_PPC_CHRP) += chrp/
obj-$(CONFIG_4xx) += 4xx/
obj-$(CONFIG_85xx) += 85xx/
obj-$(CONFIG_PPC_PSERIES) += pseries/
......
obj-y += setup.o time.o pegasos_eth.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SMP) += smp.o
/*
* CHRP pci routines.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/prom.h>
#include <asm/gg2.h>
#include <asm/machdep.h>
#include <asm/sections.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/grackle.h>
#include <asm/rtas.h>
/* LongTrail */
void __iomem *gg2_pci_config_base;
/*
* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
* limit the bus number to 3 bits
*/
int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
int len, u32 *val)
{
volatile void __iomem *cfg_data;
struct pci_controller *hose = bus->sysdata;
if (bus->number > 7)
return PCIBIOS_DEVICE_NOT_FOUND;
/*
* Note: the caller has already checked that off is
* suitably aligned and that len is 1, 2 or 4.
*/
cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
switch (len) {
case 1:
*val = in_8(cfg_data);
break;
case 2:
*val = in_le16(cfg_data);
break;
default:
*val = in_le32(cfg_data);
break;
}
return PCIBIOS_SUCCESSFUL;
}
int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
int len, u32 val)
{
volatile void __iomem *cfg_data;
struct pci_controller *hose = bus->sysdata;
if (bus->number > 7)
return PCIBIOS_DEVICE_NOT_FOUND;
/*
* Note: the caller has already checked that off is
* suitably aligned and that len is 1, 2 or 4.
*/
cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
switch (len) {
case 1:
out_8(cfg_data, val);
break;
case 2:
out_le16(cfg_data, val);
break;
default:
out_le32(cfg_data, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops gg2_pci_ops =
{
gg2_read_config,
gg2_write_config
};
/*
* Access functions for PCI config space using RTAS calls.
*/
int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
struct pci_controller *hose = bus->sysdata;
unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
| (((bus->number - hose->first_busno) & 0xff) << 16)
| (hose->index << 24);
int ret = -1;
int rval;
rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
*val = ret;
return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}
int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
struct pci_controller *hose = bus->sysdata;
unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
| (((bus->number - hose->first_busno) & 0xff) << 16)
| (hose->index << 24);
int rval;
rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
addr, len, val);
return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}
static struct pci_ops rtas_pci_ops =
{
rtas_read_config,
rtas_write_config
};
volatile struct Hydra __iomem *Hydra = NULL;
int __init
hydra_init(void)
{
struct device_node *np;
np = find_devices("mac-io");
if (np == NULL || np->n_addrs == 0)
return 0;
Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
printk("Hydra Mac I/O at %lx\n", np->addrs[0].address);
printk("Hydra Feature_Control was %x",
in_le32(&Hydra->Feature_Control));
out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
HYDRA_FC_SCSI_CELL_EN |
HYDRA_FC_SCCA_ENABLE |
HYDRA_FC_SCCB_ENABLE |
HYDRA_FC_ARB_BYPASS |
HYDRA_FC_MPIC_ENABLE |
HYDRA_FC_SLOW_SCC_PCLK |
HYDRA_FC_MPIC_IS_MASTER));
printk(", now %x\n", in_le32(&Hydra->Feature_Control));
return 1;
}
void __init
chrp_pcibios_fixup(void)
{
struct pci_dev *dev = NULL;
struct device_node *np;
/* PCI interrupts are controlled by the OpenPIC */
for_each_pci_dev(dev) {
np = pci_device_to_OF_node(dev);
if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
dev->irq = np->intrs[0].line;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
}
#define PRG_CL_RESET_VALID 0x00010000
static void __init
setup_python(struct pci_controller *hose, struct device_node *dev)
{
u32 __iomem *reg;
u32 val;
unsigned long addr = dev->addrs[0].address;
setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
/* Clear the magic go-slow bit */
reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
val = in_be32(&reg[12]);
if (val & PRG_CL_RESET_VALID) {
out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
in_be32(&reg[12]);
}
iounmap(reg);
}
/* Marvell Discovery II based Pegasos 2 */
static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
{
struct device_node *root = find_path_device("/");
struct device_node *rtas;
rtas = of_find_node_by_name (root, "rtas");
if (rtas) {
hose->ops = &rtas_pci_ops;
} else {
printk ("RTAS supporting Pegasos OF not found, please upgrade"
" your firmware\n");
}
pci_assign_all_buses = 1;
}
void __init
chrp_find_bridges(void)
{
struct device_node *dev;
int *bus_range;
int len, index = -1;
struct pci_controller *hose;
unsigned int *dma;
char *model, *machine;
int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
struct device_node *root = find_path_device("/");
/*
* The PCI host bridge nodes on some machines don't have
* properties to adequately identify them, so we have to
* look at what sort of machine this is as well.
*/
machine = get_property(root, "model", NULL);
if (machine != NULL) {
is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
is_mot = strncmp(machine, "MOT", 3) == 0;
if (strncmp(machine, "Pegasos2", 8) == 0)
is_pegasos = 2;
else if (strncmp(machine, "Pegasos", 7) == 0)
is_pegasos = 1;
}
for (dev = root->child; dev != NULL; dev = dev->sibling) {
if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
continue;
++index;
/* The GG2 bridge on the LongTrail doesn't have an address */
if (dev->n_addrs < 1 && !is_longtrail) {
printk(KERN_WARNING "Can't use %s: no address\n",
dev->full_name);
continue;
}
bus_range = (int *) get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s\n",
dev->full_name);
continue;
}
if (bus_range[1] == bus_range[0])
printk(KERN_INFO "PCI bus %d", bus_range[0]);
else
printk(KERN_INFO "PCI buses %d..%d",
bus_range[0], bus_range[1]);
printk(" controlled by %s", dev->type);
if (dev->n_addrs > 0)
printk(" at %lx", dev->addrs[0].address);
printk("\n");
hose = pcibios_alloc_controller();
if (!hose) {
printk("Can't allocate PCI controller structure for %s\n",
dev->full_name);
continue;
}
hose->arch_data = dev;
hose->first_busno = bus_range[0];
hose->last_busno = bus_range[1];
model = get_property(dev, "model", NULL);
if (model == NULL)
model = "<none>";
if (device_is_compatible(dev, "IBM,python")) {
setup_python(hose, dev);
} else if (is_mot
|| strncmp(model, "Motorola, Grackle", 17) == 0) {
setup_grackle(hose);
} else if (is_longtrail) {
void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
hose->ops = &gg2_pci_ops;
hose->cfg_data = p;
gg2_pci_config_base = p;
} else if (is_pegasos == 1) {
setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
} else if (is_pegasos == 2) {
setup_peg2(hose, dev);
} else {
printk("No methods for %s (model %s), using RTAS\n",
dev->full_name, model);
hose->ops = &rtas_pci_ops;
}
pci_process_bridge_OF_ranges(hose, dev, index == 0);
/* check the first bridge for a property that we can
use to set pci_dram_offset */
dma = (unsigned int *)
get_property(dev, "ibm,dma-ranges", &len);
if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
pci_dram_offset = dma[2] - dma[3];
printk("pci_dram_offset = %lx\n", pci_dram_offset);
}
}
/* Do not fixup interrupts from OF tree on pegasos */
if (is_pegasos == 0)
ppc_md.pcibios_fixup = chrp_pcibios_fixup;
}
/*
* arch/ppc/platforms/chrp_pegasos_eth.c
*
* Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
* Thanks to :
* Dale Farnsworth <dale@farnsworth.org>
* Mark A. Greer <mgreer@mvista.com>
* Nicolas DET <nd@bplan-gmbh.de>
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
* And anyone else who helped me on this.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/mv643xx.h>
#include <linux/pci.h>
/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
static struct resource mv643xx_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = 9,
.end = 9,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth0_pd;
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
.resource = mv643xx_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
static struct resource mv643xx_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = 9,
.end = 9,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth1_pd;
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
.resource = mv643xx_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
&eth0_device,
&eth1_device,
};
int
mv643xx_eth_add_pds(void)
{
int ret = 0;
static struct pci_device_id pci_marvell_mv64360[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
{ }
};
if (pci_dev_present(pci_marvell_mv64360)) {
ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
}
return ret;
}
device_initcall(mv643xx_eth_add_pds);
This diff is collapsed.
/*
* Smp support for CHRP machines.
*
* Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
* deal of code from the sparc and intel versions.
*
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
*
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <asm/ptrace.h>
#include <asm/atomic.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/smp.h>
#include <asm/residual.h>
#include <asm/time.h>
#include <asm/open_pic.h>
#include <asm/machdep.h>
extern unsigned long smp_chrp_cpu_nr;
static int __init smp_chrp_probe(void)
{
if (smp_chrp_cpu_nr > 1)
openpic_request_IPIs();
return smp_chrp_cpu_nr;
}
static void __devinit smp_chrp_kick_cpu(int nr)
{
*(unsigned long *)KERNELBASE = nr;
asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
}
static void __devinit smp_chrp_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static DEFINE_SPINLOCK(timebase_lock);
static unsigned int timebase_upper = 0, timebase_lower = 0;
void __devinit smp_chrp_give_timebase(void)
{
spin_lock(&timebase_lock);
rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
timebase_upper = get_tbu();
timebase_lower = get_tbl();
spin_unlock(&timebase_lock);
while (timebase_upper || timebase_lower)
barrier();
rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
}
void __devinit smp_chrp_take_timebase(void)
{
while (!(timebase_upper || timebase_lower))
barrier();
spin_lock(&timebase_lock);
set_tb(timebase_upper, timebase_lower);
timebase_upper = 0;
timebase_lower = 0;
spin_unlock(&timebase_lock);
printk("CPU %i taken timebase\n", smp_processor_id());
}
/* CHRP with openpic */
struct smp_ops_t chrp_smp_ops = {
.message_pass = smp_openpic_message_pass,
.probe = smp_chrp_probe,
.kick_cpu = smp_chrp_kick_cpu,
.setup_cpu = smp_chrp_setup_cpu,
.give_timebase = smp_chrp_give_timebase,
.take_timebase = smp_chrp_take_timebase,
};
/*
* arch/ppc/platforms/chrp_time.c
*
* Copyright (C) 1991, 1992, 1995 Linus Torvalds
*
* Adapted for PowerPC (PReP) by Gary Thomas
* Modified by Cort Dougan (cort@cs.nmt.edu).
* Copied and modified from arch/i386/kernel/time.c
*
*/
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/init.h>
#include <linux/bcd.h>
#include <asm/io.h>
#include <asm/nvram.h>
#include <asm/prom.h>
#include <asm/sections.h>
#include <asm/time.h>
extern spinlock_t rtc_lock;
static int nvram_as1 = NVRAM_AS1;
static int nvram_as0 = NVRAM_AS0;
static int nvram_data = NVRAM_DATA;
long __init chrp_time_init(void)
{
struct device_node *rtcs;
int base;
rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
if (rtcs == NULL)
rtcs = find_compatible_devices("rtc", "ds1385-rtc");
if (rtcs == NULL || rtcs->addrs == NULL)
return 0;
base = rtcs->addrs[0].address;
nvram_as1 = 0;
nvram_as0 = base;
nvram_data = base + 1;
return 0;
}
int chrp_cmos_clock_read(int addr)
{
if (nvram_as1 != 0)
outb(addr>>8, nvram_as1);
outb(addr, nvram_as0);
return (inb(nvram_data));
}
void chrp_cmos_clock_write(unsigned long val, int addr)
{
if (nvram_as1 != 0)
outb(addr>>8, nvram_as1);
outb(addr, nvram_as0);
outb(val, nvram_data);
return;
}
/*
* Set the hardware clock. -- Cort
*/
int chrp_set_rtc_time(struct rtc_time *tmarg)
{
unsigned char save_control, save_freq_select;
struct rtc_time tm = *tmarg;
spin_lock(&rtc_lock);
save_control = chrp_cmos_clock_read(RTC_CONTROL); /* tell the clock it's being set */
chrp_cmos_clock_write((save_control|RTC_SET), RTC_CONTROL);
save_freq_select = chrp_cmos_clock_read(RTC_FREQ_SELECT); /* stop and reset prescaler */
chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
tm.tm_year -= 1900;
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
BIN_TO_BCD(tm.tm_sec);
BIN_TO_BCD(tm.tm_min);
BIN_TO_BCD(tm.tm_hour);
BIN_TO_BCD(tm.tm_mon);
BIN_TO_BCD(tm.tm_mday);
BIN_TO_BCD(tm.tm_year);
}
chrp_cmos_clock_write(tm.tm_sec,RTC_SECONDS);
chrp_cmos_clock_write(tm.tm_min,RTC_MINUTES);
chrp_cmos_clock_write(tm.tm_hour,RTC_HOURS);
chrp_cmos_clock_write(tm.tm_mon,RTC_MONTH);
chrp_cmos_clock_write(tm.tm_mday,RTC_DAY_OF_MONTH);
chrp_cmos_clock_write(tm.tm_year,RTC_YEAR);
/* The following flags have to be released exactly in this order,
* otherwise the DS12887 (popular MC146818A clone with integrated
* battery and quartz) will not reset the oscillator and will not
* update precisely 500 ms later. You won't find this mentioned in
* the Dallas Semiconductor data sheets, but who believes data
* sheets anyway ... -- Markus Kuhn
*/
chrp_cmos_clock_write(save_control, RTC_CONTROL);
chrp_cmos_clock_write(save_freq_select, RTC_FREQ_SELECT);
spin_unlock(&rtc_lock);
return 0;
}
void chrp_get_rtc_time(struct rtc_time *tm)
{
unsigned int year, mon, day, hour, min, sec;
int uip, i;
/* The Linux interpretation of the CMOS clock register contents:
* When the Update-In-Progress (UIP) flag goes from 1 to 0, the
* RTC registers show the second which has precisely just started.
* Let's hope other operating systems interpret the RTC the same way.
*/
/* Since the UIP flag is set for about 2.2 ms and the clock
* is typically written with a precision of 1 jiffy, trying
* to obtain a precision better than a few milliseconds is
* an illusion. Only consistency is interesting, this also
* allows to use the routine for /dev/rtc without a potential
* 1 second kernel busy loop triggered by any reader of /dev/rtc.
*/
for ( i = 0; i<1000000; i++) {
uip = chrp_cmos_clock_read(RTC_FREQ_SELECT);
sec = chrp_cmos_clock_read(RTC_SECONDS);
min = chrp_cmos_clock_read(RTC_MINUTES);
hour = chrp_cmos_clock_read(RTC_HOURS);
day = chrp_cmos_clock_read(RTC_DAY_OF_MONTH);
mon = chrp_cmos_clock_read(RTC_MONTH);
year = chrp_cmos_clock_read(RTC_YEAR);
uip |= chrp_cmos_clock_read(RTC_FREQ_SELECT);
if ((uip & RTC_UIP)==0) break;
}
if (!(chrp_cmos_clock_read(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
BCD_TO_BIN(sec);
BCD_TO_BIN(min);
BCD_TO_BIN(hour);
BCD_TO_BIN(day);
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
}
if ((year += 1900) < 1970)
year += 100;
tm->tm_sec = sec;
tm->tm_min = min;
tm->tm_hour = hour;
tm->tm_mday = day;
tm->tm_mon = mon;
tm->tm_year = year;
}
void __init chrp_calibrate_decr(void)
{
struct device_node *cpu;
unsigned int freq, *fp;
/*
* The cpu node should have a timebase-frequency property
* to tell us the rate at which the decrementer counts.
*/
freq = 16666000; /* hardcoded default */
cpu = find_type_devices("cpu");
if (cpu != 0) {
fp = (unsigned int *)
get_property(cpu, "timebase-frequency", NULL);
if (fp != 0)
freq = *fp;
}
ppc_tb_freq = freq;
}
......@@ -71,10 +71,6 @@ static u32 level_mask[4];
static DEFINE_SPINLOCK(pmac_pic_lock);
/* XXX here for now, should move to arch/powerpc/kernel/irq.c */
int ppc_do_canonicalize_irqs;
EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
#define GATWICK_IRQ_POOL_SIZE 10
static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
......
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