mips, bpf: Optimize loading of 64-bit constants

This patch shaves off a few instructions when loading sparse 64-bit
constants to register. The change is covered by additional tests in
lib/test_bpf.c.
Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20211007142828.634182-1-johan.almbladh@anyfinetworks.com

arch/mips/net/bpf_jit_comp64.c

@@ -131,19 +131,25 @@ static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64)
 		emit(ctx, ori, dst, dst, (u16)imm64 & 0xffff);
 	} else {
 		u8 acc = MIPS_R_ZERO;
+		int shift = 0;
 		int k;
 
 		for (k = 0; k < 4; k++) {
 			u16 half = imm64 >> (48 - 16 * k);
 
 			if (acc == dst)
-				emit(ctx, dsll, dst, dst, 16);
+				shift += 16;
 
 			if (half) {
+				if (shift)
+					emit(ctx, dsll_safe, dst, dst, shift);
 				emit(ctx, ori, dst, acc, half);
 				acc = dst;
+				shift = 0;
 			}
 		}
+		if (shift)
+			emit(ctx, dsll_safe, dst, dst, shift);
 	}
 	clobber_reg(ctx, dst);
 }