Commit bc8a2d9b authored by Dinh Nguyen's avatar Dinh Nguyen Committed by David S. Miller

net: stmmac: socfpga: add additional ocp reset line for Stratix10

The Stratix10 platform has an additional reset line, OCP(Open Core Protocol),
that also needs to get deasserted for the stmmac ethernet controller to work.
Thus we need to update the Kconfig to include ARCH_STRATIX10 in order to build
dwmac-socfpga.

Also, remove the redundant check for the reset controller pointer. The
reset driver already checks for the pointer and returns 0 if the pointer
is NULL.
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 12b03558
...@@ -111,7 +111,7 @@ config DWMAC_ROCKCHIP ...@@ -111,7 +111,7 @@ config DWMAC_ROCKCHIP
config DWMAC_SOCFPGA config DWMAC_SOCFPGA
tristate "SOCFPGA dwmac support" tristate "SOCFPGA dwmac support"
default ARCH_SOCFPGA default ARCH_SOCFPGA
depends on OF && (ARCH_SOCFPGA || COMPILE_TEST) depends on OF && (ARCH_SOCFPGA || ARCH_STRATIX10 || COMPILE_TEST)
select MFD_SYSCON select MFD_SYSCON
help help
Support for ethernet controller on Altera SOCFPGA Support for ethernet controller on Altera SOCFPGA
......
...@@ -55,6 +55,7 @@ struct socfpga_dwmac { ...@@ -55,6 +55,7 @@ struct socfpga_dwmac {
struct device *dev; struct device *dev;
struct regmap *sys_mgr_base_addr; struct regmap *sys_mgr_base_addr;
struct reset_control *stmmac_rst; struct reset_control *stmmac_rst;
struct reset_control *stmmac_ocp_rst;
void __iomem *splitter_base; void __iomem *splitter_base;
bool f2h_ptp_ref_clk; bool f2h_ptp_ref_clk;
struct tse_pcs pcs; struct tse_pcs pcs;
...@@ -262,8 +263,8 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) ...@@ -262,8 +263,8 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
/* Assert reset to the enet controller before changing the phy mode */ /* Assert reset to the enet controller before changing the phy mode */
if (dwmac->stmmac_rst) reset_control_assert(dwmac->stmmac_ocp_rst);
reset_control_assert(dwmac->stmmac_rst); reset_control_assert(dwmac->stmmac_rst);
regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
...@@ -288,8 +289,8 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) ...@@ -288,8 +289,8 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
/* Deassert reset for the phy configuration to be sampled by /* Deassert reset for the phy configuration to be sampled by
* the enet controller, and operation to start in requested mode * the enet controller, and operation to start in requested mode
*/ */
if (dwmac->stmmac_rst) reset_control_deassert(dwmac->stmmac_ocp_rst);
reset_control_deassert(dwmac->stmmac_rst); reset_control_deassert(dwmac->stmmac_rst);
if (phymode == PHY_INTERFACE_MODE_SGMII) { if (phymode == PHY_INTERFACE_MODE_SGMII) {
if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
dev_err(dwmac->dev, "Unable to initialize TSE PCS"); dev_err(dwmac->dev, "Unable to initialize TSE PCS");
...@@ -324,6 +325,15 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) ...@@ -324,6 +325,15 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
goto err_remove_config_dt; goto err_remove_config_dt;
} }
dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
if (IS_ERR(dwmac->stmmac_ocp_rst)) {
ret = PTR_ERR(dwmac->stmmac_ocp_rst);
dev_err(dev, "error getting reset control of ocp %d\n", ret);
goto err_remove_config_dt;
}
reset_control_deassert(dwmac->stmmac_ocp_rst);
ret = socfpga_dwmac_parse_data(dwmac, dev); ret = socfpga_dwmac_parse_data(dwmac, dev);
if (ret) { if (ret) {
dev_err(dev, "Unable to parse OF data\n"); dev_err(dev, "Unable to parse OF data\n");
......
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