Commit bc8ffc2d authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

ARM: dts: sun9i: Add usb clock nodes to a80 dtsi

The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent d67b984b
......@@ -137,6 +137,28 @@ osc32k: osc32k_clk {
clock-output-names = "osc32k";
};
usb_mod_clk: clk@00a08000 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-usb-mod-clk";
reg = <0x00a08000 0x4>;
clocks = <&ahb1_gates 1>;
clock-output-names = "usb0_ahb", "usb_ohci0",
"usb1_ahb", "usb_ohci1",
"usb2_ahb", "usb_ohci2";
};
usb_phy_clk: clk@00a08004 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-usb-phy-clk";
reg = <0x00a08004 0x4>;
clocks = <&ahb1_gates 1>;
clock-output-names = "usb_phy0", "usb_hsic1_480M",
"usb_phy1", "usb_hsic2_480M",
"usb_phy2", "usb_hsic_12M";
};
pll4: clk@0600000c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
......
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