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Commit bd08b0a9 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
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[PATCH] Fix support for the Motorola PrPMC800 

From: Tom Rini <trini@kernel.crashing.org>

Makes the Motorola PrPMC800 platform functional again.  This comes from Randy
Vinson <rvinson@mvista.com>.
parent 51a58c58
Hide whitespace changes
Inline Side-by-side
Showing with 1123 additions and 433 deletions
arch/ppc/Kconfig
View file @ bd08b0a9
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || PRPMC750 || K2
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || PRPMC750 || K2 || PRPMC800
default y
config FORCE
......@@ -622,6 +622,15 @@ config GT64260
depends on EV64260
default y
config NONMONARCH_SUPPORT
bool "Enable Non-Monarch Support"
depends on PRPMC800
config HARRIER
bool
depends on PRPMC800
default y
config EPIC_SERIAL_MODE
bool
depends on 6xx && (LOPEC || SANDPOINT)
......@@ -640,6 +649,10 @@ config CPC710_DATA_GATHERING
bool "Enable CPC710 data gathering"
depends on K2
config HARRIER_STORE_GATHERING
bool "Enable Harrier store gathering"
depends on HARRIER
config MVME5100_IPMC761_PRESENT
bool "MVME5100 configured with an IPMC761"
depends on MVME5100
......
arch/ppc/configs/prpmc800_defconfig
View file @ bd08b0a9
......@@ -4,23 +4,39 @@
CONFIG_MMU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_STANDALONE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
# CONFIG_KALLSYMS is not set
CONFIG_FUTEX=y
# CONFIG_EPOLL is not set
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
#
# Loadable module support
......@@ -33,24 +49,25 @@ CONFIG_OBSOLETE_MODPARM=y
CONFIG_KMOD=y
#
# Platform support
# Processor
#
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
CONFIG_ALTIVEC=y
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
CONFIG_PPC_STD_MMU=y
#
# IBM 4xx options
# Platform options
#
# CONFIG_8260 is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_STD_MMU=y
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
# CONFIG_WILLOW_2 is not set
# CONFIG_WILLOW is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
# CONFIG_EV64260 is not set
......@@ -66,33 +83,31 @@ CONFIG_PRPMC800=y
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_EST8260 is not set
# CONFIG_SBS8260 is not set
# CONFIG_RPX6 is not set
# CONFIG_TQM8260 is not set
CONFIG_PPC_GEN550=y
# CONFIG_NONMONARCH_SUPPORT is not set
CONFIG_HARRIER=y
# CONFIG_HARRIER_STORE_GATHERING is not set
# CONFIG_SMP is not set
# CONFIG_PREEMPT is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_HIGHMEM is not set
CONFIG_KERNEL_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# General setup
# Bus options
#
# CONFIG_HIGHMEM is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_KERNEL_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PCI_LEGACY_PROC is not set
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
# CONFIG_PPC601_SYNC_FIX is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# Advanced setup
......@@ -108,15 +123,27 @@ CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Device Drivers
#
#
# Generic Driver Options
#
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Block devices
......@@ -128,31 +155,100 @@ CONFIG_BOOT_LOAD=0x00800000
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_CARMEL is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
# CONFIG_LBD is not set
#
# Multi-device support (RAID and LVM)
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_MD is not set
# CONFIG_IDE is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# SCSI device support
#
CONFIG_SCSI=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI Transport Attributes
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
#
# SCSI low-level drivers
#
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INIA100 is not set
CONFIG_SCSI_SYM53C8XX_2=y
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
CONFIG_SCSI_QLA2XXX=y
# CONFIG_SCSI_QLA21XX is not set
# CONFIG_SCSI_QLA22XX is not set
# CONFIG_SCSI_QLA2300 is not set
# CONFIG_SCSI_QLA2322 is not set
# CONFIG_SCSI_QLA6312 is not set
# CONFIG_SCSI_QLA6322 is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
#
# SCSI support
# Multi-device support (RAID and LVM)
#
# CONFIG_SCSI is not set
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
......@@ -161,6 +257,10 @@ CONFIG_BLK_DEV_INITRD=y
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
#
# Networking support
#
......@@ -172,8 +272,6 @@ CONFIG_NET=y
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK_DEV is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
......@@ -187,71 +285,24 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
#
# IP: Netfilter Configuration
#
CONFIG_IP_NF_CONNTRACK=m
CONFIG_IP_NF_FTP=m
CONFIG_IP_NF_IRC=m
# CONFIG_IP_NF_TFTP is not set
# CONFIG_IP_NF_AMANDA is not set
# CONFIG_IP_NF_QUEUE is not set
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_LIMIT=m
CONFIG_IP_NF_MATCH_MAC=m
CONFIG_IP_NF_MATCH_PKTTYPE=m
CONFIG_IP_NF_MATCH_MARK=m
CONFIG_IP_NF_MATCH_MULTIPORT=m
CONFIG_IP_NF_MATCH_TOS=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_DSCP=m
CONFIG_IP_NF_MATCH_AH_ESP=m
CONFIG_IP_NF_MATCH_LENGTH=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_MATCH_TCPMSS=m
CONFIG_IP_NF_MATCH_HELPER=m
CONFIG_IP_NF_MATCH_STATE=m
CONFIG_IP_NF_MATCH_CONNTRACK=m
CONFIG_IP_NF_MATCH_UNCLEAN=m
CONFIG_IP_NF_MATCH_OWNER=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_MIRROR=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_REDIRECT=m
# CONFIG_IP_NF_NAT_LOCAL is not set
# CONFIG_IP_NF_NAT_SNMP_BASIC is not set
CONFIG_IP_NF_NAT_IRC=m
CONFIG_IP_NF_NAT_FTP=m
# CONFIG_IP_NF_MANGLE is not set
# CONFIG_IP_NF_TARGET_LOG is not set
CONFIG_IP_NF_TARGET_ULOG=m
CONFIG_IP_NF_TARGET_TCPMSS=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_COMPAT_IPCHAINS=m
# CONFIG_IP_NF_COMPAT_IPFWADM is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
# CONFIG_NETFILTER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
......@@ -269,17 +320,21 @@ CONFIG_IPV6_SCTP__=y
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
......@@ -301,6 +356,7 @@ CONFIG_NET_PCI=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
CONFIG_EEPRO100=y
# CONFIG_EEPRO100_PIO is not set
......@@ -333,60 +389,54 @@ CONFIG_EEPRO100=y
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_S2IO is not set
#
# Wireless LAN (non-hamradio)
# Token Ring devices
#
# CONFIG_NET_RADIO is not set
# CONFIG_TR is not set
#
# Token Ring devices (depends on LLC=y)
# Wireless LAN (non-hamradio)
#
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
#
# ISDN subsystem
#
# CONFIG_ISDN_BOOL is not set
#
# Graphics support
#
# CONFIG_FB is not set
# CONFIG_ISDN is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Telephony Support
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_PHONE is not set
#
# Input device support
#
# CONFIG_INPUT is not set
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
......@@ -394,18 +444,21 @@ CONFIG_EEPRO100=y
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_SERIO is not set
# CONFIG_SERIO_I8042 is not set
#
# Input Device Drivers
#
#
# Macintosh device drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
......@@ -413,6 +466,7 @@ CONFIG_SOUND_GAMEPORT=y
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
......@@ -421,26 +475,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
CONFIG_BUSMOUSE=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_QIC02_TAPE is not set
#
......@@ -466,7 +502,15 @@ CONFIG_GEN_RTC=y
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Misc devices
#
#
# Multimedia devices
......@@ -478,6 +522,26 @@ CONFIG_GEN_RTC=y
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# File systems
#
......@@ -515,10 +579,12 @@ CONFIG_FS_MBCACHE=y
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
......@@ -527,6 +593,7 @@ CONFIG_RAMFS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
......@@ -543,12 +610,13 @@ CONFIG_RAMFS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
......@@ -563,20 +631,9 @@ CONFIG_SUNRPC=y
CONFIG_MSDOS_PARTITION=y
#
# Sound
# Native Language Support
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
# CONFIG_NLS is not set
#
# Library routines
......@@ -587,8 +644,7 @@ CONFIG_MSDOS_PARTITION=y
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_KALLSYMS is not set
CONFIG_SERIAL_TEXT_DEBUG=y
# CONFIG_SERIAL_TEXT_DEBUG is not set
#
# Security options
......
arch/ppc/platforms/Makefile
View file @ bd08b0a9
......@@ -43,7 +43,7 @@ obj-$(CONFIG_PCORE) += pcore.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SPRUCE) += spruce.o
......
arch/ppc/platforms/prpmc800_setup.c → arch/ppc/platforms/prpmc800.c
View file @ bd08b0a9
/*
* arch/ppc/platforms/prpmc800.c
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -25,66 +26,274 @@
#include <linux/seq_file.h>
#include <linux/ide.h>
#include <linux/root_dev.h>
#include <linux/harrier_defs.h>
#include <asm/byteorder.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <platforms/prpmc800.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/bootinfo.h>
#include <asm/harrier.h>
#include "prpmc800.h"
#define HARRIER_REVI_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_REVI_OFF)
#define HARRIER_UCTL_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_UCTL_OFF)
#define HARRIER_MISC_CSR_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF)
#define HARRIER_IFEVP_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF)
#define HARRIER_IFEDE_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF)
#define HARRIER_MISC_CSR_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF)
#define HARRIER_IFEVP_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF)
#define HARRIER_IFEDE_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF)
#define HARRIER_FEEN_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEEN_OFF)
#define HARRIER_FEMA_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEMA_OFF)
extern void prpmc800_find_bridges(void);
#define HARRIER_VENI_REG (PRPMC800_HARRIER_XCSR_BASE + HARRIER_VENI_OFF)
#define HARRIER_MISC_CSR (PRPMC800_HARRIER_XCSR_BASE + \
HARRIER_MISC_CSR_OFF)
#define MONARCH (monarch != 0)
#define NON_MONARCH (monarch == 0)
extern int mpic_init(void);
extern unsigned long loops_per_jiffy;
extern void gen550_progress(char *, unsigned short);
static int monarch = 0;
static int found_self = 0;
static int self = 0;
static u_char prpmc800_openpic_initsenses[] __initdata =
{
1, /* PRPMC800_INT_HOSTINT0 */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_DEBUGINT */
1, /* PRPMC800_INT_HARRIER_WDT */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_HOSTINT1 */
1, /* PRPMC800_INT_HOSTINT2 */
1, /* PRPMC800_INT_HOSTINT3 */
1, /* PRPMC800_INT_PMC_INTA */
1, /* PRPMC800_INT_PMC_INTB */
1, /* PRPMC800_INT_PMC_INTC */
1, /* PRPMC800_INT_PMC_INTD */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_UNUSED */
1, /* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_DEBUGINT */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_WDT */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT3 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTA */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTB */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTC */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTD */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */
};
/*
* Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
* Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
*/
static inline int
prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
{0, 0, 0, 0}, /* IDSEL 15 - unused */
{10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
{10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
{11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
{0, 0, 0, 0}, /* IDSEL 19 - unused */
{9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
{11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
{12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
};
const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
static int
prpmc800_show_cpuinfo(struct seq_file *m)
prpmc_read_config_dword(struct pci_controller *hose, u8 bus, u8 devfn,
int offset, u32 * val)
{
/* paranoia */
if ((hose == NULL) ||
(hose->cfg_addr == NULL) || (hose->cfg_data == NULL))
return PCIBIOS_DEVICE_NOT_FOUND;
out_be32(hose->cfg_addr, ((offset & 0xfc) << 24) | (devfn << 16)
| ((bus - hose->bus_offset) << 8) | 0x80);
*val = in_le32((u32 *) (hose->cfg_data + (offset & 3)));
return PCIBIOS_SUCCESSFUL;
}
#define HARRIER_PCI_VEND_DEV_ID (PCI_VENDOR_ID_MOTOROLA | \
(PCI_DEVICE_ID_MOTOROLA_HARRIER << 16))
static int prpmc_self(u8 bus, u8 devfn)
{
/*
* Harriers always view themselves as being on bus 0. If we're not
* looking at bus 0, we're not going to find ourselves.
*/
if (bus != 0)
return PCIBIOS_DEVICE_NOT_FOUND;
else {
int result;
int val;
struct pci_controller *hose;
hose = pci_bus_to_hose(bus);
/* See if target device is a Harrier */
result = prpmc_read_config_dword(hose, bus, devfn,
PCI_VENDOR_ID, &val);
if ((result != PCIBIOS_SUCCESSFUL) ||
(val != HARRIER_PCI_VEND_DEV_ID))
return PCIBIOS_DEVICE_NOT_FOUND;
/*
* LBA bit is set if target Harrier == initiating Harrier
* (i.e. if we are reading our own PCI header).
*/
result = prpmc_read_config_dword(hose, bus, devfn,
HARRIER_LBA_OFF, &val);
if ((result != PCIBIOS_SUCCESSFUL) ||
((val & HARRIER_LBA_MSK) != HARRIER_LBA_MSK))
return PCIBIOS_DEVICE_NOT_FOUND;
/* It's us, save our location for later */
self = devfn;
found_self = 1;
return PCIBIOS_SUCCESSFUL;
}
}
static int prpmc_exclude_device(u8 bus, u8 devfn)
{
/*
* Monarch is allowed to access all PCI devices. Non-monarch is
* only allowed to access its own Harrier.
*/
if (MONARCH)
return PCIBIOS_SUCCESSFUL;
if (found_self)
if ((bus == 0) && (devfn == self))
return PCIBIOS_SUCCESSFUL;
else
return PCIBIOS_DEVICE_NOT_FOUND;
else
return prpmc_self(bus, devfn);
}
void __init prpmc800_find_bridges(void)
{
struct pci_controller *hose;
int host_bridge;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
ppc_md.pci_exclude_device = prpmc_exclude_device;
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
setup_indirect_pci(hose,
PRPMC800_PCI_CONFIG_ADDR, PRPMC800_PCI_CONFIG_DATA);
/* Get host bridge vendor/dev id */
host_bridge = in_be32((uint *) (HARRIER_VENI_REG));
if (host_bridge != HARRIER_VEND_DEV_ID) {
printk(KERN_CRIT "Host bridge 0x%x not supported\n",
host_bridge);
return;
}
monarch = in_be32((uint *) HARRIER_MISC_CSR) & HARRIER_SYSCON;
printk(KERN_INFO "Running as %s.\n",
MONARCH ? "Monarch" : "Non-Monarch");
hose->io_space.start = PRPMC800_PCI_IO_START;
hose->io_space.end = PRPMC800_PCI_IO_END;
hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE;
hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
PRPMC800_PCI_IO_START, PRPMC800_PCI_IO_END,
IORESOURCE_IO, "PCI host bridge");
if (MONARCH) {
hose->mem_space.start = PRPMC800_PCI_MEM_START;
hose->mem_space.end = PRPMC800_PCI_MEM_END;
pci_init_resource(&hose->mem_resources[0],
PRPMC800_PCI_MEM_START,
PRPMC800_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
if (harrier_init(hose,
PRPMC800_HARRIER_XCSR_BASE,
PRPMC800_PROC_PCI_MEM_START,
PRPMC800_PROC_PCI_MEM_END,
PRPMC800_PROC_PCI_IO_START,
PRPMC800_PROC_PCI_IO_END,
PRPMC800_HARRIER_MPIC_BASE) != 0)
printk(KERN_CRIT "Could not initialize HARRIER "
"bridge\n");
harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
harrier_wait_eready(PRPMC800_HARRIER_XCSR_BASE);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
} else {
pci_init_resource(&hose->mem_resources[0],
PRPMC800_NM_PCI_MEM_START,
PRPMC800_NM_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
hose->mem_space.start = PRPMC800_NM_PCI_MEM_START;
hose->mem_space.end = PRPMC800_NM_PCI_MEM_END;
if (harrier_init(hose,
PRPMC800_HARRIER_XCSR_BASE,
PRPMC800_NM_PROC_PCI_MEM_START,
PRPMC800_NM_PROC_PCI_MEM_END,
PRPMC800_PROC_PCI_IO_START,
PRPMC800_PROC_PCI_IO_END,
PRPMC800_HARRIER_MPIC_BASE) != 0)
printk(KERN_CRIT "Could not initialize HARRIER "
"bridge\n");
harrier_setup_nonmonarch(PRPMC800_HARRIER_XCSR_BASE,
HARRIER_ITSZ_1MB);
harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
}
}
static int prpmc800_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: PrPMC800\n");
return 0;
}
static void __init
prpmc800_setup_arch(void)
static void __init prpmc800_setup_arch(void)
{
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
loops_per_jiffy = 50000000 / HZ;
/* Lookup PCI host bridges */
prpmc800_find_bridges();
......@@ -104,18 +313,14 @@ prpmc800_setup_arch(void)
conswitchp = &dummy_con;
#endif
OpenPIC_InitSenses = prpmc800_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses);
printk("PrPMC800 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
printk(KERN_INFO "Port by MontaVista Software, Inc. "
"(source@mvista.com)\n");
}
/*
* Compute the PrPMC800's tbl frequency using the baud clock as a reference.
*/
static void __init
prpmc800_calibrate_decr(void)
static void __init prpmc800_calibrate_decr(void)
{
unsigned long tbl_start, tbl_end;
unsigned long current_state, old_state, tb_ticks_per_second;
......@@ -125,9 +330,9 @@ prpmc800_calibrate_decr(void)
harrier_revision = readb(HARRIER_REVI_REG);
if (harrier_revision < 2) {
/* XTAL64 was broken in harrier revision 1 */
printk("time_init: Harrier revision %d, assuming 100 Mhz bus\n",
harrier_revision);
tb_ticks_per_second = 100000000/4;
printk(KERN_INFO "time_init: Harrier revision %d, assuming "
"100 Mhz bus\n", harrier_revision);
tb_ticks_per_second = 100000000 / 4;
tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
return;
......@@ -143,9 +348,8 @@ prpmc800_calibrate_decr(void)
/* Find the first edge of the baud clock */
old_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
do {
current_state = readb(HARRIER_UCTL_REG) &
HARRIER_XTAL64_MASK;
} while(old_state == current_state);
current_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
} while (old_state == current_state);
old_state = current_state;
......@@ -159,8 +363,8 @@ prpmc800_calibrate_decr(void)
do {
do {
current_state = readb(HARRIER_UCTL_REG) &
HARRIER_XTAL64_MASK;
} while(old_state == current_state);
HARRIER_XTAL64_MASK;
} while (old_state == current_state);
old_state = current_state;
} while (--count);
......@@ -173,128 +377,76 @@ prpmc800_calibrate_decr(void)
tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
}
static void
prpmc800_restart(char *cmd)
static void prpmc800_restart(char *cmd)
{
ulong temp;
local_irq_disable();
writeb(HARRIER_RSTOUT_MASK, HARRIER_MISC_CSR_REG);
while(1);
temp = in_be32((uint *) HARRIER_MISC_CSR_REG);
temp |= HARRIER_RSTOUT;
out_be32((uint *) HARRIER_MISC_CSR_REG, temp);
while (1) ;
}
static void
prpmc800_halt(void)
static void prpmc800_halt(void)
{
local_irq_disable();
while (1);
while (1) ;
}
static void
prpmc800_power_off(void)
static void prpmc800_power_off(void)
{
prpmc800_halt();
}
static void __init
prpmc800_init_IRQ(void)
static void __init prpmc800_init_IRQ(void)
{
openpic_init(1, 0, 0, -1);
OpenPIC_InitSenses = prpmc800_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses);
#define PRIORITY 15
#define VECTOR 16
#define PROCESSOR 0
/* initialize the harrier's internal interrupt priority 15, irq 1 */
out_be32((u32 *)HARRIER_IFEVP_REG, (PRIORITY<<16) | VECTOR);
out_be32((u32 *)HARRIER_IFEDE_REG, (1<<PROCESSOR));
/* Setup external interrupt sources. */
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
/* Setup internal UART interrupt source. */
openpic_set_sources(16, 1, OpenPIC_Addr + 0x10200);
/* Do the MPIC initialization based on the above settings. */
openpic_init(0);
/* enable functional exceptions for uarts and abort */
out_8((u8 *)HARRIER_FEEN_REG, (HARRIER_FE_UA0|HARRIER_FE_UA1));
out_8((u8 *)HARRIER_FEMA_REG, ~(HARRIER_FE_UA0|HARRIER_FE_UA1));
out_8((u8 *) HARRIER_FEEN_REG, (HARRIER_FE_UA0 | HARRIER_FE_UA1));
out_8((u8 *) HARRIER_FEMA_REG, ~(HARRIER_FE_UA0 | HARRIER_FE_UA1));
}
/*
* Set BAT 3 to map 0xf0000000 to end of physical memory space.
*/
static __inline__ void
prpmc800_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set)
{
__asm__ __volatile__(
" lis %0,0xf000\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x1ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
void
prpmc800_progress(char *s, unsigned short hex)
static __inline__ void prpmc800_set_bat(void)
{
volatile char c;
volatile unsigned char *com_port;
volatile unsigned char *com_port_lsr;
com_port = (volatile unsigned char *) rs_table[0].port;
com_port_lsr = com_port + UART_LSR;
while ((c = *s++) != 0) {
while ((*com_port_lsr & UART_LSR_THRE) == 0)
;
*com_port = c;
if (c == '\n') {
while ((*com_port_lsr & UART_LSR_THRE) == 0)
;
*com_port = '\r';
}
}
mb();
mtspr(DBAT1U, 0xf0001ffe);
mtspr(DBAT1L, 0xf000002a);
mb();
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
/*
* We need to read the Harrier memory controller
* to properly determine this value
*/
static unsigned long __init
prpmc800_find_end_of_memory(void)
static unsigned long __init prpmc800_find_end_of_memory(void)
{
/* Cover the harrier registers with a BAT */
prpmc800_set_bat();
/* Read the memory size from the Harrier XCSR */
return harrier_get_mem_size(PRPMC800_HARRIER_XCSR_BASE);
}
static void __init
prpmc800_map_io(void)
static void __init prpmc800_map_io(void)
{
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
......@@ -304,26 +456,26 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
isa_mem_base = PRPMC800_ISA_MEM_BASE;
pci_dram_offset = PRPMC800_PCI_DRAM_OFFSET;
ppc_md.setup_arch = prpmc800_setup_arch;
ppc_md.show_cpuinfo = prpmc800_show_cpuinfo;
ppc_md.init_IRQ = prpmc800_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.setup_arch = prpmc800_setup_arch;
ppc_md.show_cpuinfo = prpmc800_show_cpuinfo;
ppc_md.init_IRQ = prpmc800_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.find_end_of_memory = prpmc800_find_end_of_memory;
ppc_md.setup_io_mappings = prpmc800_map_io;
ppc_md.restart = prpmc800_restart;
ppc_md.power_off = prpmc800_power_off;
ppc_md.halt = prpmc800_halt;
ppc_md.restart = prpmc800_restart;
ppc_md.power_off = prpmc800_power_off;
ppc_md.halt = prpmc800_halt;
/* PrPMC800 has no timekeeper part */
ppc_md.time_init = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.set_rtc_time = NULL;
ppc_md.calibrate_decr = prpmc800_calibrate_decr;
ppc_md.time_init = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.set_rtc_time = NULL;
ppc_md.calibrate_decr = prpmc800_calibrate_decr;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = prpmc800_progress;
#else /* !CONFIG_SERIAL_TEXT_DEBUG */
ppc_md.progress = gen550_progress;
#else /* !CONFIG_SERIAL_TEXT_DEBUG */
ppc_md.progress = NULL;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
}
arch/ppc/platforms/prpmc800.h
View file @ bd08b0a9
......@@ -5,21 +5,22 @@
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
/*
* From Processor to PCI:
* PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
* PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
* Copyright 2001 MontaVista Software Inc.
*
* From PCI to Processor:
* System Memory: 0x00000000 -> 0x00000000
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* From Processor to PCI:
* PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
* PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI to Processor:
* System Memory: 0x00000000 -> 0x00000000
*/
#ifndef __ASMPPC_PRPMC800_H
#define __ASMPPC_PRPMC800_H
......@@ -37,18 +38,29 @@
#define PRPMC800_PCI_MEM_START 0x80000000U
#define PRPMC800_PCI_MEM_END 0x9fffffffU
#define PRPMC800_NM_PROC_PCI_MEM_START 0x40000000U
#define PRPMC800_NM_PROC_PCI_MEM_END 0xdfffffffU
#define PRPMC800_NM_PCI_MEM_START 0x40000000U
#define PRPMC800_NM_PCI_MEM_END 0xdfffffffU
#define PRPMC800_PCI_DRAM_OFFSET 0x00000000U
#define PRPMC800_PCI_PHY_MEM_OFFSET 0x00000000U
#define PRPMC800_ISA_IO_BASE PRPMC800_PROC_PCI_IO_START
#define PRPMC800_ISA_MEM_BASE 0x00000000U
#define PRPMC800_HARRIER_XCSR_BASE 0xfeff0000
#define PRPMC800_HARRIER_XCSR_BASE HARRIER_DEFAULT_XCSR_BASE
#define PRPMC800_HARRIER_MPIC_BASE 0xff000000
#define PRPMC800_SERIAL_1 0xfeff00c0
#define PRPMC800_BASE_BAUD 1843200
/*
* interrupt vector number and priority for harrier internal interrupt
* sources
*/
#define PRPMC800_INT_IRQ 16
#define PRPMC800_INT_PRI 15
#endif /* __ASMPPC_PRPMC800_H */
#endif /* __ASMPPC_PRPMC800_H */
arch/ppc/platforms/prpmc800_pci.c deleted 100644 → 0
View file @ 51a58c58
/*
* arch/ppc/platforms/prpmc800_pci.c
*
* PCI support for Motorola PrPMC800
*
* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <platforms/prpmc800.h>
#include <asm/harrier.h>
/*
* Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
* Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
*/
static inline int
prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
{0, 0, 0, 0}, /* IDSEL 15 - unused */
{10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
{10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
{11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
{0, 0, 0, 0}, /* IDSEL 19 - unused */
{9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
{11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
{12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
};
const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
void __init
prpmc800_find_bridges(void)
{
struct pci_controller* hose;
int host_bridge;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
PRPMC800_PCI_IO_START,
PRPMC800_PCI_IO_END,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
PRPMC800_PCI_MEM_START,
PRPMC800_PCI_MEM_END,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = PRPMC800_PCI_IO_START;
hose->io_space.end = PRPMC800_PCI_IO_END;
hose->mem_space.start = PRPMC800_PCI_MEM_START;
hose->mem_space.end = PRPMC800_PCI_MEM_END;
hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE;
setup_indirect_pci(hose,
PRPMC800_PCI_CONFIG_ADDR,
PRPMC800_PCI_CONFIG_DATA);
/* Get host bridge vendor/dev id */
early_read_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_VENDOR_ID,
&host_bridge);
switch (host_bridge) {
case HARRIER_VEND_DEV_ID:
if (harrier_init(hose,
PRPMC800_HARRIER_XCSR_BASE,
PRPMC800_PROC_PCI_MEM_START,
PRPMC800_PROC_PCI_MEM_END,
PRPMC800_PROC_PCI_IO_START,
PRPMC800_PROC_PCI_IO_END,
PRPMC800_HARRIER_MPIC_BASE) != 0) {
printk("Could not initialize HARRIER bridge\n");
}
break;
default:
printk("Host bridge 0x%x not supported\n", host_bridge);
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
}
arch/ppc/syslib/Makefile
View file @ bd08b0a9
......@@ -57,8 +57,8 @@ obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o i8259.o \
indirect_pci.o todc_time.o pci_auto.o
obj-$(CONFIG_PRPMC750) += open_pic.o indirect_pci.o pci_auto.o \
hawk_common.o
obj-$(CONFIG_PRPMC800) += open_pic.o indirect_pci.o pci_auto.o \
hawk_common.o harrier.o
obj-$(CONFIG_HARRIER) += harrier.o
obj-$(CONFIG_PRPMC800) += open_pic.o indirect_pci.o pci_auto.o
obj-$(CONFIG_SANDPOINT) += i8259.o open_pic.o pci_auto.o todc_time.o
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
......
arch/ppc/syslib/harrier.c
View file @ bd08b0a9
......@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/harrier_defs.h>
#include <asm/byteorder.h>
#include <asm/io.h>
......@@ -23,6 +24,93 @@
#include <asm/open_pic.h>
#include <asm/harrier.h>
/* define defaults for inbound windows */
#define HARRIER_ITAT_DEFAULT (HARRIER_ITAT_ENA | \
HARRIER_ITAT_MEM | \
HARRIER_ITAT_WPE | \
HARRIER_ITAT_GBL)
#define HARRIER_MPAT_DEFAULT (HARRIER_ITAT_ENA | \
HARRIER_ITAT_MEM | \
HARRIER_ITAT_WPE | \
HARRIER_ITAT_GBL)
/*
* Initialize the inbound window size on a non-monarch harrier.
*/
void __init harrier_setup_nonmonarch(uint ppc_reg_base, uint in0_size)
{
u16 temps;
u32 temp;
if (in0_size > HARRIER_ITSZ_2GB) {
printk
("harrier_setup_nonmonarch: Invalid window size code %d\n",
in0_size);
return;
}
/* Clear the PCI memory enable bit. If we don't, then when the
* inbound windows are enabled below, the corresponding BARs will be
* "live" and start answering to PCI memory reads from their default
* addresses (0x0), which overlap with system RAM.
*/
temps = in_le16((u16 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(PCI_COMMAND)));
temps &= ~(PCI_COMMAND_MEMORY);
out_le16((u16 *) (ppc_reg_base + HARRIER_XCSR_CONFIG(PCI_COMMAND)),
temps);
/* Setup a non-prefetchable inbound window */
out_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_ITSZ0_OFF)), in0_size);
temp = in_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)));
temp &= ~HARRIER_ITAT_PRE;
temp |= HARRIER_ITAT_DEFAULT;
out_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)), temp);
/* Enable the message passing block */
temp = in_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)));
temp |= HARRIER_MPAT_DEFAULT;
out_le32((u32 *) (ppc_reg_base +
HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)), temp);
}
void __init harrier_release_eready(uint ppc_reg_base)
{
ulong temp;
/*
* Set EREADY to allow the line to be pulled up after everyone is
* ready.
*/
temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
temp |= HARRIER_EREADY;
out_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF), temp);
}
void __init harrier_wait_eready(uint ppc_reg_base)
{
ulong temp;
/*
* Poll the ERDYS line until it goes high to indicate that all
* non-monarch PrPMCs are ready for bus enumeration (or that there are
* no PrPMCs present).
*/
/* FIXME: Add a timeout of some kind to prevent endless waits. */
do {
temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
} while (!(temp & HARRIER_ERDYS));
}
/*
* Initialize the Motorola MCG Harrier host bridge.
*
......@@ -40,25 +128,25 @@ harrier_init(struct pci_controller *hose,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base)
ulong processor_pci_io_end, ulong processor_mpic_base)
{
uint addr, offset;
uint addr, offset;
/*
* Some sanity checks...
*/
if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) ||
((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) {
if (((processor_pci_mem_start & 0xffff0000) != processor_pci_mem_start)
|| ((processor_pci_io_start & 0xffff0000) !=
processor_pci_io_start)) {
printk("harrier_init: %s\n",
"PPC to PCI mappings must start on 64 KB boundaries");
"PPC to PCI mappings must start on 64 KB boundaries");
return -1;
}
if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) ||
((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) {
if (((processor_pci_mem_end & 0x0000ffff) != 0x0000ffff) ||
((processor_pci_io_end & 0x0000ffff) != 0x0000ffff)) {
printk("harrier_init: PPC to PCI mappings %s\n",
"must end just before a 64 KB boundaries");
"must end just before a 64 KB boundaries");
return -1;
}
......@@ -67,19 +155,19 @@ harrier_init(struct pci_controller *hose,
((processor_pci_io_end - processor_pci_io_start) !=
(hose->io_space.end - hose->io_space.start))) {
printk("harrier_init: %s\n",
"PPC and PCI memory or I/O space sizes don't match");
"PPC and PCI memory or I/O space sizes don't match");
return -1;
}
if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
printk("harrier_init: %s\n",
"MPIC address must start on 256 KB boundary");
"MPIC address must start on 256 KB boundary");
return -1;
}
if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
printk("harrier_init: %s\n",
"pci_dram_offset must be multiple of 64 KB");
"pci_dram_offset must be multiple of 64 KB");
return -1;
}
......@@ -89,28 +177,32 @@ harrier_init(struct pci_controller *hose,
* the PCI bus.
*
* Note: Don't need to 'AND' start/end addresses with 0xffff0000
* because sanity check above ensures that they are properly
* aligned.
* because sanity check above ensures that they are properly
* aligned.
*/
/* Set up PPC->PCI Mem mapping */
addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
#ifdef CONFIG_HARRIER_STORE_GATHERING
offset = (hose->mem_space.start - processor_pci_mem_start) | 0x9a;
#else
offset = (hose->mem_space.start - processor_pci_mem_start) | 0x92;
out_be32((uint *)(ppc_reg_base + HARRIER_OTAD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + HARRIER_OTOF0_OFF), offset);
#endif
out_be32((uint *) (ppc_reg_base + HARRIER_OTAD0_OFF), addr);
out_be32((uint *) (ppc_reg_base + HARRIER_OTOF0_OFF), offset);
/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
addr = processor_pci_io_start | (processor_pci_io_end >> 16);
offset = (hose->io_space.start - processor_pci_io_start) | 0x80;
out_be32((uint *)(ppc_reg_base + HARRIER_OTAD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + HARRIER_OTOF1_OFF), offset);
out_be32((uint *) (ppc_reg_base + HARRIER_OTAD1_OFF), addr);
out_be32((uint *) (ppc_reg_base + HARRIER_OTOF1_OFF), offset);
/* Enable MPIC */
OpenPIC_Addr = (void *)processor_mpic_base;
addr = (processor_mpic_base >> 16) | 1;
out_be16((ushort *)(ppc_reg_base + HARRIER_MBAR_OFF), addr);
out_8((u_char *)(ppc_reg_base + HARRIER_MPIC_CSR_OFF),
HARRIER_MPIC_OPI_ENABLE);
out_be16((ushort *) (ppc_reg_base + HARRIER_MBAR_OFF), addr);
out_8((u_char *) (ppc_reg_base + HARRIER_MPIC_CSR_OFF),
HARRIER_MPIC_OPI_ENABLE);
return 0;
}
......@@ -127,22 +219,22 @@ harrier_init(struct pci_controller *hose,
#define MB (1024*1024UL)
static uint harrier_size_table[] __initdata = {
0 * MB, /* 0 ==> 0 MB */
32 * MB, /* 1 ==> 32 MB */
64 * MB, /* 2 ==> 64 MB */
64 * MB, /* 3 ==> 64 MB */
128 * MB, /* 4 ==> 128 MB */
128 * MB, /* 5 ==> 128 MB */
128 * MB, /* 6 ==> 128 MB */
256 * MB, /* 7 ==> 256 MB */
256 * MB, /* 8 ==> 256 MB */
256 * MB, /* 9 ==> 256 MB */
512 * MB, /* a ==> 512 MB */
512 * MB, /* b ==> 512 MB */
512 * MB, /* c ==> 512 MB */
1024 * MB, /* d ==> 1024 MB */
1024 * MB, /* e ==> 1024 MB */
2048 * MB, /* f ==> 2048 MB */
0 * MB, /* 0 ==> 0 MB */
32 * MB, /* 1 ==> 32 MB */
64 * MB, /* 2 ==> 64 MB */
64 * MB, /* 3 ==> 64 MB */
128 * MB, /* 4 ==> 128 MB */
128 * MB, /* 5 ==> 128 MB */
128 * MB, /* 6 ==> 128 MB */
256 * MB, /* 7 ==> 256 MB */
256 * MB, /* 8 ==> 256 MB */
256 * MB, /* 9 ==> 256 MB */
512 * MB, /* a ==> 512 MB */
512 * MB, /* b ==> 512 MB */
512 * MB, /* c ==> 512 MB */
1024 * MB, /* d ==> 1024 MB */
1024 * MB, /* e ==> 1024 MB */
2048 * MB, /* f ==> 2048 MB */
};
/*
......@@ -152,23 +244,22 @@ static uint harrier_size_table[] __initdata = {
* memory. Assumes that the memory controller registers are already mapped
* into virtual memory--too early to use ioremap().
*/
unsigned long __init
harrier_get_mem_size(uint xcsr_base)
unsigned long __init harrier_get_mem_size(uint xcsr_base)
{
ulong last_addr;
int i;
uint vend_dev_id;
uint *size_table;
uint val;
uint *csrp;
uint size;
int size_table_entries;
ulong last_addr;
int i;
uint vend_dev_id;
uint *size_table;
uint val;
uint *csrp;
uint size;
int size_table_entries;
vend_dev_id = in_be32((uint *)xcsr_base + PCI_VENDOR_ID);
vend_dev_id = in_be32((uint *) xcsr_base + PCI_VENDOR_ID);
if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
printk("harrier_get_mem_size: %s (0x%x)\n",
"Not a Motorola Memory Controller", vend_dev_id);
"Not a Motorola Memory Controller", vend_dev_id);
return 0;
}
......@@ -177,18 +268,17 @@ harrier_get_mem_size(uint xcsr_base)
if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HARRIER) {
size_table = harrier_size_table;
size_table_entries = sizeof(harrier_size_table) /
sizeof(harrier_size_table[0]);
}
else {
sizeof(harrier_size_table[0]);
} else {
printk("harrier_get_mem_size: %s (0x%x)\n",
"Not a Harrier", vend_dev_id);
"Not a Harrier", vend_dev_id);
return 0;
}
last_addr = 0;
csrp = (uint *)(xcsr_base + HARRIER_SDBA_OFF);
for (i=0; i<8; i++) {
csrp = (uint *) (xcsr_base + HARRIER_SDBA_OFF);
for (i = 0; i < 8; i++) {
val = in_be32(csrp++);
if (val & 0x100) { /* If enabled */
......@@ -198,8 +288,8 @@ harrier_get_mem_size(uint xcsr_base)
break; /* Register not set correctly */
}
size = size_table[size];
val &= ~(size-1);
val &= ~(size - 1);
val += size;
if (val > last_addr) {
......
include/asm-ppc/harrier.h
View file @ bd08b0a9
/*
* include/asm-ppc/harrier.h
* arch/ppc/kernel/harrier.h
*
* Definitions for Motorola MCG Harrier North Bridge & Memory controller
*
* Author: Dale Farnsworth
* dale.farnsworth@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
* Modified by: Randy Vinson
* rvinson@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASMPPC_HARRIER_H
#define __ASMPPC_HARRIER_H
#include <linux/types.h>
#include <asm/pci-bridge.h>
#define HARRIER_VEND_DEV_ID 0x480b1057
/*
* Define outbound register offsets.
*/
#define HARRIER_OTAD0_OFF 0x220
#define HARRIER_OTOF0_OFF 0x224
#define HARRIER_OTAD1_OFF 0x228
#define HARRIER_OTOF1_OFF 0x22c
#define HARRIER_OTAD2_OFF 0x230
#define HARRIER_OTOF2_OFF 0x234
#define HARRIER_OTAD3_OFF 0x238
#define HARRIER_OTOF3_OFF 0x23c
/*
* Define inbound register offsets.
*/
#define HARRIER_ITSZ0_OFF 0x348
#define HARRIER_ITSZ1_OFF 0x350
#define HARRIER_ITSZ2_OFF 0x358
#define HARRIER_ITSZ3_OFF 0x360
/*
* Define the Memory Controller register offsets.
*/
#define HARRIER_SDBA_OFF 0x110
#define HARRIER_SDBB_OFF 0x114
#define HARRIER_SDBC_OFF 0x118
#define HARRIER_SDBD_OFF 0x11c
#define HARRIER_SDBE_OFF 0x120
#define HARRIER_SDBF_OFF 0x124
#define HARRIER_SDBG_OFF 0x128
#define HARRIER_SDBH_OFF 0x12c
#define HARRIER_SDB_ENABLE 0x00000100
#define HARRIER_SDB_SIZE_MASK 0xf
#define HARRIER_SDB_SIZE_SHIFT 16
#define HARRIER_SDB_BASE_MASK 0xff
#define HARRIER_SDB_BASE_SHIFT 24
#define HARRIER_SERIAL_0_OFF 0xc0
#define HARRIER_REVI_OFF 0x05
#define HARRIER_UCTL_OFF 0xd0
#define HARRIER_XTAL64_MASK 0x02
#define HARRIER_MISC_CSR_OFF 0x1c
#define HARRIER_RSTOUT_MASK 0x01
#define HARRIER_MBAR_OFF 0xe0
#define HARRIER_MPIC_CSR_OFF 0xe4
#define HARRIER_MPIC_OPI_ENABLE 0x40
#define HARRIER_MPIC_IFEVP_OFF 0x10200
#define HARRIER_MPIC_IFEDE_OFF 0x10210
#define HARRIER_FEEN_OFF 0x40
#define HARRIER_FEST_OFF 0x44
#define HARRIER_FEMA_OFF 0x48
#define HARRIER_FE_DMA 0x80
#define HARRIER_FE_MIDB 0x40
#define HARRIER_FE_MIM0 0x20
#define HARRIER_FE_MIM1 0x10
#define HARRIER_FE_MIP 0x08
#define HARRIER_FE_UA0 0x04
#define HARRIER_FE_UA1 0x02
#define HARRIER_FE_ABT 0x01
struct pci_controller;
int harrier_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
......@@ -97,4 +36,10 @@ unsigned long harrier_get_mem_size(uint smc_base);
int harrier_mpic_init(unsigned int pci_mem_offset);
void harrier_setup_nonmonarch(uint ppc_reg_base,
uint in0_size);
void harrier_release_eready(uint ppc_reg_base);
void harrier_wait_eready(uint ppc_reg_base);
#endif /* __ASMPPC_HARRIER_H */
include/linux/harrier_defs.h 0 → 100644
View file @ bd08b0a9
/*
* asm-ppc/harrier_defs.h
*
* Definitions for Motorola MCG Harrier North Bridge & Memory controller
*
* Author: Dale Farnsworth
* dale.farnsworth@mvista.com
*
* Extracted from asm-ppc/harrier.h by:
* Randy Vinson
* rvinson@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASMPPC_HARRIER_DEFS_H
#define __ASMPPC_HARRIER_DEFS_H
#define HARRIER_DEFAULT_XCSR_BASE 0xfeff0000
#define HARRIER_VEND_DEV_ID 0x1057480b
#define HARRIER_VENI_OFF 0x00
#define HARRIER_REVI_OFF 0x05
#define HARRIER_UCTL_OFF 0xd0
#define HARRIER_XTAL64_MASK 0x02
#define HARRIER_MISC_CSR_OFF 0x1c
#define HARRIER_RSTOUT 0x01000000
#define HARRIER_SYSCON 0x08000000
#define HARRIER_EREADY 0x10000000
#define HARRIER_ERDYS 0x20000000
/* Function exception registers */
#define HARRIER_FEEN_OFF 0x40 /* enable */
#define HARRIER_FEST_OFF 0x44 /* status */
#define HARRIER_FEMA_OFF 0x48 /* mask */
#define HARRIER_FECL_OFF 0x4c /* clear */
#define HARRIER_FE_DMA 0x80
#define HARRIER_FE_MIDB 0x40
#define HARRIER_FE_MIM0 0x20
#define HARRIER_FE_MIM1 0x10
#define HARRIER_FE_MIP 0x08
#define HARRIER_FE_UA0 0x04
#define HARRIER_FE_UA1 0x02
#define HARRIER_FE_ABT 0x01
#define HARRIER_SERIAL_0_OFF 0xc0
#define HARRIER_MBAR_OFF 0xe0
#define HARRIER_MBAR_MSK 0xfffc0000
#define HARRIER_MPIC_CSR_OFF 0xe4
#define HARRIER_MPIC_OPI_ENABLE 0x40
#define HARRIER_MPIC_IFEVP_OFF 0x10200
#define HARRIER_MPIC_IFEVP_VECT_MSK 0xff
#define HARRIER_MPIC_IFEDE_OFF 0x10210
/*
* Define the Memory Controller register offsets.
*/
#define HARRIER_SDBA_OFF 0x110
#define HARRIER_SDBB_OFF 0x114
#define HARRIER_SDBC_OFF 0x118
#define HARRIER_SDBD_OFF 0x11c
#define HARRIER_SDBE_OFF 0x120
#define HARRIER_SDBF_OFF 0x124
#define HARRIER_SDBG_OFF 0x128
#define HARRIER_SDBH_OFF 0x12c
#define HARRIER_SDB_ENABLE 0x00000100
#define HARRIER_SDB_SIZE_MASK 0xf
#define HARRIER_SDB_SIZE_SHIFT 16
#define HARRIER_SDB_BASE_MASK 0xff
#define HARRIER_SDB_BASE_SHIFT 24
/*
* Define outbound register offsets.
*/
#define HARRIER_OTAD0_OFF 0x220
#define HARRIER_OTOF0_OFF 0x224
#define HARRIER_OTAD1_OFF 0x228
#define HARRIER_OTOF1_OFF 0x22c
#define HARRIER_OTAD2_OFF 0x230
#define HARRIER_OTOF2_OFF 0x234
#define HARRIER_OTAD3_OFF 0x238
#define HARRIER_OTOF3_OFF 0x23c
#define HARRIER_OTADX_START_MSK 0xffff0000UL
#define HARRIER_OTADX_END_MSK 0x0000ffffUL
#define HARRIER_OTOFX_OFF_MSK 0xffff0000UL
#define HARRIER_OTOFX_ENA 0x80UL
#define HARRIER_OTOFX_WPE 0x10UL
#define HARRIER_OTOFX_SGE 0x08UL
#define HARRIER_OTOFX_RAE 0x04UL
#define HARRIER_OTOFX_MEM 0x02UL
#define HARRIER_OTOFX_IOM 0x01UL
/*
* Define generic message passing register offsets
*/
/* Mirrored registers (visible from both PowerPC and PCI space) */
#define HARRIER_XCSR_MP_BASE_OFF 0x290 /* base offset in XCSR space */
#define HARRIER_PMEP_MP_BASE_OFF 0x100 /* base offset in PMEM space */
#define HARRIER_MGOM0_OFF 0x00 /* outbound msg 0 */
#define HARRIER_MGOM1_OFF 0x04 /* outbound msg 1 */
#define HARRIER_MGOD_OFF 0x08 /* outbound doorbells */
#define HARRIER_MGIM0_OFF 0x10 /* inbound msg 0 */
#define HARRIER_MGIM1_OFF 0x14 /* inbound msg 1 */
#define HARRIER_MGID_OFF 0x18 /* inbound doorbells */
/* PowerPC-only registers */
#define HARRIER_MGIDM_OFF 0x20 /* inbound doorbell mask */
/* PCI-only registers */
#define HARRIER_PMEP_MGST_OFF 0x20 /* (outbound) interrupt status */
#define HARRIER_PMEP_MGMS_OFF 0x24 /* (outbound) interrupt mask */
#define HARRIER_MG_OMI0 (1<<4)
#define HARRIER_MG_OMI1 (1<<5)
#define HARRIER_PMEP_MGODM_OFF 0x28 /* outbound doorbell mask */
/*
* Define PCI configuration space register offsets
*/
#define HARRIER_XCSR_TO_PCFS_OFF 0x300
/*
* Define message passing attribute register offset
*/
#define HARRIER_MPAT_OFF 0x44
/*
* Define inbound attribute register offsets.
*/
#define HARRIER_ITSZ0_OFF 0x48
#define HARRIER_ITAT0_OFF 0x4c
#define HARRIER_ITSZ1_OFF 0x50
#define HARRIER_ITAT1_OFF 0x54
#define HARRIER_ITSZ2_OFF 0x58
#define HARRIER_ITAT2_OFF 0x5c
#define HARRIER_ITSZ3_OFF 0x60
#define HARRIER_ITAT3_OFF 0x64
/* inbound translation size constants */
#define HARRIER_ITSZ_MSK 0xff
#define HARRIER_ITSZ_4KB 0x00
#define HARRIER_ITSZ_8KB 0x01
#define HARRIER_ITSZ_16KB 0x02
#define HARRIER_ITSZ_32KB 0x03
#define HARRIER_ITSZ_64KB 0x04
#define HARRIER_ITSZ_128KB 0x05
#define HARRIER_ITSZ_256KB 0x06
#define HARRIER_ITSZ_512KB 0x07
#define HARRIER_ITSZ_1MB 0x08
#define HARRIER_ITSZ_2MB 0x09
#define HARRIER_ITSZ_4MB 0x0A
#define HARRIER_ITSZ_8MB 0x0B
#define HARRIER_ITSZ_16MB 0x0C
#define HARRIER_ITSZ_32MB 0x0D
#define HARRIER_ITSZ_64MB 0x0E
#define HARRIER_ITSZ_128MB 0x0F
#define HARRIER_ITSZ_256MB 0x10
#define HARRIER_ITSZ_512MB 0x11
#define HARRIER_ITSZ_1GB 0x12
#define HARRIER_ITSZ_2GB 0x13
/* inbound translation offset */
#define HARRIER_ITOF_SHIFT 0x10
#define HARRIER_ITOF_MSK 0xffff
/* inbound translation atttributes */
#define HARRIER_ITAT_PRE (1<<3)
#define HARRIER_ITAT_RAE (1<<4)
#define HARRIER_ITAT_WPE (1<<5)
#define HARRIER_ITAT_MEM (1<<6)
#define HARRIER_ITAT_ENA (1<<7)
#define HARRIER_ITAT_GBL (1<<16)
#define HARRIER_LBA_OFF 0x80
#define HARRIER_LBA_MSK (1<<31)
#define HARRIER_XCSR_SIZE 1024
/* macros to calculate message passing register offsets */
#define HARRIER_MP_XCSR(x) ((u32)HARRIER_XCSR_MP_BASE_OFF + (u32)x)
#define HARRIER_MP_PMEP(x) ((u32)HARRIER_PMEP_MP_BASE_OFF + (u32)x)
/*
* Define PCI configuration space register offsets
*/
#define HARRIER_MPBAR_OFF PCI_BASE_ADDRESS_0
#define HARRIER_ITBAR0_OFF PCI_BASE_ADDRESS_1
#define HARRIER_ITBAR1_OFF PCI_BASE_ADDRESS_2
#define HARRIER_ITBAR2_OFF PCI_BASE_ADDRESS_3
#define HARRIER_ITBAR3_OFF PCI_BASE_ADDRESS_4
#define HARRIER_XCSR_CONFIG(x) ((u32)HARRIER_XCSR_TO_PCFS_OFF + (u32)x)
#endif /* __ASMPPC_HARRIER_DEFS_H */
include/linux/pci_ids.h
View file @ bd08b0a9
......@@ -759,6 +759,7 @@
#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
#define PCI_VENDOR_ID_PROMISE 0x105a
#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
......
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