Commit bdb18d93 authored by Linus Walleij's avatar Linus Walleij

Merge branch 'ingenic' into devel

parents 7f0ff06c e25f2af6
Ingenic jz47xx GPIO controller
That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
driver node.
Required properties:
--------------------
- compatible: Must contain one of:
- "ingenic,jz4740-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
- reg: The GPIO bank number.
- interrupt-controller: Marks the device node as an interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
- #interrupt-cells: Should be 2. Refer to
../interrupt-controller/interrupts.txt for more details.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
'gpio.txt' in this directory for more details.
Example:
--------
&pinctrl {
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4740-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <28>;
};
};
Ingenic jz47xx pin controller
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
be used as GPIOs, multiplexed device functions are configured within the
GPIO port configuration registers and it is typical to refer to pins using the
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
total of 192 pins.
Required properties:
--------------------
- compatible: One of:
- "ingenic,jz4740-pinctrl"
- "ingenic,jz4770-pinctrl"
- "ingenic,jz4780-pinctrl"
- reg: Address range of the pinctrl registers.
GPIO sub-nodes
--------------
The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
please refer to ../gpio/ingenic,gpio.txt.
Example:
--------
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4740-pinctrl";
reg = <0x10010000 0x400>;
};
...@@ -364,6 +364,7 @@ config MACH_INGENIC ...@@ -364,6 +364,7 @@ config MACH_INGENIC
select SYS_SUPPORTS_ZBOOT_UART16550 select SYS_SUPPORTS_ZBOOT_UART16550
select DMA_NONCOHERENT select DMA_NONCOHERENT
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
select PINCTRL
select GPIOLIB select GPIOLIB
select COMMON_CLK select COMMON_CLK
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
......
...@@ -29,18 +29,30 @@ &ext { ...@@ -29,18 +29,30 @@ &ext {
&uart0 { &uart0 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_uart0>;
}; };
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_uart1>;
}; };
&uart3 { &uart3 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_uart2>;
}; };
&uart4 { &uart4 {
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_uart4>;
}; };
&nemc { &nemc {
...@@ -61,6 +73,13 @@ nandc: nand-controller@1 { ...@@ -61,6 +73,13 @@ nandc: nand-controller@1 {
ingenic,nemc-tAW = <15>; ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>; ingenic,nemc-tSTRV = <100>;
/*
* Only CLE/ALE are needed for the devices that are connected, rather
* than the full address line set.
*/
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc>;
nand@1 { nand@1 {
reg = <1>; reg = <1>;
...@@ -69,6 +88,9 @@ nand@1 { ...@@ -69,6 +88,9 @@ nand@1 {
nand-ecc-mode = "hw"; nand-ecc-mode = "hw";
nand-on-flash-bbt; nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc_cs1>;
partitions { partitions {
compatible = "fixed-partitions"; compatible = "fixed-partitions";
#address-cells = <2>; #address-cells = <2>;
...@@ -106,3 +128,41 @@ partition@0x8c00000 { ...@@ -106,3 +128,41 @@ partition@0x8c00000 {
&bch { &bch {
status = "okay"; status = "okay";
}; };
&pinctrl {
pins_uart0: uart0 {
function = "uart0";
groups = "uart0-data";
bias-disable;
};
pins_uart1: uart1 {
function = "uart1";
groups = "uart1-data";
bias-disable;
};
pins_uart2: uart2 {
function = "uart2";
groups = "uart2-data", "uart2-hwflow";
bias-disable;
};
pins_uart4: uart4 {
function = "uart4";
groups = "uart4-data";
bias-disable;
};
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
bias-disable;
};
pins_nemc_cs1: nemc-cs1 {
function = "nemc-cs1";
groups = "nemc-cs1";
bias-disable;
};
};
...@@ -55,6 +55,74 @@ rtc_dev: rtc@10003000 { ...@@ -55,6 +55,74 @@ rtc_dev: rtc@10003000 {
clock-names = "rtc"; clock-names = "rtc";
}; };
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4740-pinctrl";
reg = <0x10010000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4740-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <28>;
};
gpb: gpio@1 {
compatible = "ingenic,jz4740-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <27>;
};
gpc: gpio@2 {
compatible = "ingenic,jz4740-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <26>;
};
gpd: gpio@3 {
compatible = "ingenic,jz4740-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <25>;
};
};
uart0: serial@10030000 { uart0: serial@10030000 {
compatible = "ingenic,jz4740-uart"; compatible = "ingenic,jz4740-uart";
reg = <0x10030000 0x100>; reg = <0x10030000 0x100>;
......
...@@ -44,6 +44,104 @@ cgu: jz4780-cgu@10000000 { ...@@ -44,6 +44,104 @@ cgu: jz4780-cgu@10000000 {
#clock-cells = <1>; #clock-cells = <1>;
}; };
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4780-pinctrl";
reg = <0x10010000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4780-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <17>;
};
gpb: gpio@1 {
compatible = "ingenic,jz4780-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <16>;
};
gpc: gpio@2 {
compatible = "ingenic,jz4780-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <15>;
};
gpd: gpio@3 {
compatible = "ingenic,jz4780-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
gpe: gpio@4 {
compatible = "ingenic,jz4780-gpio";
reg = <4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <13>;
};
gpf: gpio@5 {
compatible = "ingenic,jz4780-gpio";
reg = <5>;
gpio-controller;
gpio-ranges = <&pinctrl 0 160 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <12>;
};
};
uart0: serial@10030000 { uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart"; compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>; reg = <0x10030000 0x100>;
......
...@@ -17,3 +17,16 @@ &ext { ...@@ -17,3 +17,16 @@ &ext {
&rtc_dev { &rtc_dev {
system-power-controller; system-power-controller;
}; };
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pins_uart0>;
};
&pinctrl {
pins_uart0: uart0 {
function = "uart0";
groups = "uart0-data";
bias-disable;
};
};
This diff is collapsed.
...@@ -7,8 +7,6 @@ ...@@ -7,8 +7,6 @@
obj-y += prom.o time.o reset.o setup.o \ obj-y += prom.o time.o reset.o setup.o \
platform.o timer.o platform.o timer.o
obj-$(CONFIG_MACH_JZ4740) += gpio.o
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
# board specific support # board specific support
......
...@@ -22,6 +22,8 @@ ...@@ -22,6 +22,8 @@
#include <linux/input/matrix_keypad.h> #include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h> #include <linux/spi/spi_gpio.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/power_supply.h> #include <linux/power_supply.h>
#include <linux/power/jz4740-battery.h> #include <linux/power/jz4740-battery.h>
#include <linux/power/gpio-charger.h> #include <linux/power/gpio-charger.h>
...@@ -159,7 +161,7 @@ static struct jz_nand_platform_data qi_lb60_nand_pdata = { ...@@ -159,7 +161,7 @@ static struct jz_nand_platform_data qi_lb60_nand_pdata = {
static struct gpiod_lookup_table qi_lb60_nand_gpio_table = { static struct gpiod_lookup_table qi_lb60_nand_gpio_table = {
.dev_id = "jz4740-nand.0", .dev_id = "jz4740-nand.0",
.table = { .table = {
GPIO_LOOKUP("Bank C", 30, "busy", 0), GPIO_LOOKUP("GPIOC", 30, "busy", 0),
{ }, { },
}, },
}; };
...@@ -421,8 +423,8 @@ static struct platform_device qi_lb60_audio_device = { ...@@ -421,8 +423,8 @@ static struct platform_device qi_lb60_audio_device = {
static struct gpiod_lookup_table qi_lb60_audio_gpio_table = { static struct gpiod_lookup_table qi_lb60_audio_gpio_table = {
.dev_id = "qi-lb60-audio", .dev_id = "qi-lb60-audio",
.table = { .table = {
GPIO_LOOKUP("Bank B", 29, "snd", 0), GPIO_LOOKUP("GPIOB", 29, "snd", 0),
GPIO_LOOKUP("Bank D", 4, "amp", 0), GPIO_LOOKUP("GPIOD", 4, "amp", 0),
{ }, { },
}, },
}; };
...@@ -447,13 +449,36 @@ static struct platform_device *jz_platform_devices[] __initdata = { ...@@ -447,13 +449,36 @@ static struct platform_device *jz_platform_devices[] __initdata = {
&qi_lb60_audio_device, &qi_lb60_audio_device,
}; };
static void __init board_gpio_setup(void) static unsigned long pin_cfg_bias_disable[] = {
{ PIN_CONFIG_BIAS_DISABLE,
/* We only need to enable/disable pullup here for pins used in generic };
* drivers. Everything else is done by the drivers themselves. */
jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N); static struct pinctrl_map pin_map[] __initdata = {
jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD); /* NAND pin configuration */
} PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
"10010000.jz4740-pinctrl", "nand", "nand-cs1"),
/* fbdev pin configuration */
PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
"10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),
PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
"10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),
/* MMC pin configuration */
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
"10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
"10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),
PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
"10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),
PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
"10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),
/* PWM pin configuration */
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
"10010000.jz4740-pinctrl", "pwm4", "pwm4"),
};
static int __init qi_lb60_init_platform_devices(void) static int __init qi_lb60_init_platform_devices(void)
{ {
...@@ -469,6 +494,7 @@ static int __init qi_lb60_init_platform_devices(void) ...@@ -469,6 +494,7 @@ static int __init qi_lb60_init_platform_devices(void)
ARRAY_SIZE(qi_lb60_spi_board_info)); ARRAY_SIZE(qi_lb60_spi_board_info));
pwm_add_table(qi_lb60_pwm_lookup, ARRAY_SIZE(qi_lb60_pwm_lookup)); pwm_add_table(qi_lb60_pwm_lookup, ARRAY_SIZE(qi_lb60_pwm_lookup));
pinctrl_register_mappings(pin_map, ARRAY_SIZE(pin_map));
return platform_add_devices(jz_platform_devices, return platform_add_devices(jz_platform_devices,
ARRAY_SIZE(jz_platform_devices)); ARRAY_SIZE(jz_platform_devices));
...@@ -479,8 +505,6 @@ static int __init qi_lb60_board_setup(void) ...@@ -479,8 +505,6 @@ static int __init qi_lb60_board_setup(void)
{ {
printk(KERN_INFO "Qi Hardware JZ4740 QI LB60 setup\n"); printk(KERN_INFO "Qi Hardware JZ4740 QI LB60 setup\n");
board_gpio_setup();
if (qi_lb60_init_platform_devices()) if (qi_lb60_init_platform_devices())
panic("Failed to initialize platform devices"); panic("Failed to initialize platform devices");
......
This diff is collapsed.
...@@ -242,6 +242,16 @@ config GPIO_ICH ...@@ -242,6 +242,16 @@ config GPIO_ICH
If unsure, say N. If unsure, say N.
config GPIO_INGENIC
tristate "Ingenic JZ47xx SoCs GPIO support"
depends on MACH_INGENIC || COMPILE_TEST
select GPIOLIB_IRQCHIP
help
Say yes here to support the GPIO functionality present on the
JZ4740 and JZ4780 SoCs from Ingenic.
If unsure, say N.
config GPIO_IOP config GPIO_IOP
tristate "Intel IOP GPIO" tristate "Intel IOP GPIO"
depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST
......
...@@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o ...@@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o
obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
obj-$(CONFIG_GPIO_ICH) += gpio-ich.o obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
obj-$(CONFIG_GPIO_INGENIC) += gpio-ingenic.o
obj-$(CONFIG_GPIO_IOP) += gpio-iop.o obj-$(CONFIG_GPIO_IOP) += gpio-iop.o
obj-$(CONFIG_GPIO_IT87) += gpio-it87.o obj-$(CONFIG_GPIO_IT87) += gpio-it87.o
obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
......
This diff is collapsed.
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/scatterlist.h> #include <linux/scatterlist.h>
...@@ -27,7 +28,6 @@ ...@@ -27,7 +28,6 @@
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <asm/mach-jz4740/gpio.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/dmaengine.h> #include <linux/dmaengine.h>
...@@ -901,15 +901,6 @@ static const struct mmc_host_ops jz4740_mmc_ops = { ...@@ -901,15 +901,6 @@ static const struct mmc_host_ops jz4740_mmc_ops = {
.enable_sdio_irq = jz4740_mmc_enable_sdio_irq, .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
}; };
static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
JZ_GPIO_BULK_PIN(MSC_CMD),
JZ_GPIO_BULK_PIN(MSC_CLK),
JZ_GPIO_BULK_PIN(MSC_DATA0),
JZ_GPIO_BULK_PIN(MSC_DATA1),
JZ_GPIO_BULK_PIN(MSC_DATA2),
JZ_GPIO_BULK_PIN(MSC_DATA3),
};
static int jz4740_mmc_request_gpio(struct device *dev, int gpio, static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
const char *name, bool output, int value) const char *name, bool output, int value)
{ {
...@@ -973,15 +964,6 @@ static void jz4740_mmc_free_gpios(struct platform_device *pdev) ...@@ -973,15 +964,6 @@ static void jz4740_mmc_free_gpios(struct platform_device *pdev)
gpio_free(pdata->gpio_power); gpio_free(pdata->gpio_power);
} }
static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
{
size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
if (host->pdata && host->pdata->data_1bit)
num_pins -= 3;
return num_pins;
}
static int jz4740_mmc_probe(struct platform_device* pdev) static int jz4740_mmc_probe(struct platform_device* pdev)
{ {
int ret; int ret;
...@@ -1022,15 +1004,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev) ...@@ -1022,15 +1004,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
goto err_free_host; goto err_free_host;
} }
ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
if (ret) {
dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
goto err_free_host;
}
ret = jz4740_mmc_request_gpios(mmc, pdev); ret = jz4740_mmc_request_gpios(mmc, pdev);
if (ret) if (ret)
goto err_gpio_bulk_free; goto err_release_dma;
mmc->ops = &jz4740_mmc_ops; mmc->ops = &jz4740_mmc_ops;
mmc->f_min = JZ_MMC_CLK_RATE / 128; mmc->f_min = JZ_MMC_CLK_RATE / 128;
...@@ -1086,10 +1062,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev) ...@@ -1086,10 +1062,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
free_irq(host->irq, host); free_irq(host->irq, host);
err_free_gpios: err_free_gpios:
jz4740_mmc_free_gpios(pdev); jz4740_mmc_free_gpios(pdev);
err_gpio_bulk_free: err_release_dma:
if (host->use_dma) if (host->use_dma)
jz4740_mmc_release_dma_channels(host); jz4740_mmc_release_dma_channels(host);
jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
err_free_host: err_free_host:
mmc_free_host(mmc); mmc_free_host(mmc);
...@@ -1109,7 +1084,6 @@ static int jz4740_mmc_remove(struct platform_device *pdev) ...@@ -1109,7 +1084,6 @@ static int jz4740_mmc_remove(struct platform_device *pdev)
free_irq(host->irq, host); free_irq(host->irq, host);
jz4740_mmc_free_gpios(pdev); jz4740_mmc_free_gpios(pdev);
jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
if (host->use_dma) if (host->use_dma)
jz4740_mmc_release_dma_channels(host); jz4740_mmc_release_dma_channels(host);
...@@ -1123,20 +1097,12 @@ static int jz4740_mmc_remove(struct platform_device *pdev) ...@@ -1123,20 +1097,12 @@ static int jz4740_mmc_remove(struct platform_device *pdev)
static int jz4740_mmc_suspend(struct device *dev) static int jz4740_mmc_suspend(struct device *dev)
{ {
struct jz4740_mmc_host *host = dev_get_drvdata(dev); return pinctrl_pm_select_sleep_state(dev);
jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
return 0;
} }
static int jz4740_mmc_resume(struct device *dev) static int jz4740_mmc_resume(struct device *dev)
{ {
struct jz4740_mmc_host *host = dev_get_drvdata(dev); return pinctrl_pm_select_default_state(dev);
jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
return 0;
} }
static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
......
...@@ -25,7 +25,6 @@ ...@@ -25,7 +25,6 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/jz4740_nand.h> #include <asm/mach-jz4740/jz4740_nand.h>
#define JZ_REG_NAND_CTRL 0x50 #define JZ_REG_NAND_CTRL 0x50
...@@ -310,34 +309,20 @@ static int jz_nand_detect_bank(struct platform_device *pdev, ...@@ -310,34 +309,20 @@ static int jz_nand_detect_bank(struct platform_device *pdev,
uint8_t *nand_dev_id) uint8_t *nand_dev_id)
{ {
int ret; int ret;
int gpio;
char gpio_name[9];
char res_name[6]; char res_name[6];
uint32_t ctrl; uint32_t ctrl;
struct nand_chip *chip = &nand->chip; struct nand_chip *chip = &nand->chip;
struct mtd_info *mtd = nand_to_mtd(chip); struct mtd_info *mtd = nand_to_mtd(chip);
/* Request GPIO port. */
gpio = JZ_GPIO_MEM_CS0 + bank - 1;
sprintf(gpio_name, "NAND CS%d", bank);
ret = gpio_request(gpio, gpio_name);
if (ret) {
dev_warn(&pdev->dev,
"Failed to request %s gpio %d: %d\n",
gpio_name, gpio, ret);
goto notfound_gpio;
}
/* Request I/O resource. */ /* Request I/O resource. */
sprintf(res_name, "bank%d", bank); sprintf(res_name, "bank%d", bank);
ret = jz_nand_ioremap_resource(pdev, res_name, ret = jz_nand_ioremap_resource(pdev, res_name,
&nand->bank_mem[bank - 1], &nand->bank_mem[bank - 1],
&nand->bank_base[bank - 1]); &nand->bank_base[bank - 1]);
if (ret) if (ret)
goto notfound_resource; return ret;
/* Enable chip in bank. */ /* Enable chip in bank. */
jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
ctrl = readl(nand->base + JZ_REG_NAND_CTRL); ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1); ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
writel(ctrl, nand->base + JZ_REG_NAND_CTRL); writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
...@@ -377,12 +362,8 @@ static int jz_nand_detect_bank(struct platform_device *pdev, ...@@ -377,12 +362,8 @@ static int jz_nand_detect_bank(struct platform_device *pdev,
dev_info(&pdev->dev, "No chip found on bank %i\n", bank); dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1)); ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
writel(ctrl, nand->base + JZ_REG_NAND_CTRL); writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1], jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]); nand->bank_base[bank - 1]);
notfound_resource:
gpio_free(gpio);
notfound_gpio:
return ret; return ret;
} }
...@@ -503,7 +484,6 @@ static int jz_nand_probe(struct platform_device *pdev) ...@@ -503,7 +484,6 @@ static int jz_nand_probe(struct platform_device *pdev)
err_unclaim_banks: err_unclaim_banks:
while (chipnr--) { while (chipnr--) {
unsigned char bank = nand->banks[chipnr]; unsigned char bank = nand->banks[chipnr];
gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1], jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]); nand->bank_base[bank - 1]);
} }
...@@ -530,7 +510,6 @@ static int jz_nand_remove(struct platform_device *pdev) ...@@ -530,7 +510,6 @@ static int jz_nand_remove(struct platform_device *pdev)
if (bank != 0) { if (bank != 0) {
jz_nand_iounmap_resource(nand->bank_mem[bank - 1], jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]); nand->bank_base[bank - 1]);
gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
} }
} }
......
...@@ -296,6 +296,15 @@ config PINCTRL_ZYNQ ...@@ -296,6 +296,15 @@ config PINCTRL_ZYNQ
help help
This selects the pinctrl driver for Xilinx Zynq. This selects the pinctrl driver for Xilinx Zynq.
config PINCTRL_INGENIC
bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
default y
depends on MACH_INGENIC || COMPILE_TEST
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select REGMAP_MMIO
source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/berlin/Kconfig"
......
...@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o ...@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-y += bcm/ obj-y += bcm/
......
This diff is collapsed.
...@@ -21,22 +21,10 @@ ...@@ -21,22 +21,10 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pwm.h> #include <linux/pwm.h>
#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/timer.h> #include <asm/mach-jz4740/timer.h>
#define NUM_PWM 8 #define NUM_PWM 8
static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = {
JZ_GPIO_PWM0,
JZ_GPIO_PWM1,
JZ_GPIO_PWM2,
JZ_GPIO_PWM3,
JZ_GPIO_PWM4,
JZ_GPIO_PWM5,
JZ_GPIO_PWM6,
JZ_GPIO_PWM7,
};
struct jz4740_pwm_chip { struct jz4740_pwm_chip {
struct pwm_chip chip; struct pwm_chip chip;
struct clk *clk; struct clk *clk;
...@@ -49,9 +37,6 @@ static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) ...@@ -49,9 +37,6 @@ static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{ {
unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
int ret;
/* /*
* Timers 0 and 1 are used for system tasks, so they are unavailable * Timers 0 and 1 are used for system tasks, so they are unavailable
* for use as PWMs. * for use as PWMs.
...@@ -59,15 +44,6 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) ...@@ -59,15 +44,6 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
if (pwm->hwpwm < 2) if (pwm->hwpwm < 2)
return -EBUSY; return -EBUSY;
ret = gpio_request(gpio, pwm->label);
if (ret) {
dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n",
gpio, ret);
return ret;
}
jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM);
jz4740_timer_start(pwm->hwpwm); jz4740_timer_start(pwm->hwpwm);
return 0; return 0;
...@@ -75,13 +51,8 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) ...@@ -75,13 +51,8 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{ {
unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
jz4740_timer_set_ctrl(pwm->hwpwm, 0); jz4740_timer_set_ctrl(pwm->hwpwm, 0);
jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
gpio_free(gpio);
jz4740_timer_stop(pwm->hwpwm); jz4740_timer_stop(pwm->hwpwm);
} }
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/mutex.h> #include <linux/mutex.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
...@@ -27,7 +28,6 @@ ...@@ -27,7 +28,6 @@
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <asm/mach-jz4740/jz4740_fb.h> #include <asm/mach-jz4740/jz4740_fb.h>
#include <asm/mach-jz4740/gpio.h>
#define JZ_REG_LCD_CFG 0x00 #define JZ_REG_LCD_CFG 0x00
#define JZ_REG_LCD_VSYNC 0x04 #define JZ_REG_LCD_VSYNC 0x04
...@@ -146,93 +146,6 @@ static const struct fb_fix_screeninfo jzfb_fix = { ...@@ -146,93 +146,6 @@ static const struct fb_fix_screeninfo jzfb_fix = {
.accel = FB_ACCEL_NONE, .accel = FB_ACCEL_NONE,
}; };
static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
JZ_GPIO_BULK_PIN(LCD_PCLK),
JZ_GPIO_BULK_PIN(LCD_HSYNC),
JZ_GPIO_BULK_PIN(LCD_VSYNC),
JZ_GPIO_BULK_PIN(LCD_DE),
JZ_GPIO_BULK_PIN(LCD_PS),
JZ_GPIO_BULK_PIN(LCD_REV),
JZ_GPIO_BULK_PIN(LCD_CLS),
JZ_GPIO_BULK_PIN(LCD_SPL),
};
static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
JZ_GPIO_BULK_PIN(LCD_DATA0),
JZ_GPIO_BULK_PIN(LCD_DATA1),
JZ_GPIO_BULK_PIN(LCD_DATA2),
JZ_GPIO_BULK_PIN(LCD_DATA3),
JZ_GPIO_BULK_PIN(LCD_DATA4),
JZ_GPIO_BULK_PIN(LCD_DATA5),
JZ_GPIO_BULK_PIN(LCD_DATA6),
JZ_GPIO_BULK_PIN(LCD_DATA7),
JZ_GPIO_BULK_PIN(LCD_DATA8),
JZ_GPIO_BULK_PIN(LCD_DATA9),
JZ_GPIO_BULK_PIN(LCD_DATA10),
JZ_GPIO_BULK_PIN(LCD_DATA11),
JZ_GPIO_BULK_PIN(LCD_DATA12),
JZ_GPIO_BULK_PIN(LCD_DATA13),
JZ_GPIO_BULK_PIN(LCD_DATA14),
JZ_GPIO_BULK_PIN(LCD_DATA15),
JZ_GPIO_BULK_PIN(LCD_DATA16),
JZ_GPIO_BULK_PIN(LCD_DATA17),
};
static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
{
unsigned int num;
switch (jzfb->pdata->lcd_type) {
case JZ_LCD_TYPE_GENERIC_16_BIT:
num = 4;
break;
case JZ_LCD_TYPE_GENERIC_18_BIT:
num = 4;
break;
case JZ_LCD_TYPE_8BIT_SERIAL:
num = 3;
break;
case JZ_LCD_TYPE_SPECIAL_TFT_1:
case JZ_LCD_TYPE_SPECIAL_TFT_2:
case JZ_LCD_TYPE_SPECIAL_TFT_3:
num = 8;
break;
default:
num = 0;
break;
}
return num;
}
static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
{
unsigned int num;
switch (jzfb->pdata->lcd_type) {
case JZ_LCD_TYPE_GENERIC_16_BIT:
num = 16;
break;
case JZ_LCD_TYPE_GENERIC_18_BIT:
num = 18;
break;
case JZ_LCD_TYPE_8BIT_SERIAL:
num = 8;
break;
case JZ_LCD_TYPE_SPECIAL_TFT_1:
case JZ_LCD_TYPE_SPECIAL_TFT_2:
case JZ_LCD_TYPE_SPECIAL_TFT_3:
if (jzfb->pdata->bpp == 18)
num = 18;
else
num = 16;
break;
default:
num = 0;
break;
}
return num;
}
/* Based on CNVT_TOHW macro from skeletonfb.c */ /* Based on CNVT_TOHW macro from skeletonfb.c */
static inline uint32_t jzfb_convert_color_to_hw(unsigned val, static inline uint32_t jzfb_convert_color_to_hw(unsigned val,
struct fb_bitfield *bf) struct fb_bitfield *bf)
...@@ -487,8 +400,7 @@ static void jzfb_enable(struct jzfb *jzfb) ...@@ -487,8 +400,7 @@ static void jzfb_enable(struct jzfb *jzfb)
clk_prepare_enable(jzfb->ldclk); clk_prepare_enable(jzfb->ldclk);
jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); pinctrl_pm_select_default_state(&jzfb->pdev->dev);
jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
writel(0, jzfb->base + JZ_REG_LCD_STATE); writel(0, jzfb->base + JZ_REG_LCD_STATE);
...@@ -511,8 +423,7 @@ static void jzfb_disable(struct jzfb *jzfb) ...@@ -511,8 +423,7 @@ static void jzfb_disable(struct jzfb *jzfb)
ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
} while (!(ctrl & JZ_LCD_STATE_DISABLED)); } while (!(ctrl & JZ_LCD_STATE_DISABLED));
jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); pinctrl_pm_select_sleep_state(&jzfb->pdev->dev);
jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
clk_disable_unprepare(jzfb->ldclk); clk_disable_unprepare(jzfb->ldclk);
} }
...@@ -701,9 +612,6 @@ static int jzfb_probe(struct platform_device *pdev) ...@@ -701,9 +612,6 @@ static int jzfb_probe(struct platform_device *pdev)
fb->mode = NULL; fb->mode = NULL;
jzfb_set_par(fb); jzfb_set_par(fb);
jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
ret = register_framebuffer(fb); ret = register_framebuffer(fb);
if (ret) { if (ret) {
dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
...@@ -715,9 +623,6 @@ static int jzfb_probe(struct platform_device *pdev) ...@@ -715,9 +623,6 @@ static int jzfb_probe(struct platform_device *pdev)
return 0; return 0;
err_free_devmem: err_free_devmem:
jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
fb_dealloc_cmap(&fb->cmap); fb_dealloc_cmap(&fb->cmap);
jzfb_free_devmem(jzfb); jzfb_free_devmem(jzfb);
err_framebuffer_release: err_framebuffer_release:
...@@ -731,9 +636,6 @@ static int jzfb_remove(struct platform_device *pdev) ...@@ -731,9 +636,6 @@ static int jzfb_remove(struct platform_device *pdev)
jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb);
jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
fb_dealloc_cmap(&jzfb->fb->cmap); fb_dealloc_cmap(&jzfb->fb->cmap);
jzfb_free_devmem(jzfb); jzfb_free_devmem(jzfb);
......
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