Commit be16cd38 authored by Hiroyuki Yokoyama's avatar Hiroyuki Yokoyama Committed by Simon Horman

ARM: shmobile: r8a7794: Add SYS-DMAC clocks to device tree

Signed-off-by: default avatarHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
[horms: resolved conflicts]
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ce85ad47
...@@ -479,16 +479,19 @@ mstp2_clks: mstp2_clks@e6150138 { ...@@ -479,16 +479,19 @@ mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
<&mp_clk>, <&mp_clk>, <&mp_clk>; <&mp_clk>, <&mp_clk>, <&mp_clk>,
<&zs_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = < clock-indices = <
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
>; >;
clock-output-names = clock-output-names =
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0", "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
"scifb1", "msiof1", "scifb2"; "scifb1", "msiof1", "scifb2",
"sys-dmac1", "sys-dmac0";
}; };
mstp3_clks: mstp3_clks@e615013c { mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
......
...@@ -48,6 +48,8 @@ ...@@ -48,6 +48,8 @@
#define R8A7794_CLK_SCIFB1 7 #define R8A7794_CLK_SCIFB1 7
#define R8A7794_CLK_MSIOF1 8 #define R8A7794_CLK_MSIOF1 8
#define R8A7794_CLK_SCIFB2 16 #define R8A7794_CLK_SCIFB2 16
#define R8A7794_CLK_SYS_DMAC1 18
#define R8A7794_CLK_SYS_DMAC0 19
/* MSTP3 */ /* MSTP3 */
#define R8A7794_CLK_CMT1 29 #define R8A7794_CLK_CMT1 29
......
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