Skip to content

L
linux
Commit bedd1738 authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
Browse files
Options

perf vendor events intel: Update event list for haswellx 

Update JSON core/uncore events for haswellx to perf.

Based on HSX JSON list v24:

https://download.01.org/perfmon/HSXReviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220614145019.2177071-2-zhengjun.xing@linux.intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 28738de9
Show whitespace changes
Inline Side-by-side
Showing with 11519 additions and 275 deletions
tools/perf/pmu-events/arch/x86/haswellx/cache.json
View file @ bedd1738
......@@ -832,9 +832,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0244",
"MSRValue": "0x4003C0244",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -847,7 +846,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -858,9 +856,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0091",
"MSRValue": "0x4003C0091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -873,7 +870,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -884,9 +880,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C07F7",
"MSRValue": "0x4003C07F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -899,7 +894,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
"Offcore": "1",
"PublicDescription": "Counts all requests hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -912,7 +906,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -923,9 +916,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0122",
"MSRValue": "0x4003C0122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -938,7 +930,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -949,9 +940,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0004",
"MSRValue": "0x4003C0004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -964,7 +954,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -975,9 +964,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0001",
"MSRValue": "0x4003C0001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -990,7 +978,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1001,9 +988,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0002",
"MSRValue": "0x4003C0002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1016,7 +1002,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0040",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1029,7 +1014,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1042,7 +1026,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1055,7 +1038,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1068,7 +1050,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1081,7 +1062,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -1091,6 +1071,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
"UMask": "0x10"
}
......
tools/perf/pmu-events/arch/x86/haswellx/memory.json
View file @ bedd1738
......@@ -233,7 +233,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -244,9 +243,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400244",
"MSRValue": "0x600400244",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -259,7 +257,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -270,9 +267,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400091",
"MSRValue": "0x600400091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -283,9 +279,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x063F800091",
"MSRValue": "0x63F800091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -298,7 +293,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -309,9 +303,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x083FC00091",
"MSRValue": "0x83FC00091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -324,7 +317,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -335,9 +327,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x06004007F7",
"MSRValue": "0x6004007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -348,9 +339,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x063F8007F7",
"MSRValue": "0x63F8007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -363,7 +353,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -374,9 +363,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x083FC007F7",
"MSRValue": "0x83FC007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -389,7 +377,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
"Offcore": "1",
"PublicDescription": "Counts all requests miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -402,7 +389,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -413,9 +399,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400122",
"MSRValue": "0x600400122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -428,7 +413,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -439,9 +423,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400004",
"MSRValue": "0x600400004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -454,7 +437,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -465,9 +447,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400001",
"MSRValue": "0x600400001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -480,7 +461,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -491,9 +471,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400002",
"MSRValue": "0x600400002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -506,7 +485,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -519,7 +497,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00040",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -532,7 +509,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00010",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -545,7 +521,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00020",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -558,7 +533,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -571,7 +545,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00080",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......@@ -584,7 +557,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
......
tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
View file @ bedd1738
......@@ -1295,7 +1295,7 @@
"BriefDescription": "Cycles with less than 10 actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
......
tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
View file @ bedd1738
This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
View file @ bedd1738
[
{
"BriefDescription": "QPI clock ticks",
"BriefDescription": "Number of qfclks",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Count of CTO Events",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
"ExtSel": "1",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Success",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L1",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0p",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
"Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "CRC Errors Detected; LinkInit",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "CRC Errors Detected; Normal Operations",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; NCB",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; HOM",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; NDR",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; DRS",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCB",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCS",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; HOM",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; SNP",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NDR",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credit Consumed",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
"ExtSel": "1",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; SNP Flits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.SNP",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; HOM Request Flits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; HOM Flits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; DRS Data Flits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; DRS Header Flits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.DRS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x18",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_Q_RxL_INSERTS",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.GV",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0p",
"Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
"Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_TxL0_POWER_CYCLES",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_Q_TxL_BYPASSED",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Cycles not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
"Counter": "0,1,2,3",
"EventName": "QPI_DATA_BANDWIDTH_TX",
"EventName": "QPI_DATA_BANDWIDTH_TX",
"PerPkg": "1",
"ScaleUnit": "8Bytes",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Number of data flits transmitted ",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
"ScaleUnit": "8Bytes",
"UMask": "0x2",
......@@ -24,5 +1006,449 @@
"ScaleUnit": "8Bytes",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Number of non data (control) flits transmitted ",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
"ScaleUnit": "8Bytes",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; SNP Flits",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.SNP",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Flits",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x18",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCS",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
"Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
"ExtSel": "1",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
"Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
"ExtSel": "1",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
"Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
"ExtSel": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Returned",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
"ExtSel": "1",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
"ExtSel": "1",
"PerPkg": "1",
"Unit": "QPI LL"
}
]
tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
View file @ bedd1738
[
{
"BriefDescription": "DRAM Activate Count; Activate due to Read",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.RD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
"Counter": "0,1,2,3",
......@@ -9,6 +81,34 @@
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "read requests to memory controller",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
......@@ -20,44 +120,323 @@
"Unit": "iMC"
},
{
"BriefDescription": "Memory controller clock ticks",
"BriefDescription": "write requests to memory controller",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Clockticks",
"Counter": "0,1,2,3",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
"BriefDescription": "DRAM Precharge All Commands",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles in a Major Mode; Read Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles in a Major Mode; Write Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Channel DLLOFF Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Channel PPD Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
"MetricName": "power_channel_ppd %",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles all ranks are in critical thermal throttle",
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Critical Throttle Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.",
"MetricName": "power_critical_throttle_cycles %",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles Memory is in self refresh power mode",
"BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M_POWER_PCU_THROTTLING",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
"MetricName": "power_self_refresh %",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Pre-charges due to page misses",
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
......@@ -66,7 +445,16 @@
"Unit": "iMC"
},
{
"BriefDescription": "Pre-charge for reads",
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
......@@ -75,12 +463,2437 @@
"Unit": "iMC"
},
{
"BriefDescription": "Pre-charge for writes",
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with LOW priority",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with HIGH priority",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Not getting the requested Major Mode",
"Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; All Banks",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK10",
"PerPkg": "1",
"UMask": "0xA",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
"UMask": "0xB",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
"UMask": "0xD",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
"UMask": "0xE",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
"Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Clockticks",
"Counter": "0,1,2,3",
"EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
}
]
tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json 0 → 100644
View file @ bedd1738
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Clocks in the IRP",
"Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; PCIRdCur",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; CRd",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; DRd",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; RFO",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; PCIDCAHin5t",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; CLFlush",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Requests",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Received Invalid",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Received Valid",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1; Data Throttled",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "AK Ingress Occupancy",
"Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
"Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
"Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Miss",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Hit I",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Hit E or S",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Hit M",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpCode",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpData",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpInv",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Write Prefetches",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Atomic",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Other",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Select Source",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "No AD Egress Credit Stalls",
"Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
"Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
"Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
"Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
"Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_TIMEOUT",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Number of uclks in domain",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R2PCIe"
},
{
"BriefDescription": "AK Ingress Bounced; Up",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCB",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCS",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Occupancy Accumulator; DRS",
"EventCode": "0x13",
"EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
"EventCode": "0x2A",
"EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
"EventCode": "0x2A",
"EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress Cycles Full; AD",
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress Cycles Full; AK",
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress Cycles Full; BL",
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress Cycles Not Empty; AD",
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress Cycles Not Empty; AK",
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AK",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress Cycles Not Empty; BL",
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Number of uclks in domain",
"Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Backpressure",
"Counter": "0,1,2",
"EventCode": "0xB",
"EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Backpressure",
"Counter": "0,1,2",
"EventCode": "0xB",
"EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
"Counter": "0,1,2",
"EventCode": "0xD",
"EventName": "UNC_R3_IOT_CTS_HI.CTS2",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
"Counter": "0,1,2",
"EventCode": "0xD",
"EventName": "UNC_R3_IOT_CTS_HI.CTS3",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
"Counter": "0,1,2",
"EventCode": "0xC",
"EventName": "UNC_R3_IOT_CTS_LO.CTS0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
"Counter": "0,1,2",
"EventCode": "0xC",
"EventName": "UNC_R3_IOT_CTS_LO.CTS1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
"Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
"Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
"Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise",
"Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise",
"Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
"Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
"Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise",
"Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise",
"Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
"Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
"Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise",
"Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise",
"Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 IV Ring in Use; Clockwise",
"Counter": "0,1,2",
"EventCode": "0xA",
"EventName": "UNC_R3_RING_IV_USED.CW",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 IV Ring in Use; Any",
"Counter": "0,1,2",
"EventCode": "0xA",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
"UMask": "0xF",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ring Stop Starved; AK",
"Counter": "0,1,2",
"EventCode": "0xE",
"EventName": "UNC_R3_RING_SINK_STARVED.AK",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Cycles Not Empty; SNP",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NDR",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; HOM",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; SNP",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NDR",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; DRS",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NCB",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NCS",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; HOM",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; SNP",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NDR",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; DRS",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCB",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCS",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS",
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
"EventCode": "0x2A",
"EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
"EventCode": "0x2A",
"EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
"EventCode": "0x2B",
"EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
"EventCode": "0x2B",
"EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_BL",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AK",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.UP_AD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.UP_BL",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.UP_AK",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; SNP Message Class",
"Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NDR Message Class",
"Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; DRS Message Class",
"Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
"Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
"Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
"Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
"Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
"Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
"Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
"Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; SNP Message Class",
"Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NDR Message Class",
"Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; DRS Message Class",
"Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCB Message Class",
"Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCS Message Class",
"Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; HOM Message Class",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; SNP Message Class",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; NDR Message Class",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; DRS Message Class",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; NCB Message Class",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; NCS Message Class",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "Bounce Control",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_S_BOUNCE_CONTROL",
"PerPkg": "1",
"Unit": "SBO"
},
{
"BriefDescription": "Uncore Clocks",
"Counter": "0,1,2,3",
"EventName": "UNC_S_CLOCKTICKS",
"PerPkg": "1",
"Unit": "SBO"
},
{
"BriefDescription": "FaST wire asserted",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_S_FAST_ASSERTED",
"PerPkg": "1",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.UP_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Event",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.UP",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.UP_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Event",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.UP",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.UP_ODD",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Event",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.UP",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "SBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_S_RING_IV_USED.UP",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
"Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_S_RING_IV_USED.DN",
"PerPkg": "1",
"UMask": "0xC",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; AK",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.AK",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; IV",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.IV",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; AK",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.AK",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; IV",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.IV",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; IVF Credit",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; AK",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.AK",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; IV",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.IV",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; AK",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.AK",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; IV",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.IV",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.AD",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.AK",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.AK",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.BL",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; AK",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.AK",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; IV",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.IV",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; AD - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; AD - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; BL - Credits",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; BL - Bounces",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; AK",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.AK",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; IV",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.IV",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AK",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
"Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.IV",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "VLW Received",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
"Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
"Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Other",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_CLOCKTICKS",
"Counter": "0,1",
"EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "UBOX"
}
]
tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
View file @ bedd1738
[
{
"BriefDescription": "PCU clock ticks. Use to get percentages of PCU cycles events",
"BriefDescription": "pclk Cycles",
"Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"Filter": "occ_sel=1",
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "power_state_occupancy.cores_c0 %",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"Filter": "occ_sel=2",
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "power_state_occupancy.cores_c3 %",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events ",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"Filter": "occ_sel=3",
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "power_state_occupancy.cores_c6 %",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "prochot_external_cycles %",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when temperature is the upper limit on frequency",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_max_limit_thermal_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when the OS is the upper limit on frequency",
"BriefDescription": "OS Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_max_os_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when power is the upper limit on frequency",
"BriefDescription": "Power Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_max_power_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when current is the upper limit on frequency",
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_trans_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C7 State Residency",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C1E",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
"Unit": "PCU"
}
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7