Commit bf80d34b authored by Philip Yang's avatar Philip Yang Committed by Alex Deucher

drm/amdgpu: Increase soft IH ring size

Retry faults are delegated to soft IH ring and then processed by
deferred worker. Current soft IH ring size PAGE_SIZE can store 128
entries, which may overflow and drop retry faults, causes HW stucks
because the retry fault is not recovered.

Increase soft IH ring size to 8KB, enough to store 256 CAM entries
because we clear the CAM entry after handling the retry fault from soft
ring.

Define macro IH_RING_SIZE and IH_SW_RING_SIZE to remove duplicate
constant.

Show warning message if soft IH ring overflows with CAM enabled because
this should not happen.
Signed-off-by: default avatarPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95b88ea1
...@@ -138,6 +138,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ...@@ -138,6 +138,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
/** /**
* amdgpu_ih_ring_write - write IV to the ring buffer * amdgpu_ih_ring_write - write IV to the ring buffer
* *
* @adev: amdgpu_device pointer
* @ih: ih ring to write to * @ih: ih ring to write to
* @iv: the iv to write * @iv: the iv to write
* @num_dw: size of the iv in dw * @num_dw: size of the iv in dw
...@@ -145,8 +146,8 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ...@@ -145,8 +146,8 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
* Writes an IV to the ring buffer using the CPU and increment the wptr. * Writes an IV to the ring buffer using the CPU and increment the wptr.
* Used for testing and delegating IVs to a software ring. * Used for testing and delegating IVs to a software ring.
*/ */
void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
unsigned int num_dw) const uint32_t *iv, unsigned int num_dw)
{ {
uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
unsigned int i; unsigned int i;
...@@ -161,6 +162,9 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, ...@@ -161,6 +162,9 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
if (wptr != READ_ONCE(ih->rptr)) { if (wptr != READ_ONCE(ih->rptr)) {
wmb(); wmb();
WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
} else if (adev->irq.retry_cam_enabled) {
dev_warn_once(adev->dev, "IH soft ring buffer overflow 0x%X, 0x%X\n",
wptr, ih->rptr);
} }
} }
......
...@@ -27,6 +27,9 @@ ...@@ -27,6 +27,9 @@
/* Maximum number of IVs processed at once */ /* Maximum number of IVs processed at once */
#define AMDGPU_IH_MAX_NUM_IVS 32 #define AMDGPU_IH_MAX_NUM_IVS 32
#define IH_RING_SIZE (256 * 1024)
#define IH_SW_RING_SIZE (8 * 1024) /* enough for 256 CAM entries */
struct amdgpu_device; struct amdgpu_device;
struct amdgpu_iv_entry; struct amdgpu_iv_entry;
...@@ -97,8 +100,8 @@ struct amdgpu_ih_funcs { ...@@ -97,8 +100,8 @@ struct amdgpu_ih_funcs {
int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
unsigned ring_size, bool use_bus_addr); unsigned ring_size, bool use_bus_addr);
void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
unsigned int num_dw); const uint32_t *iv, unsigned int num_dw);
int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev, int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
struct amdgpu_ih_ring *ih); struct amdgpu_ih_ring *ih);
int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
......
...@@ -493,7 +493,7 @@ void amdgpu_irq_delegate(struct amdgpu_device *adev, ...@@ -493,7 +493,7 @@ void amdgpu_irq_delegate(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry, struct amdgpu_iv_entry *entry,
unsigned int num_dw) unsigned int num_dw)
{ {
amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw); amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);
schedule_work(&adev->irq.ih_soft_work); schedule_work(&adev->irq.ih_soft_work);
} }
......
...@@ -535,7 +535,7 @@ static int ih_v6_0_sw_init(void *handle) ...@@ -535,7 +535,7 @@ static int ih_v6_0_sw_init(void *handle)
* use bus address for ih ring by psp bl */ * use bus address for ih ring by psp bl */
use_bus_addr = use_bus_addr =
(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
if (r) if (r)
return r; return r;
...@@ -548,7 +548,7 @@ static int ih_v6_0_sw_init(void *handle) ...@@ -548,7 +548,7 @@ static int ih_v6_0_sw_init(void *handle)
/* initialize ih control register offset */ /* initialize ih control register offset */
ih_v6_0_init_register_offset(adev); ih_v6_0_init_register_offset(adev);
r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
if (r) if (r)
return r; return r;
......
...@@ -565,7 +565,7 @@ static int navi10_ih_sw_init(void *handle) ...@@ -565,7 +565,7 @@ static int navi10_ih_sw_init(void *handle)
use_bus_addr = false; use_bus_addr = false;
else else
use_bus_addr = true; use_bus_addr = true;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
if (r) if (r)
return r; return r;
...@@ -578,7 +578,7 @@ static int navi10_ih_sw_init(void *handle) ...@@ -578,7 +578,7 @@ static int navi10_ih_sw_init(void *handle)
/* initialize ih control registers offset */ /* initialize ih control registers offset */
navi10_ih_init_register_offset(adev); navi10_ih_init_register_offset(adev);
r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
if (r) if (r)
return r; return r;
......
...@@ -485,7 +485,7 @@ static int vega10_ih_sw_init(void *handle) ...@@ -485,7 +485,7 @@ static int vega10_ih_sw_init(void *handle)
if (r) if (r)
return r; return r;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true);
if (r) if (r)
return r; return r;
...@@ -510,7 +510,7 @@ static int vega10_ih_sw_init(void *handle) ...@@ -510,7 +510,7 @@ static int vega10_ih_sw_init(void *handle)
/* initialize ih control registers offset */ /* initialize ih control registers offset */
vega10_ih_init_register_offset(adev); vega10_ih_init_register_offset(adev);
r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
if (r) if (r)
return r; return r;
......
...@@ -539,7 +539,7 @@ static int vega20_ih_sw_init(void *handle) ...@@ -539,7 +539,7 @@ static int vega20_ih_sw_init(void *handle)
(adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)))
use_bus_addr = false; use_bus_addr = false;
r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
if (r) if (r)
return r; return r;
...@@ -565,7 +565,7 @@ static int vega20_ih_sw_init(void *handle) ...@@ -565,7 +565,7 @@ static int vega20_ih_sw_init(void *handle)
/* initialize ih control registers offset */ /* initialize ih control registers offset */
vega20_ih_init_register_offset(adev); vega20_ih_init_register_offset(adev);
r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, use_bus_addr); r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
if (r) if (r)
return r; return r;
......
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