Commit c00d4ffd authored by Russell King's avatar Russell King Committed by Russell King

Merge branch 'orion' into devel

* orion: (26 commits)
  [ARM] Orion: implement power-off method for QNAP TS-109/209
  [ARM] Orion: add support for QNAP TS-109/TS-209
  [ARM] Orion: I2C support
  [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries
  [I2C] Split mv643xx I2C platform support
  [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323
  [ARM] Orion defconfig
  [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323
  [ARM] Orion: MV88F5181 support bits
  [ARM] Orion: Buffalo/Revogear Kurobox Pro support
  [ARM] OrionNAS RD board support
  [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board
  [ARM] Orion: common platform setup for Gigabit Ethernet port
  [ARM] Orion: platform device registration for UART, USB and NAND
  [ARM] Orion: system timer support
  [ARM] Orion edge GPIO IRQ support
  [ARM] Orion: IRQ support
  [ARM] Orion: provide GPIO method for enabling hardware assisted blinking
  [ARM] Orion: GPIO support
  [ARM] Orion: programable address map support
  ...

Conflicts:

	arch/arm/Kconfig
	arch/arm/Makefile
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parents d0d42df2 8f86dda3
...@@ -334,6 +334,16 @@ config ARCH_MXC ...@@ -334,6 +334,16 @@ config ARCH_MXC
help help
Support for Freescale MXC/iMX-based family of processors Support for Freescale MXC/iMX-based family of processors
config ARCH_ORION
bool "Marvell Orion"
depends on MMU
select PCI
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
Support for Marvell Orion System on Chip family.
config ARCH_PNX4008 config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile" bool "Philips Nexperia PNX4008 Mobile"
help help
...@@ -454,6 +464,8 @@ source "arch/arm/mach-omap1/Kconfig" ...@@ -454,6 +464,8 @@ source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig" source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig" source "arch/arm/plat-s3c/Kconfig"
...@@ -732,7 +744,7 @@ config LEDS ...@@ -732,7 +744,7 @@ config LEDS
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
ARCH_KS8695 ARCH_KS8695 || MACH_RD88F5182
help help
If you say Y here, the LEDs on your machine will be used If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status. to provide useful information about your current system status.
...@@ -967,7 +979,7 @@ config FPE_FASTFPE ...@@ -967,7 +979,7 @@ config FPE_FASTFPE
config VFP config VFP
bool "VFP-format floating point maths" bool "VFP-format floating point maths"
depends on CPU_V6 || CPU_ARM926T || CPU_V7 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
help help
Say Y to include VFP support code in the kernel. This is needed Say Y to include VFP support code in the kernel. This is needed
if your hardware includes a VFP unit. if your hardware includes a VFP unit.
......
...@@ -139,6 +139,7 @@ endif ...@@ -139,6 +139,7 @@ endif
machine-$(CONFIG_ARCH_KS8695) := ks8695 machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_ORION) := orion
machine-$(CONFIG_ARCH_MSM7X00A) := msm machine-$(CONFIG_ARCH_MSM7X00A) := msm
ifeq ($(CONFIG_ARCH_EBSA110),y) ifeq ($(CONFIG_ARCH_EBSA110),y)
......
...@@ -623,6 +623,12 @@ proc_types: ...@@ -623,6 +623,12 @@ proc_types:
b __armv4_mmu_cache_off b __armv4_mmu_cache_off
b __armv4_mmu_cache_flush b __armv4_mmu_cache_flush
.word 0x56055310 @ Feroceon
.word 0xfffffff0
b __armv4_mmu_cache_on
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
@ These match on the architecture ID @ These match on the architecture ID
.word 0x00020000 @ ARMv4T .word 0x00020000 @ ARMv4T
...@@ -641,7 +647,7 @@ proc_types: ...@@ -641,7 +647,7 @@ proc_types:
.word 0x000f0000 .word 0x000f0000
b __armv4_mmu_cache_on b __armv4_mmu_cache_on
b __armv4_mmu_cache_off b __armv4_mmu_cache_off
b __armv4_mmu_cache_flush b __armv5tej_mmu_cache_flush
.word 0x0007b000 @ ARMv6 .word 0x0007b000 @ ARMv6
.word 0x000ff000 .word 0x000ff000
...@@ -821,6 +827,13 @@ iflush: ...@@ -821,6 +827,13 @@ iflush:
mcr p15, 0, r10, c7, c10, 4 @ drain WB mcr p15, 0, r10, c7, c10, 4 @ drain WB
mov pc, lr mov pc, lr
__armv5tej_mmu_cache_flush:
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
mcr p15, 0, r0, c7, c5, 0 @ flush I cache
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
__armv4_mmu_cache_flush: __armv4_mmu_cache_flush:
mov r2, #64*1024 @ default: 32K dcache size (*2) mov r2, #64*1024 @ default: 32K dcache size (*2)
mov r11, #32 @ default: 32 byte line size mov r11, #32 @ default: 32 byte line size
......
This diff is collapsed.
if ARCH_ORION
menu "Orion Implementations"
config MACH_DB88F5281
bool "Marvell Orion-2 Development Board"
select I2C_BOARDINFO
help
Say 'Y' here if you want your kernel to support the
Marvell Orion-2 (88F5281) Development Board
config MACH_RD88F5182
bool "Marvell Orion-NAS Reference Design"
select I2C_BOARDINFO
help
Say 'Y' here if you want your kernel to support the
Marvell Orion-NAS (88F5182) RD2
config MACH_KUROBOX_PRO
bool "KuroBox Pro"
select I2C_BOARDINFO
help
Say 'Y' here if you want your kernel to support the
KuroBox Pro platform.
config MACH_DNS323
bool "D-Link DNS-323"
select I2C_BOARDINFO
help
Say 'Y' here if you want your kernel to support the
D-Link DNS-323 platform.
config MACH_TS209
bool "QNAP TS-109/TS-209"
help
Say 'Y' here if you want your kernel to support the
QNAP TS-109/TS-209 platform.
endmenu
endif
obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
obj-$(CONFIG_MACH_TS209) += ts209-setup.o
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
This diff is collapsed.
/*
* arch/arm/mach-orion/common.c
*
* Core functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
#include <asm/arch/orion.h>
#include "common.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc orion_io_desc[] __initdata = {
{
.virtual = ORION_REGS_BASE,
.pfn = __phys_to_pfn(ORION_REGS_BASE),
.length = ORION_REGS_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_IO_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
.length = ORION_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCI_IO_BASE,
.pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
.length = ORION_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_WA_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
.length = ORION_PCIE_WA_SIZE,
.type = MT_DEVICE
},
};
void __init orion_map_io(void)
{
iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
}
/*****************************************************************************
* UART
****************************************************************************/
static struct resource orion_uart_resources[] = {
{
.start = UART0_BASE,
.end = UART0_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_UART0,
.end = IRQ_ORION_UART0,
.flags = IORESOURCE_IRQ,
},
{
.start = UART1_BASE,
.end = UART1_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_UART1,
.end = IRQ_ORION_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port orion_uart_data[] = {
{
.mapbase = UART0_BASE,
.membase = (char *)UART0_BASE,
.irq = IRQ_ORION_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = ORION_TCLK,
},
{
.mapbase = UART1_BASE,
.membase = (char *)UART1_BASE,
.irq = IRQ_ORION_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = ORION_TCLK,
},
{ },
};
static struct platform_device orion_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = orion_uart_data,
},
.resource = orion_uart_resources,
.num_resources = ARRAY_SIZE(orion_uart_resources),
};
/*******************************************************************************
* USB Controller - 2 interfaces
******************************************************************************/
static struct resource orion_ehci0_resources[] = {
{
.start = ORION_USB0_REG_BASE,
.end = ORION_USB0_REG_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_USB0_CTRL,
.end = IRQ_ORION_USB0_CTRL,
.flags = IORESOURCE_IRQ,
},
};
static struct resource orion_ehci1_resources[] = {
{
.start = ORION_USB1_REG_BASE,
.end = ORION_USB1_REG_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_USB1_CTRL,
.end = IRQ_ORION_USB1_CTRL,
.flags = IORESOURCE_IRQ,
},
};
static u64 ehci_dmamask = 0xffffffffUL;
static struct platform_device orion_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = orion_ehci0_resources,
.num_resources = ARRAY_SIZE(orion_ehci0_resources),
};
static struct platform_device orion_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = orion_ehci1_resources,
.num_resources = ARRAY_SIZE(orion_ehci1_resources),
};
/*****************************************************************************
* Gigabit Ethernet port
* (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
****************************************************************************/
static struct resource orion_eth_shared_resources[] = {
{
.start = ORION_ETH_REG_BASE,
.end = ORION_ETH_REG_BASE + 0xffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion_eth_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = 1,
.resource = orion_eth_shared_resources,
};
static struct resource orion_eth_resources[] = {
{
.name = "eth irq",
.start = IRQ_ORION_ETH_SUM,
.end = IRQ_ORION_ETH_SUM,
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device orion_eth = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = orion_eth_resources,
};
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
orion_eth.dev.platform_data = eth_data;
platform_device_register(&orion_eth_shared);
platform_device_register(&orion_eth);
}
/*****************************************************************************
* I2C controller
* (The Orion and Discovery (MV643xx) families share the same I2C controller)
****************************************************************************/
static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion_i2c_resources[] = {
{
.name = "i2c base",
.start = I2C_BASE,
.end = I2C_BASE + 0x20 -1,
.flags = IORESOURCE_MEM,
},
{
.name = "i2c irq",
.start = IRQ_ORION_I2C,
.end = IRQ_ORION_I2C,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(orion_i2c_resources),
.resource = orion_i2c_resources,
.dev = {
.platform_data = &orion_i2c_pdata,
},
};
/*****************************************************************************
* General
****************************************************************************/
/*
* Identify device ID and rev from PCIE configuration header space '0'.
*/
static void orion_id(u32 *dev, u32 *rev, char **dev_name)
{
orion_pcie_id(dev, rev);
if (*dev == MV88F5281_DEV_ID) {
if (*rev == MV88F5281_REV_D2) {
*dev_name = "MV88F5281-D2";
} else if (*rev == MV88F5281_REV_D1) {
*dev_name = "MV88F5281-D1";
} else {
*dev_name = "MV88F5281-Rev-Unsupported";
}
} else if (*dev == MV88F5182_DEV_ID) {
if (*rev == MV88F5182_REV_A2) {
*dev_name = "MV88F5182-A2";
} else {
*dev_name = "MV88F5182-Rev-Unsupported";
}
} else if (*dev == MV88F5181_DEV_ID) {
if (*rev == MV88F5181_REV_B1) {
*dev_name = "MV88F5181-Rev-B1";
} else {
*dev_name = "MV88F5181-Rev-Unsupported";
}
} else {
*dev_name = "Device-Unknown";
}
}
void __init orion_init(void)
{
char *dev_name;
u32 dev, rev;
orion_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
/*
* Setup Orion address map
*/
orion_setup_cpu_wins();
orion_setup_usb_wins();
orion_setup_eth_wins();
orion_setup_pci_wins();
orion_setup_pcie_wins();
if (dev == MV88F5182_DEV_ID)
orion_setup_sata_wins();
/*
* REgister devices
*/
platform_device_register(&orion_uart);
platform_device_register(&orion_ehci0);
if (dev == MV88F5182_DEV_ID)
platform_device_register(&orion_ehci1);
platform_device_register(&orion_i2c);
}
#ifndef __ARCH_ORION_COMMON_H__
#define __ARCH_ORION_COMMON_H__
/*
* Basic Orion init functions used early by machine-setup.
*/
void __init orion_map_io(void);
void __init orion_init_irq(void);
void __init orion_init(void);
/*
* Enumerations and functions for Orion windows mapping. Used by Orion core
* functions to map its interfaces and by the machine-setup to map its on-
* board devices. Details in /mach-orion/addr-map.c
*/
enum orion_target {
ORION_DEV_BOOT = 0,
ORION_DEV0,
ORION_DEV1,
ORION_DEV2,
ORION_PCIE_MEM,
ORION_PCIE_IO,
ORION_PCI_MEM,
ORION_PCI_IO,
ORION_DDR,
ORION_REGS,
ORION_MAX_TARGETS
};
void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
void orion_setup_cpu_wins(void);
void orion_setup_eth_wins(void);
void orion_setup_usb_wins(void);
void orion_setup_pci_wins(void);
void orion_setup_pcie_wins(void);
void orion_setup_sata_wins(void);
/*
* Shared code used internally by other Orion core functions.
* (/mach-orion/pci.c)
*/
struct pci_sys_data;
struct pci_bus;
void orion_pcie_id(u32 *dev, u32 *rev);
u32 orion_pcie_local_bus_nr(void);
u32 orion_pci_local_bus_nr(void);
u32 orion_pci_local_dev_nr(void);
int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
/*
* Valid GPIO pins according to MPP setup, used by machine-setup.
* (/mach-orion/gpio.c).
*/
void __init orion_gpio_set_valid_pins(u32 pins);
void gpio_display(void); /* debug */
/*
* Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
*/
extern struct sys_timer orion_timer;
/*
* Pull in Orion Ethernet platform_data, used by machine-setup
*/
struct mv643xx_eth_platform_data;
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
#endif /* __ARCH_ORION_COMMON_H__ */
/*
* arch/arm/mach-orion/db88f5281-setup.c
*
* Marvell Orion-2 Development Board Setup
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/timer.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include "common.h"
/*****************************************************************************
* DB-88F5281 on board devices
****************************************************************************/
/*
* 512K NOR flash Device bus boot chip select
*/
#define DB88F5281_NOR_BOOT_BASE 0xf4000000
#define DB88F5281_NOR_BOOT_SIZE SZ_512K
/*
* 7-Segment on Device bus chip select 0
*/
#define DB88F5281_7SEG_BASE 0xfa000000
#define DB88F5281_7SEG_SIZE SZ_1K
/*
* 32M NOR flash on Device bus chip select 1
*/
#define DB88F5281_NOR_BASE 0xfc000000
#define DB88F5281_NOR_SIZE SZ_32M
/*
* 32M NAND flash on Device bus chip select 2
*/
#define DB88F5281_NAND_BASE 0xfa800000
#define DB88F5281_NAND_SIZE SZ_1K
/*
* PCI
*/
#define DB88F5281_PCI_SLOT0_OFFS 7
#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
/*****************************************************************************
* 512M NOR Flash on Device bus Boot CS
****************************************************************************/
static struct physmap_flash_data db88f5281_boot_flash_data = {
.width = 1, /* 8 bit bus width */
};
static struct resource db88f5281_boot_flash_resource = {
.flags = IORESOURCE_MEM,
.start = DB88F5281_NOR_BOOT_BASE,
.end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
};
static struct platform_device db88f5281_boot_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &db88f5281_boot_flash_data,
},
.num_resources = 1,
.resource = &db88f5281_boot_flash_resource,
};
/*****************************************************************************
* 32M NOR Flash on Device bus CS1
****************************************************************************/
static struct physmap_flash_data db88f5281_nor_flash_data = {
.width = 4, /* 32 bit bus width */
};
static struct resource db88f5281_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = DB88F5281_NOR_BASE,
.end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
};
static struct platform_device db88f5281_nor_flash = {
.name = "physmap-flash",
.id = 1,
.dev = {
.platform_data = &db88f5281_nor_flash_data,
},
.num_resources = 1,
.resource = &db88f5281_nor_flash_resource,
};
/*****************************************************************************
* 32M NAND Flash on Device bus CS2
****************************************************************************/
static struct mtd_partition db88f5281_nand_parts[] = {
{
.name = "kernel",
.offset = 0,
.size = SZ_2M,
},
{
.name = "root",
.offset = SZ_2M,
.size = (SZ_16M - SZ_2M),
},
{
.name = "user",
.offset = SZ_16M,
.size = SZ_8M,
},
{
.name = "recovery",
.offset = (SZ_16M + SZ_8M),
.size = SZ_8M,
},
};
static struct resource db88f5281_nand_resource = {
.flags = IORESOURCE_MEM,
.start = DB88F5281_NAND_BASE,
.end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
};
static struct orion_nand_data db88f5281_nand_data = {
.parts = db88f5281_nand_parts,
.nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
.cle = 0,
.ale = 1,
.width = 8,
};
static struct platform_device db88f5281_nand_flash = {
.name = "orion_nand",
.id = -1,
.dev = {
.platform_data = &db88f5281_nand_data,
},
.resource = &db88f5281_nand_resource,
.num_resources = 1,
};
/*****************************************************************************
* 7-Segment on Device bus CS0
* Dummy counter every 2 sec
****************************************************************************/
static void __iomem *db88f5281_7seg;
static struct timer_list db88f5281_timer;
static void db88f5281_7seg_event(unsigned long data)
{
static int count = 0;
writel(0, db88f5281_7seg + (count << 4));
count = (count + 1) & 7;
mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
}
static int __init db88f5281_7seg_init(void)
{
if (machine_is_db88f5281()) {
db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
DB88F5281_7SEG_SIZE);
if (!db88f5281_7seg) {
printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
return -EIO;
}
setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
}
return 0;
}
__initcall(db88f5281_7seg_init);
/*****************************************************************************
* PCI
****************************************************************************/
void __init db88f5281_pci_preinit(void)
{
int pin;
/*
* Configure PCI GPIO IRQ pins
*/
pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
}
pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield "
"to set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
}
}
static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/*
* PCIE IRQ is connected internally (not GPIO)
*/
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
/*
* PCI IRQs are connected via GPIOs
*/
switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
case 0:
return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
case 1:
case 2:
return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
default:
return -1;
}
}
static struct hw_pci db88f5281_pci __initdata = {
.nr_controllers = 2,
.preinit = db88f5281_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.map_irq = db88f5281_pci_map_irq,
};
static int __init db88f5281_pci_init(void)
{
if (machine_is_db88f5281())
pci_common_init(&db88f5281_pci);
return 0;
}
subsys_initcall(db88f5281_pci_init);
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data db88f5281_eth_data = {
.phy_addr = 8,
.force_phy_addr = 1,
};
/*****************************************************************************
* RTC DS1339 on I2C bus
****************************************************************************/
static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
.driver_name = "rtc-ds1307",
.type = "ds1339",
.addr = 0x68,
};
/*****************************************************************************
* General Setup
****************************************************************************/
static struct platform_device *db88f5281_devs[] __initdata = {
&db88f5281_boot_flash,
&db88f5281_nor_flash,
&db88f5281_nand_flash,
};
static void __init db88f5281_init(void)
{
/*
* Basic Orion setup. Need to be called early.
*/
orion_init();
/*
* Setup the CPU address decode windows for our on-board devices
*/
orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
DB88F5281_NOR_BOOT_SIZE, -1);
orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
DB88F5281_7SEG_SIZE, -1);
orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
DB88F5281_NOR_SIZE, -1);
orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
DB88F5281_NAND_SIZE, -1);
/*
* Setup Multiplexing Pins:
* MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
* MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
* MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
* MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
* MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
* MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
* MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
* MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
* MPP16: UART1_RX MPP17: UART1_TX
* MPP18: UART1_CTS MPP19: UART1_RTS
* MPP-DEV: DEV_D[16:31]
*/
orion_write(MPP_0_7_CTRL, 0x00222203);
orion_write(MPP_8_15_CTRL, 0x44000000);
orion_write(MPP_16_19_CTRL, 0);
orion_write(MPP_DEV_CTRL, 0);
orion_gpio_set_valid_pins(0x00003fc3);
platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
orion_eth_init(&db88f5281_eth_data);
}
MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
MACHINE_END
/*
* arch/arm/mach-orion/dns323-setup.c
*
* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include "common.h"
#define DNS323_GPIO_LED_RIGHT_AMBER 1
#define DNS323_GPIO_LED_LEFT_AMBER 2
#define DNS323_GPIO_LED_POWER 5
#define DNS323_GPIO_OVERTEMP 6
#define DNS323_GPIO_RTC 7
#define DNS323_GPIO_POWER_OFF 8
#define DNS323_GPIO_KEY_POWER 9
#define DNS323_GPIO_KEY_RESET 10
/****************************************************************************
* PCI setup
*/
static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/* PCI-E */
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
pr_err("%s: requested mapping for unknown bus\n", __func__);
return -1;
}
static struct hw_pci dns323_pci __initdata = {
.nr_controllers = 1,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.map_irq = dns323_pci_map_irq,
};
static int __init dns323_pci_init(void)
{
if (machine_is_dns323())
pci_common_init(&dns323_pci);
return 0;
}
subsys_initcall(dns323_pci_init);
/****************************************************************************
* Ethernet
*/
static struct mv643xx_eth_platform_data dns323_eth_data = {
.phy_addr = 8,
.force_phy_addr = 1,
};
/****************************************************************************
* 8MiB NOR flash (Spansion S29GL064M90TFIR4)
*
* Layout as used by D-Link:
* 0x00000000-0x00010000 : "MTD1"
* 0x00010000-0x00020000 : "MTD2"
* 0x00020000-0x001a0000 : "Linux Kernel"
* 0x001a0000-0x007d0000 : "File System"
* 0x007d0000-0x00800000 : "u-boot"
*/
#define DNS323_NOR_BOOT_BASE 0xf4000000
#define DNS323_NOR_BOOT_SIZE SZ_8M
static struct mtd_partition dns323_partitions[] = {
{
.name = "MTD1",
.size = 0x00010000,
.offset = 0,
}, {
.name = "MTD2",
.size = 0x00010000,
.offset = 0x00010000,
}, {
.name = "Linux Kernel",
.size = 0x00180000,
.offset = 0x00020000,
}, {
.name = "File System",
.size = 0x00630000,
.offset = 0x001A0000,
}, {
.name = "u-boot",
.size = 0x00030000,
.offset = 0x007d0000,
}
};
static struct physmap_flash_data dns323_nor_flash_data = {
.width = 1,
.parts = dns323_partitions,
.nr_parts = ARRAY_SIZE(dns323_partitions)
};
static struct resource dns323_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = DNS323_NOR_BOOT_BASE,
.end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1,
};
static struct platform_device dns323_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = { .platform_data = &dns323_nor_flash_data, },
.resource = &dns323_nor_flash_resource,
.num_resources = 1,
};
/****************************************************************************
* GPIO LEDs (simple - doesn't use hardware blinking support)
*/
static struct gpio_led dns323_leds[] = {
{
.name = "power:blue",
.gpio = DNS323_GPIO_LED_POWER,
.active_low = 1,
}, {
.name = "right:amber",
.gpio = DNS323_GPIO_LED_RIGHT_AMBER,
.active_low = 1,
}, {
.name = "left:amber",
.gpio = DNS323_GPIO_LED_LEFT_AMBER,
.active_low = 1,
},
};
static struct gpio_led_platform_data dns323_led_data = {
.num_leds = ARRAY_SIZE(dns323_leds),
.leds = dns323_leds,
};
static struct platform_device dns323_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = { .platform_data = &dns323_led_data, },
};
/****************************************************************************
* GPIO Attached Keys
*/
static struct gpio_keys_button dns323_buttons[] = {
{
.code = KEY_RESTART,
.gpio = DNS323_GPIO_KEY_RESET,
.desc = "Reset Button",
.active_low = 1,
},
{
.code = KEY_POWER,
.gpio = DNS323_GPIO_KEY_POWER,
.desc = "Power Button",
.active_low = 1,
}
};
static struct gpio_keys_platform_data dns323_button_data = {
.buttons = dns323_buttons,
.nbuttons = ARRAY_SIZE(dns323_buttons),
};
static struct platform_device dns323_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = { .platform_data = &dns323_button_data, },
};
/****************************************************************************
* General Setup
*/
static struct platform_device *dns323_plat_devices[] __initdata = {
&dns323_nor_flash,
&dns323_gpio_leds,
&dns323_button_device,
};
/*
* On the DNS-323 the following devices are attached via I2C:
*
* i2c addr | chip | description
* 0x3e | GMT G760Af | fan speed PWM controller
* 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
* 0x68 | ST M41T80 | RTC w/ alarm
*/
static struct i2c_board_info __initdata dns323_i2c_devices[] = {
{
I2C_BOARD_INFO("g760a", 0x3e),
.type = "g760a",
},
#if 0
/* this entry requires the new-style driver model lm75 driver,
* for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
{
I2C_BOARD_INFO("lm75", 0x48),
.type = "g751",
},
#endif
{
I2C_BOARD_INFO("rtc-m41t80", 0x68),
.type = "m41t80",
}
};
/* DNS-323 specific power off method */
static void dns323_power_off(void)
{
pr_info("%s: triggering power-off...\n", __func__);
gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
}
static void __init dns323_init(void)
{
/* Setup basic Orion functions. Need to be called early. */
orion_init();
/* setup flash mapping
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
*/
orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
DNS323_NOR_BOOT_SIZE, -1);
/* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070,
(0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
orion_write(MPP_0_7_CTRL, 0);
orion_write(MPP_8_15_CTRL, 0);
orion_write(MPP_16_19_CTRL, 0);
orion_write(MPP_DEV_CTRL, 0);
/* Define used GPIO pins
GPIO Map:
| 0 | | PEX_RST_OUT (not controlled by GPIO)
| 1 | Out | right amber LED (= sata ch0 LED) (low-active)
| 2 | Out | left amber LED (= sata ch1 LED) (low-active)
| 3 | Out | //unknown//
| 4 | Out | power button LED (low-active, together with pin #5)
| 5 | Out | power button LED (low-active, together with pin #4)
| 6 | In | GMT G751-2f overtemp. shutdown signal (low-active)
| 7 | In | M41T80 nIRQ/OUT/SQW signal
| 8 | Out | triggers power off (high-active)
| 9 | In | power button switch (low-active)
| 10 | In | reset button switch (low-active)
| 11 | Out | //unknown//
| 12 | Out | //unknown//
| 13 | Out | //unknown//
| 14 | Out | //unknown//
| 15 | Out | //unknown//
*/
orion_gpio_set_valid_pins(0x07f6);
/* register dns323 specific power-off method */
if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
|| (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
pr_err("DNS323: failed to setup power-off GPIO\n");
pm_power_off = dns323_power_off;
/* register flash and other platform devices */
platform_add_devices(dns323_plat_devices,
ARRAY_SIZE(dns323_plat_devices));
i2c_register_board_info(0, dns323_i2c_devices,
ARRAY_SIZE(dns323_i2c_devices));
orion_eth_init(&dns323_eth_data);
}
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
MACHINE_END
/*
* arch/arm/mach-orion/gpio.c
*
* GPIO functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <asm/gpio.h>
#include <asm/arch/orion.h>
#include "common.h"
static DEFINE_SPINLOCK(gpio_lock);
static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
void __init orion_gpio_set_valid_pins(u32 pins)
{
gpio_valid[0] = pins;
}
/*
* GENERIC_GPIO primitives
*/
int gpio_direction_input(unsigned pin)
{
unsigned long flags;
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
return -EINVAL;
}
spin_lock_irqsave(&gpio_lock, flags);
/*
* Some callers might have not used the gpio_request(),
* so flag this pin as requested now.
*/
if (!gpio_label[pin])
gpio_label[pin] = "?";
orion_setbits(GPIO_IO_CONF, 1 << pin);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
EXPORT_SYMBOL(gpio_direction_input);
int gpio_direction_output(unsigned pin, int value)
{
unsigned long flags;
int mask;
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
return -EINVAL;
}
spin_lock_irqsave(&gpio_lock, flags);
/*
* Some callers might have not used the gpio_request(),
* so flag this pin as requested now.
*/
if (!gpio_label[pin])
gpio_label[pin] = "?";
mask = 1 << pin;
orion_clrbits(GPIO_BLINK_EN, mask);
if (value)
orion_setbits(GPIO_OUT, mask);
else
orion_clrbits(GPIO_OUT, mask);
orion_clrbits(GPIO_IO_CONF, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
EXPORT_SYMBOL(gpio_direction_output);
int gpio_get_value(unsigned pin)
{
int val, mask = 1 << pin;
if (orion_read(GPIO_IO_CONF) & mask)
val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
else
val = orion_read(GPIO_OUT);
return val & mask;
}
EXPORT_SYMBOL(gpio_get_value);
void gpio_set_value(unsigned pin, int value)
{
unsigned long flags;
int mask = 1 << pin;
spin_lock_irqsave(&gpio_lock, flags);
orion_clrbits(GPIO_BLINK_EN, mask);
if (value)
orion_setbits(GPIO_OUT, mask);
else
orion_clrbits(GPIO_OUT, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(gpio_set_value);
void orion_gpio_set_blink(unsigned pin, int blink)
{
unsigned long flags;
int mask = 1 << pin;
spin_lock_irqsave(&gpio_lock, flags);
orion_clrbits(GPIO_OUT, mask);
if (blink)
orion_setbits(GPIO_BLINK_EN, mask);
else
orion_clrbits(GPIO_BLINK_EN, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(orion_gpio_set_blink);
int gpio_request(unsigned pin, const char *label)
{
int ret = 0;
unsigned long flags;
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
return -EINVAL;
}
spin_lock_irqsave(&gpio_lock, flags);
if (gpio_label[pin]) {
pr_debug("%s: GPIO %d already used as %s\n",
__FUNCTION__, pin, gpio_label[pin]);
ret = -EBUSY;
} else
gpio_label[pin] = label ? label : "?";
spin_unlock_irqrestore(&gpio_lock, flags);
return ret;
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned pin)
{
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
return;
}
if (!gpio_label[pin])
pr_warning("%s: GPIO %d already freed\n", __FUNCTION__, pin);
else
gpio_label[pin] = NULL;
}
EXPORT_SYMBOL(gpio_free);
/* Debug helper */
void gpio_display(void)
{
int i;
for (i = 0; i < GPIO_MAX; i++) {
printk(KERN_DEBUG "Pin-%d: ", i);
if (!test_bit(i, gpio_valid)) {
printk("non-GPIO\n");
} else if (!gpio_label[i]) {
printk("GPIO, free\n");
} else {
printk("GPIO, used by %s, ", gpio_label[i]);
if (orion_read(GPIO_IO_CONF) & (1 << i)) {
printk("input, active %s, level %s, edge %s\n",
((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
} else {
printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
}
}
}
printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
GPIO_OUT, orion_read(GPIO_OUT));
printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
GPIO_IN_POL, orion_read(GPIO_IN_POL));
printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
}
/*
* arch/arm/mach-orion/irq.c
*
* Core IRQ functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/gpio.h>
#include <asm/arch/orion.h>
#include "common.h"
/*****************************************************************************
* Orion GPIO IRQ
*
* GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
* value of the line or the opposite value.
*
* Level IRQ handlers: DATA_IN is used directly as cause register.
* Interrupt are masked by LEVEL_MASK registers.
* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
* Interrupt are masked by EDGE_MASK registers.
* Both-edge handlers: Similar to regular Edge handlers, but also swaps
* the polarity to catch the next line transaction.
* This is a race condition that might not perfectly
* work on some use cases.
*
* Every eight GPIO lines are grouped (OR'ed) before going up to main
* cause register.
*
* EDGE cause mask
* data-in /--------| |-----| |----\
* -----| |----- ---- to main cause reg
* X \----------------| |----/
* polarity LEVEL mask
*
****************************************************************************/
static void orion_gpio_irq_ack(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
/*
* Mask bit for level interrupt
*/
orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
else
/*
* Clear casue bit for egde interrupt
*/
orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
}
static void orion_gpio_irq_mask(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
else
orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
}
static void orion_gpio_irq_unmask(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
else
orion_setbits(GPIO_EDGE_MASK, 1 << pin);
}
static int orion_gpio_set_irq_type(u32 irq, u32 type)
{
int pin = irq_to_gpio(irq);
struct irq_desc *desc;
if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
printk(KERN_ERR "orion_gpio_set_irq_type failed "
"(irq %d, pin %d).\n", irq, pin);
return -EINVAL;
}
desc = irq_desc + irq;
switch (type) {
case IRQT_HIGH:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_LOW:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_RISING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_FALLING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_BOTHEDGE:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
/*
* set initial polarity based on current input level
*/
if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
& (1 << pin))
orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
else
orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
break;
default:
printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
return -EINVAL;
}
desc->status &= ~IRQ_TYPE_SENSE_MASK;
desc->status |= type & IRQ_TYPE_SENSE_MASK;
return 0;
}
static struct irq_chip orion_gpio_irq_chip = {
.name = "Orion-IRQ-GPIO",
.ack = orion_gpio_irq_ack,
.mask = orion_gpio_irq_mask,
.unmask = orion_gpio_irq_unmask,
.set_type = orion_gpio_set_irq_type,
};
static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
u32 cause, offs, pin;
BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
(orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
for (pin = offs; pin < offs + 8; pin++) {
if (cause & (1 << pin)) {
irq = gpio_to_irq(pin);
desc = irq_desc + irq;
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
/* Swap polarity (race with GPIO line) */
u32 polarity = orion_read(GPIO_IN_POL);
polarity ^= 1 << pin;
orion_write(GPIO_IN_POL, polarity);
}
desc_handle_irq(irq, desc);
}
}
}
static void __init orion_init_gpio_irq(void)
{
int i;
struct irq_desc *desc;
/*
* Mask and clear GPIO IRQ interrupts
*/
orion_write(GPIO_LEVEL_MASK, 0x0);
orion_write(GPIO_EDGE_MASK, 0x0);
orion_write(GPIO_EDGE_CAUSE, 0x0);
/*
* Register chained level handlers for GPIO IRQs by default.
* User can use set_type() if he wants to use edge types handlers.
*/
for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
desc = irq_desc + i;
desc->status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
}
/*****************************************************************************
* Orion Main IRQ
****************************************************************************/
static void orion_main_irq_mask(u32 irq)
{
orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
}
static void orion_main_irq_unmask(u32 irq)
{
orion_setbits(MAIN_IRQ_MASK, 1 << irq);
}
static struct irq_chip orion_main_irq_chip = {
.name = "Orion-IRQ-Main",
.ack = orion_main_irq_mask,
.mask = orion_main_irq_mask,
.unmask = orion_main_irq_unmask,
};
static void __init orion_init_main_irq(void)
{
int i;
/*
* Mask and clear Main IRQ interrupts
*/
orion_write(MAIN_IRQ_MASK, 0x0);
orion_write(MAIN_IRQ_CAUSE, 0x0);
/*
* Register level handler for Main IRQs
*/
for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
set_irq_chip(i, &orion_main_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void __init orion_init_irq(void)
{
orion_init_main_irq();
orion_init_gpio_irq();
}
/*
* arch/arm/mach-orion/kurobox_pro-setup.c
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include "common.h"
/*****************************************************************************
* KUROBOX-PRO Info
****************************************************************************/
/*
* 256K NOR flash Device bus boot chip select
*/
#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000
#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K
/*
* 256M NAND flash on Device bus chip select 1
*/
#define KUROBOX_PRO_NAND_BASE 0xfc000000
#define KUROBOX_PRO_NAND_SIZE SZ_2M
/*****************************************************************************
* 256MB NAND Flash on Device bus CS0
****************************************************************************/
static struct mtd_partition kurobox_pro_nand_parts[] = {
{
.name = "uImage",
.offset = 0,
.size = SZ_4M,
},
{
.name = "rootfs",
.offset = SZ_4M,
.size = SZ_64M,
},
{
.name = "extra",
.offset = SZ_4M + SZ_64M,
.size = SZ_256M - (SZ_4M + SZ_64M),
},
};
static struct resource kurobox_pro_nand_resource = {
.flags = IORESOURCE_MEM,
.start = KUROBOX_PRO_NAND_BASE,
.end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1,
};
static struct orion_nand_data kurobox_pro_nand_data = {
.parts = kurobox_pro_nand_parts,
.nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts),
.cle = 0,
.ale = 1,
.width = 8,
};
static struct platform_device kurobox_pro_nand_flash = {
.name = "orion_nand",
.id = -1,
.dev = {
.platform_data = &kurobox_pro_nand_data,
},
.resource = &kurobox_pro_nand_resource,
.num_resources = 1,
};
/*****************************************************************************
* 256KB NOR Flash on BOOT Device
****************************************************************************/
static struct physmap_flash_data kurobox_pro_nor_flash_data = {
.width = 1,
};
static struct resource kurobox_pro_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = KUROBOX_PRO_NOR_BOOT_BASE,
.end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1,
};
static struct platform_device kurobox_pro_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &kurobox_pro_nor_flash_data,
},
.num_resources = 1,
.resource = &kurobox_pro_nor_flash_resource,
};
/*****************************************************************************
* PCI
****************************************************************************/
static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/*
* PCI isn't used on the Kuro
*/
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
else
printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
return -1;
}
static struct hw_pci kurobox_pro_pci __initdata = {
.nr_controllers = 1,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.map_irq = kurobox_pro_pci_map_irq,
};
static int __init kurobox_pro_pci_init(void)
{
if (machine_is_kurobox_pro())
pci_common_init(&kurobox_pro_pci);
return 0;
}
subsys_initcall(kurobox_pro_pci_init);
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
.phy_addr = 8,
.force_phy_addr = 1,
};
/*****************************************************************************
* RTC 5C372a on I2C bus
****************************************************************************/
static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
.driver_name = "rtc-rs5c372",
.type = "rs5c372a",
.addr = 0x32,
};
/*****************************************************************************
* General Setup
****************************************************************************/
static struct platform_device *kurobox_pro_devices[] __initdata = {
&kurobox_pro_nor_flash,
&kurobox_pro_nand_flash,
};
static void __init kurobox_pro_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion_init();
/*
* Setup the CPU address decode windows for our devices
*/
orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
KUROBOX_PRO_NOR_BOOT_SIZE, -1);
orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
KUROBOX_PRO_NAND_SIZE, -1);
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
* Setup Multiplexing Pins --
* MPP[0-1] Not used
* MPP[2] GPIO Micon
* MPP[3] GPIO RTC
* MPP[4-5] Not used
* MPP[6] Nand Flash REn
* MPP[7] Nand Flash WEn
* MPP[8-11] Not used
* MPP[12] SATA 0 presence Indication
* MPP[13] SATA 1 presence Indication
* MPP[14] SATA 0 active Indication
* MPP[15] SATA 1 active indication
* MPP[16-19] Not used
*/
orion_write(MPP_0_7_CTRL, 0x44220003);
orion_write(MPP_8_15_CTRL, 0x55550000);
orion_write(MPP_16_19_CTRL, 0x0);
orion_gpio_set_valid_pins(0x0000000c);
platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
orion_eth_init(&kurobox_pro_eth_data);
}
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
MACHINE_END
This diff is collapsed.
/*
* arch/arm/mach-orion/rd88f5182-setup.c
*
* Marvell Orion-NAS Reference Design Setup
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include "common.h"
/*****************************************************************************
* RD-88F5182 Info
****************************************************************************/
/*
* 512K NOR flash Device bus boot chip select
*/
#define RD88F5182_NOR_BOOT_BASE 0xf4000000
#define RD88F5182_NOR_BOOT_SIZE SZ_512K
/*
* 16M NOR flash on Device bus chip select 1
*/
#define RD88F5182_NOR_BASE 0xfc000000
#define RD88F5182_NOR_SIZE SZ_16M
/*
* PCI
*/
#define RD88F5182_PCI_SLOT0_OFFS 7
#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
/*
* GPIO Debug LED
*/
#define RD88F5182_GPIO_DBG_LED 0
/*****************************************************************************
* 16M NOR Flash on Device bus CS1
****************************************************************************/
static struct physmap_flash_data rd88f5182_nor_flash_data = {
.width = 1,
};
static struct resource rd88f5182_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = RD88F5182_NOR_BASE,
.end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
};
static struct platform_device rd88f5182_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &rd88f5182_nor_flash_data,
},
.num_resources = 1,
.resource = &rd88f5182_nor_flash_resource,
};
#ifdef CONFIG_LEDS
/*****************************************************************************
* Use GPIO debug led as CPU active indication
****************************************************************************/
static void rd88f5182_dbgled_event(led_event_t evt)
{
int val;
if (evt == led_idle_end)
val = 1;
else if (evt == led_idle_start)
val = 0;
else
return;
gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
}
static int __init rd88f5182_dbgled_init(void)
{
int pin;
if (machine_is_rd88f5182()) {
pin = RD88F5182_GPIO_DBG_LED;
if (gpio_request(pin, "DBGLED") == 0) {
if (gpio_direction_output(pin, 0) != 0) {
printk(KERN_ERR "rd88f5182_dbgled_init failed "
"to set output pin %d\n", pin);
gpio_free(pin);
return 0;
}
} else {
printk(KERN_ERR "rd88f5182_dbgled_init failed "
"to request gpio %d\n", pin);
return 0;
}
leds_event = rd88f5182_dbgled_event;
}
return 0;
}
__initcall(rd88f5182_dbgled_init);
#endif
/*****************************************************************************
* PCI
****************************************************************************/
void __init rd88f5182_pci_preinit(void)
{
int pin;
/*
* Configure PCI GPIO IRQ pins
*/
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
if (gpio_request(pin, "PCI IntA") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
}
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
if (gpio_request(pin, "PCI IntB") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQT_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
}
}
static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/*
* PCI-E isn't used on the RD2
*/
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
/*
* PCI IRQs are connected via GPIOs
*/
switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
case 0:
if (pin == 1)
return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
else
return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
default:
return -1;
}
}
static struct hw_pci rd88f5182_pci __initdata = {
.nr_controllers = 2,
.preinit = rd88f5182_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.map_irq = rd88f5182_pci_map_irq,
};
static int __init rd88f5182_pci_init(void)
{
if (machine_is_rd88f5182())
pci_common_init(&rd88f5182_pci);
return 0;
}
subsys_initcall(rd88f5182_pci_init);
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
.phy_addr = 8,
.force_phy_addr = 1,
};
/*****************************************************************************
* RTC DS1338 on I2C bus
****************************************************************************/
static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
.driver_name = "rtc-ds1307",
.type = "ds1338",
.addr = 0x68,
};
/*****************************************************************************
* General Setup
****************************************************************************/
static struct platform_device *rd88f5182_devices[] __initdata = {
&rd88f5182_nor_flash,
};
static void __init rd88f5182_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion_init();
/*
* Setup the CPU address decode windows for our devices
*/
orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
RD88F5182_NOR_BOOT_SIZE, -1);
orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
RD88F5182_NOR_SIZE, -1);
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
* Setup Multiplexing Pins --
* MPP[0] Debug Led (GPIO - Out)
* MPP[1] Debug Led (GPIO - Out)
* MPP[2] N/A
* MPP[3] RTC_Int (GPIO - In)
* MPP[4] GPIO
* MPP[5] GPIO
* MPP[6] PCI_intA (GPIO - In)
* MPP[7] PCI_intB (GPIO - In)
* MPP[8-11] N/A
* MPP[12] SATA 0 presence Indication
* MPP[13] SATA 1 presence Indication
* MPP[14] SATA 0 active Indication
* MPP[15] SATA 1 active indication
* MPP[16-19] Not used
* MPP[20] PCI Clock to MV88F5182
* MPP[21] PCI Clock to mini PCI CON11
* MPP[22] USB 0 over current indication
* MPP[23] USB 1 over current indication
* MPP[24] USB 1 over current enable
* MPP[25] USB 0 over current enable
*/
orion_write(MPP_0_7_CTRL, 0x00000003);
orion_write(MPP_8_15_CTRL, 0x55550000);
orion_write(MPP_16_19_CTRL, 0x5555);
orion_gpio_set_valid_pins(0x000000fb);
platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
orion_eth_init(&rd88f5182_eth_data);
}
MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
MACHINE_END
/*
* arch/arm/mach-orion/time.c
*
* Core time functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mach/time.h>
#include <asm/arch/orion.h>
#include "common.h"
/*
* Timer0: clock_event_device, Tick.
* Timer1: clocksource, Free running.
* WatchDog: Not used.
*
* Timers are counting down.
*/
#define CLOCKEVENT 0
#define CLOCKSOURCE 1
/*
* Timers bits
*/
#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
#define TIMER_EN(x) (1 << ((x) * 2))
#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
#define BRIDGE_INT_TIMER_WD (1 << 3)
#define TIMER_WD_EN (1 << 4)
#define TIMER_WD_RELOAD_EN (1 << 5)
static cycle_t orion_clksrc_read(void)
{
return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
}
static struct clocksource orion_clksrc = {
.name = "orion_clocksource",
.shift = 20,
.rating = 300,
.read = orion_clksrc_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static int
orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
{
unsigned long flags;
if (delta == 0)
return -ETIME;
local_irq_save(flags);
/*
* Clear and enable timer interrupt bit
*/
orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
/*
* Setup new timer value
*/
orion_write(TIMER_VAL(CLOCKEVENT), delta);
/*
* Disable auto reload and kickoff the timer
*/
orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
local_irq_restore(flags);
return 0;
}
static void
orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
unsigned long flags;
local_irq_save(flags);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
/*
* Setup latch cycles in timer and enable reload interrupt.
*/
orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
TIMER_EN(CLOCKEVENT));
} else {
/*
* Disable timer and interrupt
*/
orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
TIMER_EN(CLOCKEVENT));
}
local_irq_restore(flags);
}
static struct clock_event_device orion_clkevt = {
.name = "orion_tick",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.rating = 300,
.cpumask = CPU_MASK_CPU0,
.set_next_event = orion_clkevt_next_event,
.set_mode = orion_clkevt_mode,
};
static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
{
/*
* Clear cause bit and do event
*/
orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
orion_clkevt.event_handler(&orion_clkevt);
return IRQ_HANDLED;
}
static struct irqaction orion_timer_irq = {
.name = "orion_tick",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = orion_timer_interrupt
};
static void orion_timer_init(void)
{
/*
* Setup clocksource free running timer (no interrupt on reload)
*/
orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
TIMER_EN(CLOCKSOURCE));
/*
* Register clocksource
*/
orion_clksrc.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
clocksource_register(&orion_clksrc);
/*
* Connect and enable tick handler
*/
setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
/*
* Register clockevent
*/
orion_clkevt.mult =
div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
orion_clkevt.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &orion_clkevt);
orion_clkevt.min_delta_ns =
clockevent_delta2ns(1, &orion_clkevt);
clockevents_register_device(&orion_clkevt);
}
struct sys_timer orion_timer = {
.init = orion_timer_init,
};
This diff is collapsed.
...@@ -342,6 +342,27 @@ config CPU_XSC3 ...@@ -342,6 +342,27 @@ config CPU_XSC3
select CPU_TLB_V4WBI if MMU select CPU_TLB_V4WBI if MMU
select IO_36 select IO_36
# Feroceon
config CPU_FEROCEON
bool
depends on ARCH_ORION
default y
select CPU_32v5
select CPU_ABRT_EV5T
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU
select CPU_TLB_V4WBI if MMU
config CPU_FEROCEON_OLD_ID
bool "Accept early Feroceon cores with an ARM926 ID"
depends on CPU_FEROCEON && !CPU_ARM926T
default y
help
This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and early Feroceon-2850.
# ARMv6 # ARMv6
config CPU_V6 config CPU_V6
bool "Support ARM V6 processor" bool "Support ARM V6 processor"
...@@ -539,7 +560,7 @@ comment "Processor Features" ...@@ -539,7 +560,7 @@ comment "Processor Features"
config ARM_THUMB config ARM_THUMB
bool "Support Thumb user binaries" bool "Support Thumb user binaries"
depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
default y default y
help help
Say Y if you want to include kernel support for running user space Say Y if you want to include kernel support for running user space
...@@ -601,7 +622,7 @@ config CPU_DCACHE_SIZE ...@@ -601,7 +622,7 @@ config CPU_DCACHE_SIZE
config CPU_DCACHE_WRITETHROUGH config CPU_DCACHE_WRITETHROUGH
bool "Force write through D-cache" bool "Force write through D-cache"
depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
default y if CPU_ARM925T default y if CPU_ARM925T
help help
Say Y here to use the data cache in writethrough mode. Unless you Say Y here to use the data cache in writethrough mode. Unless you
......
...@@ -68,6 +68,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o ...@@ -68,6 +68,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o
obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o
obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o
obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o
obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o
obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6) += proc-v6.o
obj-$(CONFIG_CPU_V7) += proc-v7.o obj-$(CONFIG_CPU_V7) += proc-v7.o
......
This diff is collapsed.
...@@ -361,12 +361,6 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id) ...@@ -361,12 +361,6 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
else else
pdata.timeout = 1000; /* 1 second */ pdata.timeout = 1000; /* 1 second */
prop = of_get_property(np, "retries", NULL);
if (prop)
pdata.retries = *prop;
else
pdata.retries = 1;
pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id); pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id);
if (!pdev) if (!pdev)
return -ENOMEM; return -ENOMEM;
......
...@@ -411,7 +411,6 @@ static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = { ...@@ -411,7 +411,6 @@ static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
.freq_m = 8, .freq_m = 8,
.freq_n = 3, .freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */ .timeout = 1000, /* Default timeout of 1 second */
.retries = 1,
}; };
static struct resource mv64xxx_i2c_resources[] = { static struct resource mv64xxx_i2c_resources[] = {
......
...@@ -643,7 +643,7 @@ config I2C_PCA_ISA ...@@ -643,7 +643,7 @@ config I2C_PCA_ISA
config I2C_MV64XXX config I2C_MV64XXX
tristate "Marvell mv64xxx I2C Controller" tristate "Marvell mv64xxx I2C Controller"
depends on MV64X60 && EXPERIMENTAL depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL
help help
If you say yes to this option, support will be included for the If you say yes to this option, support will be included for the
built-in I2C interface on the Marvell 64xxx line of host bridges. built-in I2C interface on the Marvell 64xxx line of host bridges.
......
/* /*
* Driver for the i2c controller on the Marvell line of host bridges for MIPS * Driver for the i2c controller on the Marvell line of host bridges
* and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0). * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
* *
* Author: Mark A. Greer <mgreer@mvista.com> * Author: Mark A. Greer <mgreer@mvista.com>
* *
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/mv643xx.h> #include <linux/mv643xx_i2c.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <asm/io.h> #include <asm/io.h>
...@@ -86,6 +86,7 @@ struct mv64xxx_i2c_data { ...@@ -86,6 +86,7 @@ struct mv64xxx_i2c_data {
u32 cntl_bits; u32 cntl_bits;
void __iomem *reg_base; void __iomem *reg_base;
u32 reg_base_p; u32 reg_base_p;
u32 reg_size;
u32 addr1; u32 addr1;
u32 addr2; u32 addr2;
u32 bytes_left; u32 bytes_left;
...@@ -463,17 +464,20 @@ static int __devinit ...@@ -463,17 +464,20 @@ static int __devinit
mv64xxx_i2c_map_regs(struct platform_device *pd, mv64xxx_i2c_map_regs(struct platform_device *pd,
struct mv64xxx_i2c_data *drv_data) struct mv64xxx_i2c_data *drv_data)
{ {
struct resource *r; int size;
struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0);
if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) && if (!r)
request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE, return -ENODEV;
drv_data->adapter.name)) {
drv_data->reg_base = ioremap(r->start, size = r->end - r->start + 1;
MV64XXX_I2C_REG_BLOCK_SIZE);
drv_data->reg_base_p = r->start; if (!request_mem_region(r->start, size, drv_data->adapter.name))
} else return -EBUSY;
return -ENOMEM;
drv_data->reg_base = ioremap(r->start, size);
drv_data->reg_base_p = r->start;
drv_data->reg_size = size;
return 0; return 0;
} }
...@@ -483,8 +487,7 @@ mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) ...@@ -483,8 +487,7 @@ mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
{ {
if (drv_data->reg_base) { if (drv_data->reg_base) {
iounmap(drv_data->reg_base); iounmap(drv_data->reg_base);
release_mem_region(drv_data->reg_base_p, release_mem_region(drv_data->reg_base_p, drv_data->reg_size);
MV64XXX_I2C_REG_BLOCK_SIZE);
} }
drv_data->reg_base = NULL; drv_data->reg_base = NULL;
...@@ -529,7 +532,6 @@ mv64xxx_i2c_probe(struct platform_device *pd) ...@@ -529,7 +532,6 @@ mv64xxx_i2c_probe(struct platform_device *pd)
drv_data->adapter.owner = THIS_MODULE; drv_data->adapter.owner = THIS_MODULE;
drv_data->adapter.class = I2C_CLASS_HWMON; drv_data->adapter.class = I2C_CLASS_HWMON;
drv_data->adapter.timeout = pdata->timeout; drv_data->adapter.timeout = pdata->timeout;
drv_data->adapter.retries = pdata->retries;
drv_data->adapter.nr = pd->id; drv_data->adapter.nr = pd->id;
platform_set_drvdata(pd, drv_data); platform_set_drvdata(pd, drv_data);
i2c_set_adapdata(&drv_data->adapter, drv_data); i2c_set_adapdata(&drv_data->adapter, drv_data);
......
/*
* linux/include/asm-arm/arch-orion/debug-macro.S
*
* Debugging macro include header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
.macro addruart,rx
mov \rx, #0xf1000000
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
/*
* include/asm-arm/arch-orion/memory.h
*
* Marvell Orion memory definitions
*/
#ifndef __ASM_ARCH_MMU_H
#define __ASM_ARCH_MMU_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment