Commit c097338e authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Tony Lindgren

ARM: dts: dra7: cpsw: fix clocks tree

Current clocks tree definition for CPSW/CPTS doesn't
correspond TRM for dra7/am57 SoCs.

CPTS: has to be sourced from gmac_rft_clk_mux clock
CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 ->
      -> GMAC_MAIN_CLK (125 MHZ)

Hence, correct clock tree for GMAC_MAIN_CLK and use proper
clock for CPTS. This also require updating of CPTS clock
multiplier.
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: default avatarMugunthan V N <mugunthanvnm@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent dbb9c196
...@@ -1719,7 +1719,7 @@ crossbar_mpu: crossbar@4a002a48 { ...@@ -1719,7 +1719,7 @@ crossbar_mpu: crossbar@4a002a48 {
mac: ethernet@48484000 { mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw"; compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac"; ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
clock-names = "fck", "cpts"; clock-names = "fck", "cpts";
cpdma_channels = <8>; cpdma_channels = <8>;
ale_entries = <1024>; ale_entries = <1024>;
...@@ -1728,7 +1728,7 @@ mac: ethernet@48484000 { ...@@ -1728,7 +1728,7 @@ mac: ethernet@48484000 {
mac_control = <0x20>; mac_control = <0x20>;
slaves = <2>; slaves = <2>;
active_slave = <0>; active_slave = <0>;
cpts_clock_mult = <0x80000000>; cpts_clock_mult = <0x784CFE14>;
cpts_clock_shift = <29>; cpts_clock_shift = <29>;
reg = <0x48484000 0x1000 reg = <0x48484000 0x1000
0x48485200 0x2E00>; 0x48485200 0x2E00>;
......
...@@ -1003,6 +1003,14 @@ gmac_250m_dclk_div: gmac_250m_dclk_div@19c { ...@@ -1003,6 +1003,14 @@ gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
ti,index-power-of-two; ti,index-power-of-two;
}; };
gmac_main_clk: gmac_main_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&gmac_250m_dclk_div>;
clock-mult = <1>;
clock-div = <2>;
};
l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,divider-clock"; compatible = "ti,divider-clock";
...@@ -1726,14 +1734,6 @@ rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { ...@@ -1726,14 +1734,6 @@ rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
reg = <0x13d0>; reg = <0x13d0>;
}; };
gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_gmac_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
......
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