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Commit c0bf9449 authored by Martin Dalecki's avatar Martin Dalecki Committed by Linus Torvalds
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[PATCH] 2.5.5 IDE cleanup 12 

1. Add some notes to Documentation/driver-model.txt about how and
     and where to mount the driverfs.

2. Reorganize and prepare the PCI scanning code for proper device
dependant splitup. Basically tedious cleanup of macro games.

3. Use struct pci_dev name field as the name of PCI host dapaters
instead of invention ambigious IDE special names. This makes
the kernel bootup messages look a bit shifted, since those names are bit
longer, but makes up for consistance and should allow one later
to rearage things to fit into the generic PCI device initialization
mechanisms provided by the kernel.

4. Set 3. Allowed us to make the host chip specific
pci_init_xxx class functions have the proper signature of
module initializers. This will make it possible to make true
modules out of them later.

5. Make some functions in cmd64x.c static which where not used
elsewhere.

6. rename ide_special_settings to trust_pci_irq - this is reflecting
it's functionality better. And make it match the pci device vendor
as well as the device ID. It was a BUG to match only the device id!.

7. Make the chanell setup more tollerant for BIOS-es which don't
report IO and MEM bases properly. The code found previously there
tryed but was inconsistant.

8. Start to use proper terminology in ide-pci.c: host chip, channel,
drive instead of hwif, port, drive...

9. Enlarge the name field from ide_hwif_t to 64 bytes. It was only 6
previously and there where custom names there which where exceeding
this!!! But since we use the proper pci devce name there now instead,
we had to extend the size of this field anyway.

10. Add some explanatory comments and fix misguiding comments here and
there.

11. Kill the proc_ide_write_config and proc_ide_read_config brain
damage! Those where backdoors to the pci configuration registers on PCI
devices and IO registers on directly connected ISA ATA controllers.
They didn't discrement between them!

Access to both of them *simply* doesn't belong into an operating system,
which is supposed to abstract out the access to hardware! Did I mention
that access to both can be done from user land without an IDE special
interface! Any program which was using them (I hardly beleve there is
one) just deserves to loose. The programmer responsible for it
deserves to be fired immediately.

12. Move ide_map_xx and ide_unmap_xx tinny bio level wrappers away
from the "global" ide.h to where those are actually used and kill
trivial wrappers for otherwise generic bio_ routines. Just fighting
code obfuscation. The "rq->bio is used or is not there" brain
damage in ide-taskfile.c has to be fixed later. Possibly by killing
ide-taskfile.c alltogether, becouse this should be a driver for
users and not a driver for ATA disk disaster recovery companys...

13. Kill hwif->pci_devid and hwif->pci_venid. Just use the already
present hwif->pci_dev field instead.

14. Kill unused big switch ide_reinit_drive function. This silly
functon was switching upon every possible device driver cathegory
and calling the correspondng reinit function directly. This
idiocy was fortunately not used.

That's all... Most will be clear if one starts looking at the changes
in ide.h of course...

In contrast to the previous patches this one is actually fixing two
serious bugs.


The next direct step will be to kill the sigle place global PCI device
type recognition list from ide-pci.c by pushing the entries to where
they belong -> the host chips setup modules.
parent ce43a9ec
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Showing with 543 additions and 900 deletions
Documentation/driver-model.txt
View file @ c0bf9449
......@@ -118,7 +118,18 @@ User Interface
By virtue of having a complete hierarchical view of all the devices in the
system, exporting a complete hierarchical view to userspace becomes relatively
easy.
easy. This has been accomplished by implementing a special purpose virtual
file system named driverfs. It is hence possible for the user to mount the
whole driverfs on a particular mount point in the unified UNIX file hierarchy.
This can be done permanently by providing the following entry into the
/dev/fstab (under the provision that the mount point does exist, of course):
none /devices driverfs defaults 0 0
Or by hand on the command line:
~: mount -t driverfs none /devices
Whenever a device is inserted into the tree, a directory is created for it.
This directory may be populated at each layer of discovery - the global layer,
......@@ -343,6 +354,8 @@ user requests the system to suspend, it will walk the device tree, as exported
via driverfs, and tell each device to go to sleep. It will do this multiple
times based on what the system policy is.
[ FIXME: URL pointer to the corresponding utility is missing here! ]
Device resume should happen in the same manner when the system awakens.
Each suspend stage is described below:
......
drivers/ide/aec62xx.c
View file @ c0bf9449
......@@ -518,11 +518,11 @@ int aec62xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
#endif /* CONFIG_BLK_DEV_IDEDMA */
#endif /* CONFIG_AEC62XX_TUNING */
unsigned int __init pci_init_aec62xx (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_aec62xx (struct pci_dev *dev)
{
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
printk("%s: ROM enabled at 0x%08lx\n", dev->name, dev->resource[PCI_ROM_RESOURCE].start);
}
#if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
......
drivers/ide/alim15x3.c
View file @ c0bf9449
......@@ -504,7 +504,7 @@ static int ali15x3_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_ali15x3 (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_ali15x3(struct pci_dev *dev)
{
unsigned long fixdma_base = pci_resource_start(dev, 4);
......@@ -523,7 +523,7 @@ unsigned int __init pci_init_ali15x3 (struct pci_dev *dev, const char *name)
outb(inb(fixdma_base+2) & 0x60, fixdma_base+2);
if (inb(fixdma_base+2) & 0x80)
printk("%s: simplex device: DMA will fail!!\n", name);
printk("%s: simplex device: DMA will fail!!\n", dev->name);
}
#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
......
drivers/ide/amd74xx.c
View file @ c0bf9449
......@@ -406,13 +406,13 @@ int amd74xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_amd74xx (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_amd74xx(struct pci_dev *dev)
{
unsigned long fixdma_base = pci_resource_start(dev, 4);
#ifdef CONFIG_BLK_DEV_IDEDMA
if (!amd74xx_swdma_check(dev))
printk("%s: disabling single-word DMA support (revision < C4)\n", name);
printk("%s: disabling single-word DMA support (revision < C4)\n", dev->name);
#endif /* CONFIG_BLK_DEV_IDEDMA */
if (!fixdma_base) {
......@@ -426,7 +426,7 @@ unsigned int __init pci_init_amd74xx (struct pci_dev *dev, const char *name)
outb(inb(fixdma_base+2) & 0x60, fixdma_base+2);
if (inb(fixdma_base+2) & 0x80)
printk("%s: simplex device: DMA will fail!!\n", name);
printk("%s: simplex device: DMA will fail!!\n", dev->name);
}
#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
if (!amd74xx_proc) {
......
drivers/ide/cmd64x.c
View file @ c0bf9449
......@@ -954,7 +954,7 @@ static int cmd680_busproc (ide_drive_t * drive, int state)
return 0;
}
void cmd680_reset (ide_drive_t *drive)
static void cmd680_reset (ide_drive_t *drive)
{
#if 0
ide_hwif_t *hwif = HWIF(drive);
......@@ -966,7 +966,7 @@ void cmd680_reset (ide_drive_t *drive)
#endif
}
unsigned int cmd680_pci_init (struct pci_dev *dev, const char *name)
static unsigned int cmd680_pci_init(struct pci_dev *dev)
{
u8 tmpbyte = 0;
pci_write_config_byte(dev, 0x80, 0x00);
......@@ -992,7 +992,7 @@ unsigned int cmd680_pci_init (struct pci_dev *dev, const char *name)
return 0;
}
unsigned int cmd64x_pci_init (struct pci_dev *dev, const char *name)
static unsigned int cmd64x_pci_init(struct pci_dev *dev)
{
unsigned char mrdmode;
unsigned int class_rev;
......@@ -1003,7 +1003,7 @@ unsigned int cmd64x_pci_init (struct pci_dev *dev, const char *name)
#ifdef __i386__
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
printk("%s: ROM enabled at 0x%08lx\n", dev->name, dev->resource[PCI_ROM_RESOURCE].start);
}
#endif
......@@ -1011,7 +1011,7 @@ unsigned int cmd64x_pci_init (struct pci_dev *dev, const char *name)
case PCI_DEVICE_ID_CMD_643:
break;
case PCI_DEVICE_ID_CMD_646:
printk("%s: chipset revision 0x%02X, ", name, class_rev);
printk("%s: chipset revision 0x%02X, ", dev->name, class_rev);
switch(class_rev) {
case 0x07:
case 0x05:
......@@ -1081,11 +1081,11 @@ unsigned int cmd64x_pci_init (struct pci_dev *dev, const char *name)
return 0;
}
unsigned int __init pci_init_cmd64x (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_cmd64x(struct pci_dev *dev)
{
if (dev->device == PCI_DEVICE_ID_CMD_680)
return cmd680_pci_init (dev, name);
return cmd64x_pci_init (dev, name);
return cmd680_pci_init (dev);
return cmd64x_pci_init (dev);
}
unsigned int cmd680_ata66 (ide_hwif_t *hwif)
......
drivers/ide/cs5530.c
View file @ c0bf9449
......@@ -251,7 +251,7 @@ int cs5530_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
/*
* Initialize the cs5530 bridge for reliable IDE DMA operation.
*/
unsigned int __init pci_init_cs5530 (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_cs5530(struct pci_dev *dev)
{
struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
unsigned short pcicmd = 0;
......@@ -278,11 +278,11 @@ unsigned int __init pci_init_cs5530 (struct pci_dev *dev, const char *name)
}
}
if (!master_0) {
printk("%s: unable to locate PCI MASTER function\n", name);
printk("%s: unable to locate PCI MASTER function\n", dev->name);
return 0;
}
if (!cs5530_0) {
printk("%s: unable to locate CS5530 LEGACY function\n", name);
printk("%s: unable to locate CS5530 LEGACY function\n", dev->name);
return 0;
}
......
drivers/ide/cy82c693.c
View file @ c0bf9449
......@@ -383,7 +383,7 @@ static void cy82c693_tune_drive (ide_drive_t *drive, byte pio)
* the device prior to INIT.
*/
unsigned int __init pci_init_cy82c693(struct pci_dev *dev, const char *name)
unsigned int __init pci_init_cy82c693(struct pci_dev *dev)
{
#ifdef CY82C693_SETDMA_CLOCK
byte data;
......@@ -399,7 +399,7 @@ unsigned int __init pci_init_cy82c693(struct pci_dev *dev, const char *name)
data = IN_BYTE(CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO
printk (KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n", name, data);
printk (KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n", dev->name, data);
#endif /* CY82C693_DEBUG_INFO */
/*
......@@ -420,7 +420,7 @@ unsigned int __init pci_init_cy82c693(struct pci_dev *dev, const char *name)
OUT_BYTE(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO
printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n", name, data);
printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n", dev->name, data);
#endif /* CY82C693_DEBUG_INFO */
#endif /* CY82C693_SETDMA_CLOCK */
......@@ -433,7 +433,7 @@ unsigned int __init pci_init_cy82c693(struct pci_dev *dev, const char *name)
void __init ide_init_cy82c693(ide_hwif_t *hwif)
{
hwif->chipset = ide_cy82c693;
hwif->tuneproc = &cy82c693_tune_drive;
hwif->tuneproc = cy82c693_tune_drive;
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
hwif->autodma = 0;
......@@ -441,7 +441,7 @@ void __init ide_init_cy82c693(ide_hwif_t *hwif)
#ifdef CONFIG_BLK_DEV_IDEDMA
if (hwif->dma_base) {
hwif->highmem = 1;
hwif->dmaproc = &cy82c693_dmaproc;
hwif->dmaproc = cy82c693_dmaproc;
if (!noautodma)
hwif->autodma = 1;
}
......
drivers/ide/hpt34x.c
View file @ c0bf9449
......@@ -357,7 +357,7 @@ int hpt34x_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
*/
#define HPT34X_PCI_INIT_REG 0x80
unsigned int __init pci_init_hpt34x (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_hpt34x(struct pci_dev *dev)
{
int i = 0;
unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
......
drivers/ide/hpt366.c
View file @ c0bf9449
......@@ -1097,7 +1097,7 @@ static void __init init_hpt370(struct pci_dev *dev)
udelay(100);
}
unsigned int __init pci_init_hpt366 (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_hpt366(struct pci_dev *dev)
{
byte test = 0;
......
drivers/ide/ide-pci.c
View file @ c0bf9449
......@@ -32,339 +32,226 @@
#include <asm/io.h>
#include <asm/irq.h>
#define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0})
#define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1})
#define DEVID_MPIIX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX})
#define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1})
#define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB})
#define DEVID_ICH0 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1})
#define DEVID_PIIX4E2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1})
#define DEVID_ICH ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1})
#define DEVID_PIIX4U2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1})
#define DEVID_PIIX4NX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX})
#define DEVID_ICH2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9})
#define DEVID_ICH2M ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8})
#define DEVID_ICH3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10})
#define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
#define DEVID_MR_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1})
#define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
#define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
#define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
#define DEVID_PDC20265 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265})
#define DEVID_PDC20267 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267})
#define DEVID_PDC20268 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268})
#define DEVID_PDC20268R ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268R})
#define DEVID_PDC20269 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269})
#define DEVID_PDC20275 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275})
#define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000})
#define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001})
#define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
#define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640})
#define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643})
#define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646})
#define DEVID_CMD648 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648})
#define DEVID_CMD649 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649})
#define DEVID_CMD680 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_680})
#define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513})
#define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621})
#define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558})
#define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825})
#define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290})
#define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410})
#define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415})
#define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565})
#define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF})
#define DEVID_AEC6260 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860})
#define DEVID_AEC6260R ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R})
#define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
#define DEVID_UM8673F ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F})
#define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A})
#define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF})
#define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343})
#define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366})
#define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229})
#define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693})
#define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013})
#define DEVID_CS5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE})
#define DEVID_AMD7401 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401})
#define DEVID_AMD7409 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409})
#define DEVID_AMD7411 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411})
#define DEVID_AMD7441 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7441})
#define DEVID_PDCADMA ((ide_pci_devid_t){PCI_VENDOR_ID_PDC, PCI_DEVICE_ID_PDC_1841})
#define DEVID_SLC90E66 ((ide_pci_devid_t){PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1})
#define DEVID_OSB4 ((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE})
#define DEVID_CSB5 ((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE})
#define DEVID_ITE8172G ((ide_pci_devid_t){PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G})
/* Missing PCI device IDs: */
#define PCI_VENDOR_ID_HINT 0x3388
#define PCI_DEVICE_ID_HINT 0x8013
#define IDE_IGNORE ((void *)-1)
#define IDE_NO_DRIVER ((void *)-2)
#ifdef CONFIG_BLK_DEV_AEC62XX
extern unsigned int pci_init_aec62xx(struct pci_dev *, const char *);
extern unsigned int pci_init_aec62xx(struct pci_dev *);
extern unsigned int ata66_aec62xx(ide_hwif_t *);
extern void ide_init_aec62xx(ide_hwif_t *);
extern void ide_dmacapable_aec62xx(ide_hwif_t *, unsigned long);
#define PCI_AEC62XX &pci_init_aec62xx
#define ATA66_AEC62XX &ata66_aec62xx
#define INIT_AEC62XX &ide_init_aec62xx
#define DMA_AEC62XX &ide_dmacapable_aec62xx
#else
#define PCI_AEC62XX NULL
#define ATA66_AEC62XX NULL
#define INIT_AEC62XX IDE_NO_DRIVER
#define DMA_AEC62XX NULL
# define pci_init_aec62xx NULL
# define ata66_aec62xx NULL
# define ide_init_aec62xx IDE_NO_DRIVER
# define ide_dmacapable_aec62xx NULL
#endif
#ifdef CONFIG_BLK_DEV_ALI15X3
extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
extern unsigned int pci_init_ali15x3(struct pci_dev *);
extern unsigned int ata66_ali15x3(ide_hwif_t *);
extern void ide_init_ali15x3(ide_hwif_t *);
extern void ide_dmacapable_ali15x3(ide_hwif_t *, unsigned long);
#define PCI_ALI15X3 &pci_init_ali15x3
#define ATA66_ALI15X3 &ata66_ali15x3
#define INIT_ALI15X3 &ide_init_ali15x3
#define DMA_ALI15X3 &ide_dmacapable_ali15x3
#else
#define PCI_ALI15X3 NULL
#define ATA66_ALI15X3 NULL
#define INIT_ALI15X3 IDE_NO_DRIVER
#define DMA_ALI15X3 NULL
# define pci_init_ali15x3 NULL
# define ata66_ali15x3 NULL
# define ide_init_ali15x3 IDE_NO_DRIVER
# define ide_dmacapable_ali15x3 NULL
#endif
#ifdef CONFIG_BLK_DEV_AMD74XX
extern unsigned int pci_init_amd74xx(struct pci_dev *, const char *);
extern unsigned int pci_init_amd74xx(struct pci_dev *);
extern unsigned int ata66_amd74xx(ide_hwif_t *);
extern void ide_init_amd74xx(ide_hwif_t *);
extern void ide_dmacapable_amd74xx(ide_hwif_t *, unsigned long);
#define PCI_AMD74XX &pci_init_amd74xx
#define ATA66_AMD74XX &ata66_amd74xx
#define INIT_AMD74XX &ide_init_amd74xx
#define DMA_AMD74XX &ide_dmacapable_amd74xx
#else
#define PCI_AMD74XX NULL
#define ATA66_AMD74XX NULL
#define INIT_AMD74XX IDE_NO_DRIVER
#define DMA_AMD74XX NULL
# define pci_init_amd74xx NULL
# define ata66_amd74xx NULL
# define ide_init_amd74xx IDE_NO_DRIVER
# define ide_dmacapable_amd74xx NULL
#endif
#ifdef CONFIG_BLK_DEV_CMD64X
extern unsigned int pci_init_cmd64x(struct pci_dev *, const char *);
extern unsigned int pci_init_cmd64x(struct pci_dev *);
extern unsigned int ata66_cmd64x(ide_hwif_t *);
extern void ide_init_cmd64x(ide_hwif_t *);
extern void ide_dmacapable_cmd64x(ide_hwif_t *, unsigned long);
#define PCI_CMD64X &pci_init_cmd64x
#define ATA66_CMD64X &ata66_cmd64x
#define INIT_CMD64X &ide_init_cmd64x
#else
#define PCI_CMD64X NULL
#define ATA66_CMD64X NULL
#ifdef __sparc_v9__
#define INIT_CMD64X IDE_IGNORE
#else
#define INIT_CMD64X IDE_NO_DRIVER
#endif
# define pci_init_cmd64x NULL
# define ata66_cmd64x NULL
# ifdef __sparc_v9__
# define ide_init_cmd64x IDE_IGNORE
# else
# define ide_init_cmd64x IDE_NO_DRIVER
# endif
#endif
#ifdef CONFIG_BLK_DEV_CY82C693
extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *);
extern unsigned int pci_init_cy82c693(struct pci_dev *);
extern void ide_init_cy82c693(ide_hwif_t *);
#define PCI_CY82C693 &pci_init_cy82c693
#define INIT_CY82C693 &ide_init_cy82c693
#else
#define PCI_CY82C693 NULL
#define INIT_CY82C693 IDE_NO_DRIVER
# define pci_init_cy82c693 NULL
# define ide_init_cy82c693 IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_CS5530
extern unsigned int pci_init_cs5530(struct pci_dev *, const char *);
extern unsigned int pci_init_cs5530(struct pci_dev *);
extern void ide_init_cs5530(ide_hwif_t *);
#define PCI_CS5530 &pci_init_cs5530
#define INIT_CS5530 &ide_init_cs5530
#else
#define PCI_CS5530 NULL
#define INIT_CS5530 IDE_NO_DRIVER
# define pci_init_cs5530 NULL
# define ide_init_cs5530 IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_HPT34X
extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
extern unsigned int pci_init_hpt34x(struct pci_dev *);
extern void ide_init_hpt34x(ide_hwif_t *);
#define PCI_HPT34X &pci_init_hpt34x
#define INIT_HPT34X &ide_init_hpt34x
#else
#define PCI_HPT34X NULL
#define INIT_HPT34X IDE_IGNORE
# define pci_init_hpt34x NULL
# define ide_init_hpt34x IDE_IGNORE
#endif
#ifdef CONFIG_BLK_DEV_HPT366
extern byte hpt363_shared_irq;
extern byte hpt363_shared_pin;
extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
extern unsigned int pci_init_hpt366(struct pci_dev *);
extern unsigned int ata66_hpt366(ide_hwif_t *);
extern void ide_init_hpt366(ide_hwif_t *);
extern void ide_dmacapable_hpt366(ide_hwif_t *, unsigned long);
#define PCI_HPT366 &pci_init_hpt366
#define ATA66_HPT366 &ata66_hpt366
#define INIT_HPT366 &ide_init_hpt366
#define DMA_HPT366 &ide_dmacapable_hpt366
#else
static byte hpt363_shared_irq;
static byte hpt363_shared_pin;
#define PCI_HPT366 NULL
#define ATA66_HPT366 NULL
#define INIT_HPT366 IDE_NO_DRIVER
#define DMA_HPT366 NULL
# define pci_init_hpt366 NULL
# define ata66_hpt366 NULL
# define ide_init_hpt366 IDE_NO_DRIVER
# define ide_dmacapable_hpt366 NULL
#endif
#ifdef CONFIG_BLK_DEV_NS87415
extern void ide_init_ns87415(ide_hwif_t *);
#define INIT_NS87415 &ide_init_ns87415
#else
#define INIT_NS87415 IDE_IGNORE
# define ide_init_ns87415 IDE_IGNORE
#endif
#ifdef CONFIG_BLK_DEV_OPTI621
extern void ide_init_opti621(ide_hwif_t *);
#define INIT_OPTI621 &ide_init_opti621
#else
#define INIT_OPTI621 IDE_NO_DRIVER
# define ide_init_opti621 IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_PDC_ADMA
extern unsigned int pci_init_pdcadma(struct pci_dev *, const char *);
extern unsigned int pci_init_pdcadma(struct pci_dev *);
extern unsigned int ata66_pdcadma(ide_hwif_t *);
extern void ide_init_pdcadma(ide_hwif_t *);
extern void ide_dmacapable_pdcadma(ide_hwif_t *, unsigned long);
#define PCI_PDCADMA &pci_init_pdcadma
#define ATA66_PDCADMA &ata66_pdcadma
#define INIT_PDCADMA &ide_init_pdcadma
#define DMA_PDCADMA &ide_dmacapable_pdcadma
#else
#define PCI_PDCADMA IDE_IGNORE
#define ATA66_PDCADMA IDE_IGNORE
#define INIT_PDCADMA IDE_IGNORE
#define DMA_PDCADMA IDE_IGNORE
# define pci_init_pdcadma NULL
# define ata66_pdcadma NULL
# define ide_init_pdcadma IDE_IGNORE
# define ide_dmacapable_pdcadma NULL
#endif
#ifdef CONFIG_BLK_DEV_PDC202XX
extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
extern unsigned int pci_init_pdc202xx(struct pci_dev *);
extern unsigned int ata66_pdc202xx(ide_hwif_t *);
extern void ide_init_pdc202xx(ide_hwif_t *);
#define PCI_PDC202XX &pci_init_pdc202xx
#define ATA66_PDC202XX &ata66_pdc202xx
#define INIT_PDC202XX &ide_init_pdc202xx
#else
#define PCI_PDC202XX IDE_IGNORE
#define ATA66_PDC202XX IDE_IGNORE
#define INIT_PDC202XX IDE_IGNORE
# define pci_init_pdc202xx NULL
# define ata66_pdc202xx NULL
# define ide_init_pdc202xx IDE_IGNORE
#endif
#ifdef CONFIG_BLK_DEV_PIIX
extern unsigned int pci_init_piix(struct pci_dev *, const char *);
extern unsigned int pci_init_piix(struct pci_dev *);
extern unsigned int ata66_piix(ide_hwif_t *);
extern void ide_init_piix(ide_hwif_t *);
#define PCI_PIIX &pci_init_piix
#define ATA66_PIIX &ata66_piix
#define INIT_PIIX &ide_init_piix
#else
#define PCI_PIIX NULL
#define ATA66_PIIX NULL
#define INIT_PIIX IDE_NO_DRIVER
# define pci_init_piix NULL
# define ata66_piix NULL
# define ide_init_piix IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_IT8172
extern unsigned int pci_init_it8172(struct pci_dev *, const char *);
extern unsigned int pci_init_it8172(struct pci_dev *);
/* We assume that this function has not been added to the global setup lists
* due to a patch merge error.
*/
extern unsigned int ata66_it8172(ide_hwif_t *);
extern void ide_init_it8172(ide_hwif_t *);
#define PCI_IT8172 &pci_init_it8172
#define INIT_IT8172 &ide_init_it8172
#else
#define PCI_IT8172 NULL
#define ATA66_IT8172 NULL
#define INIT_IT8172 IDE_NO_DRIVER
# define pci_init_it8172 NULL
# define ata66_it8172 NULL
# define ide_init_it8172 IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_RZ1000
extern void ide_init_rz1000(ide_hwif_t *);
#define INIT_RZ1000 &ide_init_rz1000
#else
#define INIT_RZ1000 IDE_IGNORE
# define ide_init_rz1000 IDE_IGNORE
#endif
#define INIT_SAMURAI NULL
#ifdef CONFIG_BLK_DEV_SVWKS
extern unsigned int pci_init_svwks(struct pci_dev *, const char *);
extern unsigned int pci_init_svwks(struct pci_dev *);
extern unsigned int ata66_svwks(ide_hwif_t *);
extern void ide_init_svwks(ide_hwif_t *);
#define PCI_SVWKS &pci_init_svwks
#define ATA66_SVWKS &ata66_svwks
#define INIT_SVWKS &ide_init_svwks
#else
#define PCI_SVWKS NULL
#define ATA66_SVWKS NULL
#define INIT_SVWKS IDE_NO_DRIVER
# define pci_init_svwks NULL
# define ata66_svwks NULL
# define ide_init_svwks IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_SIS5513
extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
extern unsigned int pci_init_sis5513(struct pci_dev *);
extern unsigned int ata66_sis5513(ide_hwif_t *);
extern void ide_init_sis5513(ide_hwif_t *);
#define PCI_SIS5513 &pci_init_sis5513
#define ATA66_SIS5513 &ata66_sis5513
#define INIT_SIS5513 &ide_init_sis5513
#else
#define PCI_SIS5513 NULL
#define ATA66_SIS5513 NULL
#define INIT_SIS5513 IDE_NO_DRIVER
# define pci_init_sis5513 NULL
# define ata66_sis5513 NULL
# define ide_init_sis5513 IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_SLC90E66
extern unsigned int pci_init_slc90e66(struct pci_dev *, const char *);
extern unsigned int pci_init_slc90e66(struct pci_dev *);
extern unsigned int ata66_slc90e66(ide_hwif_t *);
extern void ide_init_slc90e66(ide_hwif_t *);
#define PCI_SLC90E66 &pci_init_slc90e66
#define ATA66_SLC90E66 &ata66_slc90e66
#define INIT_SLC90E66 &ide_init_slc90e66
#else
#define PCI_SLC90E66 NULL
#define ATA66_SLC90E66 NULL
#define INIT_SLC90E66 IDE_NO_DRIVER
# define pci_init_slc90e66 NULL
# define ata66_slc90e66 NULL
# define ide_init_slc90e66 IDE_NO_DRIVER
#endif
#ifdef CONFIG_BLK_DEV_SL82C105
extern unsigned int pci_init_sl82c105(struct pci_dev *, const char *);
extern unsigned int pci_init_sl82c105(struct pci_dev *);
extern void dma_init_sl82c105(ide_hwif_t *, unsigned long);
extern void ide_init_sl82c105(ide_hwif_t *);
#define PCI_W82C105 &pci_init_sl82c105
#define DMA_W82C105 &dma_init_sl82c105
#define INIT_W82C105 &ide_init_sl82c105
#else
#define PCI_W82C105 NULL
#define DMA_W82C105 NULL
#define INIT_W82C105 IDE_IGNORE
# define pci_init_sl82c105 NULL
# define dma_init_sl82c105 NULL
# define ide_init_sl82c105 IDE_IGNORE
#endif
#ifdef CONFIG_BLK_DEV_TRM290
extern void ide_init_trm290(ide_hwif_t *);
#define INIT_TRM290 &ide_init_trm290
#else
#define INIT_TRM290 IDE_IGNORE
# define ide_init_trm290 IDE_IGNORE
#endif
#ifdef CONFIG_BLK_DEV_VIA82CXXX
extern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *);
extern unsigned int pci_init_via82cxxx(struct pci_dev *);
extern unsigned int ata66_via82cxxx(ide_hwif_t *);
extern void ide_init_via82cxxx(ide_hwif_t *);
extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long);
#define PCI_VIA82CXXX &pci_init_via82cxxx
#define ATA66_VIA82CXXX &ata66_via82cxxx
#define INIT_VIA82CXXX &ide_init_via82cxxx
#define DMA_VIA82CXXX &ide_dmacapable_via82cxxx
#else
#define PCI_VIA82CXXX NULL
#define ATA66_VIA82CXXX NULL
#define INIT_VIA82CXXX IDE_NO_DRIVER
#define DMA_VIA82CXXX NULL
# define pci_init_via82cxxx NULL
# define ata66_via82cxxx NULL
# define ide_init_via82cxxx IDE_NO_DRIVER
# define ide_dmacapable_via82cxxx NULL
#endif
typedef struct ide_pci_enablebit_s {
......@@ -374,9 +261,9 @@ typedef struct ide_pci_enablebit_s {
} ide_pci_enablebit_t;
typedef struct ide_pci_device_s {
ide_pci_devid_t devid;
char *name;
unsigned int (*init_chipset)(struct pci_dev *dev, const char *name);
unsigned short vendor;
unsigned short device;
unsigned int (*init_chipset)(struct pci_dev *dev);
unsigned int (*ata66_check)(ide_hwif_t *hwif);
void (*init_hwif)(ide_hwif_t *hwif);
void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
......@@ -385,90 +272,92 @@ typedef struct ide_pci_device_s {
unsigned int extra;
} ide_pci_device_t;
static ide_pci_device_t ide_pci_chipsets[] __initdata = {
{DEVID_PIIXa, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIXb, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_MPIIX, "MPIIX", NULL, NULL, INIT_PIIX, NULL, {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX3, "PIIX3", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX4, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_ICH0, "ICH0", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX4E2, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_ICH, "ICH", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX4U2, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_PIIX4NX, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_ICH2, "ICH2", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_ICH2M, "ICH2-M", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_ICH3, "ICH3", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_MR_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
{DEVID_VP_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
static ide_pci_device_t pci_chipsets[] __initdata = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, NULL, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, NULL, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, NULL, NULL, ide_init_piix, NULL, {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, pci_init_piix, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, pci_init_piix, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, pci_init_piix, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, pci_init_piix, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, pci_init_piix, ata66_piix, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, pci_init_piix, ata66_piix, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_init_piix, NULL, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, pci_init_piix, ata66_piix, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, pci_init_piix, ata66_piix, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_init_piix, ata66_piix, ide_init_piix, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, pci_init_via82cxxx, ata66_via82cxxx, ide_init_via82cxxx, ide_dmacapable_via82cxxx, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, pci_init_via82cxxx, ata66_via82cxxx, ide_init_via82cxxx, ide_dmacapable_via82cxxx, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
#ifdef CONFIG_PDC202XX_FORCE
{DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 16 },
{DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 },
{DEVID_PDC20265,"PDC20265", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 48 },
{DEVID_PDC20267,"PDC20267", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, pci_init_pdc202xx, NULL, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 16 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 48 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 },
#else /* !CONFIG_PDC202XX_FORCE */
{DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16 },
{DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
{DEVID_PDC20265,"PDC20265", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
{DEVID_PDC20267,"PDC20267", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, pci_init_pdc202xx, NULL, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
#endif
{DEVID_PDC20268,"PDC20268", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
/* Promise used a different PCI ident for the raid card apparently to try and
prevent Linux detecting it and using our own raid code. We want to detect
it for the ataraid drivers, so we have to list both here.. */
{DEVID_PDC20268R,"PDC20270", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{DEVID_PDC20269,"PDC20269", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{DEVID_PDC20275,"PDC20275", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{DEVID_RZ1000, "RZ1000", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_RZ1001, "RZ1001", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_SAMURAI, "SAMURAI", NULL, NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CMD640, "CMD640", NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_NS87410, "NS87410", NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0 },
{DEVID_SIS5513, "SIS5513", PCI_SIS5513, ATA66_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0 },
{DEVID_CMD643, "CMD643", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CMD646, "CMD646", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_CMD648, "CMD648", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CMD649, "CMD649", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CMD680, "CMD680", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_HT6565, "HT6565", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_OPTI621, "OPTI621", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
{DEVID_OPTI621X,"OPTI621X", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
{DEVID_TRM290, "TRM290", NULL, NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_NS87415, "NS87415", NULL, NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_AEC6210, "AEC6210", PCI_AEC62XX, NULL, INIT_AEC62XX, DMA_AEC62XX, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
{DEVID_AEC6260, "AEC6260", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0 },
{DEVID_AEC6260R,"AEC6260R", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
{DEVID_W82C105, "W82C105", PCI_W82C105, NULL, INIT_W82C105, DMA_W82C105, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0 },
{DEVID_UM8673F, "UM8673F", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_HPT34X, "HPT34X", PCI_HPT34X, NULL, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16 },
{DEVID_HPT366, "HPT366", PCI_HPT366, ATA66_HPT366, INIT_HPT366, DMA_HPT366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240 },
{DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, ATA66_ALI15X3, INIT_ALI15X3, DMA_ALI15X3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CY82C693,"CY82C693", PCI_CY82C693, NULL, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CS5530, "CS5530", PCI_CS5530, NULL, INIT_CS5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_AMD7401, "AMD7401", NULL, NULL, NULL, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{DEVID_AMD7409, "AMD7409", PCI_AMD74XX, ATA66_AMD74XX, INIT_AMD74XX, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{DEVID_AMD7411, "AMD7411", PCI_AMD74XX, ATA66_AMD74XX, INIT_AMD74XX, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{DEVID_AMD7441, "AMD7441", PCI_AMD74XX, ATA66_AMD74XX, INIT_AMD74XX, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{DEVID_PDCADMA, "PDCADMA", PCI_PDCADMA, ATA66_PDCADMA, INIT_PDCADMA, DMA_PDCADMA, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{DEVID_SLC90E66,"SLC90E66", PCI_SLC90E66, ATA66_SLC90E66, INIT_SLC90E66, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{DEVID_OSB4, "ServerWorks OSB4", PCI_SVWKS, ATA66_SVWKS, INIT_SVWKS, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_CSB5, "ServerWorks CSB5", PCI_SVWKS, ATA66_SVWKS, INIT_SVWKS, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{DEVID_ITE8172G,"IT8172G", PCI_IT8172, NULL, INIT_IT8172, NULL, {{0x00,0x00,0x00}, {0x40,0x00,0x01}}, ON_BOARD, 0 },
{IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }};
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268R, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, pci_init_pdc202xx, ata66_pdc202xx, ide_init_pdc202xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000, NULL, NULL, ide_init_rz1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001, NULL, NULL, ide_init_rz1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640, NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410, NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_init_sis5513, ata66_sis5513, ide_init_sis5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, pci_init_cmd64x, NULL, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, pci_init_cmd64x, NULL, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, pci_init_cmd64x, ata66_cmd64x, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, pci_init_cmd64x, ata66_cmd64x, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_680, pci_init_cmd64x, ata66_cmd64x, ide_init_cmd64x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621, NULL, NULL, ide_init_opti621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825, NULL, NULL, ide_init_opti621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, NULL, NULL, ide_init_trm290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, NULL, NULL, ide_init_ns87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, pci_init_aec62xx, NULL, ide_init_aec62xx, ide_dmacapable_aec62xx, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, pci_init_aec62xx, ata66_aec62xx, ide_init_aec62xx, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0 },
{PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, pci_init_aec62xx, ata66_aec62xx, ide_init_aec62xx, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, pci_init_sl82c105, NULL, ide_init_sl82c105, dma_init_sl82c105, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, pci_init_hpt34x, NULL, ide_init_hpt34x, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16 },
{PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, pci_init_hpt366, ata66_hpt366, ide_init_hpt366, ide_dmacapable_hpt366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240 },
{PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, pci_init_ali15x3, ata66_ali15x3, ide_init_ali15x3, ide_dmacapable_ali15x3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_init_cy82c693, NULL, ide_init_cy82c693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, pci_init_cs5530, NULL, ide_init_cs5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, NULL, NULL, NULL, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7441, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_PDC, PCI_DEVICE_ID_PDC_1841, pci_init_pdcadma, ata66_pdcadma, ide_init_pdcadma, ide_dmacapable_pdcadma, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
{PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, pci_init_slc90e66, ata66_slc90e66, ide_init_slc90e66, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, pci_init_svwks, ata66_svwks, ide_init_svwks, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, pci_init_svwks, ata66_svwks, ide_init_svwks, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
{PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, pci_init_it8172, NULL, ide_init_it8172, NULL, {{0x00,0x00,0x00}, {0x40,0x00,0x01}}, ON_BOARD, 0 },
{0, 0, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }};
/*
* This allows offboard ide-pci cards the enable a BIOS, verify interrupt
* settings of split-mirror pci-config space, place chipset into init-mode,
* and/or preserve an interrupt if the card is not native ide support.
*/
static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
static unsigned int __init trust_pci_irq(struct pci_dev *dev)
{
if (dev->vendor == PCI_VENDOR_ID_TTI && dev->device == PCI_DEVICE_ID_TTI_HPT366)
return dev->irq;
else if (dev->vendor == PCI_VENDOR_ID_PROMISE) {
switch(dev->device) {
case PCI_DEVICE_ID_TTI_HPT366:
case PCI_DEVICE_ID_PROMISE_20246:
case PCI_DEVICE_ID_PROMISE_20262:
case PCI_DEVICE_ID_PROMISE_20265:
......@@ -477,12 +366,15 @@ static unsigned int __init ide_special_settings (struct pci_dev *dev, const char
case PCI_DEVICE_ID_PROMISE_20268R:
case PCI_DEVICE_ID_PROMISE_20269:
case PCI_DEVICE_ID_PROMISE_20275:
return dev->irq;
}
} else if (dev->vendor == PCI_VENDOR_ID_ARTOP) {
switch(dev->device) {
case PCI_DEVICE_ID_ARTOP_ATP850UF:
case PCI_DEVICE_ID_ARTOP_ATP860:
case PCI_DEVICE_ID_ARTOP_ATP860R:
return dev->irq;
default:
break;
}
}
return 0;
}
......@@ -491,7 +383,7 @@ static unsigned int __init ide_special_settings (struct pci_dev *dev, const char
* Match a PCI IDE port against an entry in ide_hwifs[],
* based on io_base port if possible.
*/
static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
static ide_hwif_t __init *lookup_hwif (unsigned long io_base, byte bootable, const char *name)
{
int h;
ide_hwif_t *hwif;
......@@ -553,7 +445,7 @@ static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable,
return NULL;
}
static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
static int __init setup_pci_baseregs (struct pci_dev *dev, const char *name)
{
byte reg, progif = 0;
......@@ -566,7 +458,7 @@ static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
return 1;
}
printk("%s: placing both ports into native PCI mode\n", name);
(void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
return 1;
......@@ -588,23 +480,211 @@ static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
}
/*
* ide_setup_pci_device() looks at the primary/secondary interfaces
* on a PCI IDE device and, if they are enabled, prepares the IDE driver
* for use with them. This generic code works for most PCI chipsets.
* Setup a particular port on an ATA host controller.
*
* One thing that is not standardized is the location of the
* primary/secondary interface "enable/disable" bits. For chipsets that
* we "know" about, this information is in the ide_pci_device_t struct;
* for all other chipsets, we just assume both interfaces are enabled.
* This get's called once for the master and for the slave interface.
*/
static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
static int __init setup_host_channel(struct pci_dev *dev,
ide_pci_device_t *d,
int port,
u8 class_rev,
int pciirq, ide_hwif_t **mate,
int autodma,
unsigned short *pcicmd)
{
unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
unsigned short pcicmd = 0, tried_config = 0;
byte tmp = 0;
ide_hwif_t *hwif, *mate = NULL;
unsigned long base = 0;
unsigned long ctl = 0;
ide_pci_enablebit_t *e = &(d->enablebits[port]);
ide_hwif_t *hwif;
u8 tmp;
if (port == 1) {
/* If this is a Promise FakeRaid controller, the 2nd controller
* will be marked as disabled while it is actually there and
* enabled by the bios for raid purposes. Skip the normal "is
* it enabled" test for those.
*/
if ((d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20265) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20262))
goto controller_ok;
}
/* Test whatever the port is enabled.
*/
if (e->reg) {
if (pci_read_config_byte(dev, e->reg, &tmp))
return 0; /* error! */
if ((tmp & e->mask) != e->val)
return 0;
}
if (port == 1) {
/* Nothing to be done for the second port. */
if ((d->vendor == PCI_VENDOR_ID_TTI && d->device == PCI_DEVICE_ID_TTI_HPT366)
&& (class_rev < 0x03))
return 0;
}
controller_ok:
if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
ctl = dev->resource[(2 * port) + 1].start;
base = dev->resource[2 * port].start;
if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) || !(base & PCI_BASE_ADDRESS_IO_MASK)) {
printk(KERN_WARNING "%s: error: IO reported as MEM by BIOS!\n", dev->name);
/* try it with the default values */
ctl = 0;
base = 0;
}
}
if (ctl && !base) {
printk(KERN_WARNING "%s: error: missing MEM base info from BIOS!\n", dev->name);
/* we will still try to get along with the default */
}
if (base && !ctl) {
printk(KERN_WARNING "%s: error: missing IO base info from BIOS!\n", dev->name);
/* we will still try to get along with the default */
}
/* Fill in the default values: */
if (!ctl)
ctl = port ? 0x374 : 0x3f4;
if (!base)
base = port ? 0x170 : 0x1f0;
if ((hwif = lookup_hwif(base, d->bootable, dev->name)) == NULL)
return -ENOMEM; /* no room in ide_hwifs[] */
if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
}
hwif->chipset = ide_pci;
hwif->pci_dev = dev;
hwif->channel = port;
if (!hwif->irq)
hwif->irq = pciirq;
if (*mate) {
hwif->mate = *mate;
(*mate)->mate = hwif;
if (d->vendor == PCI_VENDOR_ID_ARTOP && d->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
hwif->serialized = 1;
(*mate)->serialized = 1;
}
}
if ((d->vendor == PCI_VENDOR_ID_UMC && d->device == PCI_DEVICE_ID_UMC_UM8886A) ||
(d->vendor == PCI_VENDOR_ID_UMC && d->device == PCI_DEVICE_ID_UMC_UM8886BF) ||
(d->vendor == PCI_VENDOR_ID_UMC && d->device == PCI_DEVICE_ID_UMC_UM8673F)) {
/* Fixed IRQ wiring */
hwif->irq = hwif->channel ? 15 : 14;
goto no_dma;
}
if ((d->vendor == PCI_VENDOR_ID_INTEL && d->device == PCI_DEVICE_ID_INTEL_82371MX) ||
(d->vendor == PCI_VENDOR_ID_PDC && d->device == PCI_DEVICE_ID_PDC_1841))
goto no_dma;
/* Check whatever this interface is UDMA4 mode capable. */
if (hwif->udma_four) {
printk("%s: warning: ATA-66/100 forced bit set!\n", dev->name);
} else {
if (d->ata66_check)
hwif->udma_four = d->ata66_check(hwif);
}
#ifdef CONFIG_BLK_DEV_IDEDMA
if ((d->vendor == PCI_VENDOR_ID_SI && d->device == PCI_DEVICE_ID_SI_5513) ||
(d->vendor == PCI_VENDOR_ID_ARTOP && d->device == PCI_DEVICE_ID_ARTOP_ATP860) ||
(d->vendor == PCI_VENDOR_ID_INTEL && d->device == PCI_DEVICE_ID_INTEL_82451NX) ||
(d->vendor == PCI_VENDOR_ID_TTI && d->device == PCI_DEVICE_ID_TTI_HPT343) ||
(d->vendor == PCI_VENDOR_ID_VIA && d->device == PCI_DEVICE_ID_VIA_82C561) ||
(d->vendor == PCI_VENDOR_ID_VIA && d->device == PCI_DEVICE_ID_VIA_82C576_1) ||
(d->vendor == PCI_VENDOR_ID_VIA && d->device == PCI_DEVICE_ID_VIA_82C586_1))
autodma = 0;
if (autodma)
hwif->autodma = 1;
if ((d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20246) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20262) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20265) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20267) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20268) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20268R) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20269) ||
(d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20275) ||
(d->vendor == PCI_VENDOR_ID_ARTOP && d->device == PCI_DEVICE_ID_ARTOP_ATP850UF) ||
(d->vendor == PCI_VENDOR_ID_ARTOP && d->device == PCI_DEVICE_ID_ARTOP_ATP860) ||
(d->vendor == PCI_VENDOR_ID_ARTOP && d->device == PCI_DEVICE_ID_ARTOP_ATP860R) ||
(d->vendor == PCI_VENDOR_ID_TTI && d->device == PCI_DEVICE_ID_TTI_HPT343) ||
(d->vendor == PCI_VENDOR_ID_TTI && d->device == PCI_DEVICE_ID_TTI_HPT366) ||
(d->vendor == PCI_VENDOR_ID_CYRIX && d->device == PCI_DEVICE_ID_CYRIX_5530_IDE) ||
(d->vendor == PCI_VENDOR_ID_CONTAQ && d->device == PCI_DEVICE_ID_CONTAQ_82C693) ||
(d->vendor == PCI_VENDOR_ID_CMD && d->device == PCI_DEVICE_ID_CMD_646) ||
(d->vendor == PCI_VENDOR_ID_CMD && d->device == PCI_DEVICE_ID_CMD_648) ||
(d->vendor == PCI_VENDOR_ID_CMD && d->device == PCI_DEVICE_ID_CMD_649) ||
(d->vendor == PCI_VENDOR_ID_CMD && d->device == PCI_DEVICE_ID_CMD_680) ||
(d->vendor == PCI_VENDOR_ID_SERVERWORKS && d->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) ||
((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
unsigned long dma_base;
dma_base = ide_get_or_set_dma_base(hwif, (!*mate && d->extra) ? d->extra : 0, dev->name);
if (dma_base && !(*pcicmd & PCI_COMMAND_MASTER)) {
/*
* Set up BM-DMA capability (PnP BIOS should have done this already)
*/
if (!(d->vendor == PCI_VENDOR_ID_CYRIX && d->device == PCI_DEVICE_ID_CYRIX_5530_IDE))
hwif->autodma = 0; /* default DMA off if we had to configure it here */
pci_write_config_word(dev, PCI_COMMAND, *pcicmd | PCI_COMMAND_MASTER);
if (pci_read_config_word(dev, PCI_COMMAND, pcicmd) || !(*pcicmd & PCI_COMMAND_MASTER)) {
printk("%s: %s error updating PCICMD\n", hwif->name, dev->name);
dma_base = 0;
}
}
if (dma_base) {
if (d->dma_init)
d->dma_init(hwif, dma_base);
else /* FIXME: use a generic device descriptor instead */
ide_setup_dma(hwif, dma_base, 8);
} else {
printk("%s: %s Bus-Master DMA was disabled by BIOS\n", hwif->name, dev->name);
}
}
#endif
no_dma:
if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
d->init_hwif(hwif);
*mate = hwif;
/* we are done */
return 0;
}
/*
* Looks at the primary/secondary chanells on a PCI IDE device and, if they
* are enabled, prepares the IDE driver for use with them. This generic code
* works for most PCI chipsets.
*
* One thing that is not standardized is the location of the primary/secondary
* interface "enable/disable" bits. For chipsets that we "know" about, this
* information is in the ide_pci_device_t struct; for all other chipsets, we
* just assume both interfaces are enabled.
*/
static void __init setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d)
{
int autodma = 0;
int pciirq = 0;
unsigned short pcicmd = 0;
unsigned short tried_config = 0;
ide_hwif_t *mate = NULL;
unsigned int class_rev;
static int secondpdc = 0;
#ifdef CONFIG_IDEDMA_AUTO
if (!noautodma)
......@@ -612,18 +692,18 @@ static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *
#endif
if (d->init_hwif == IDE_NO_DRIVER) {
printk(KERN_WARNING "%s: detected chipset, but driver not compiled in!\n", d->name);
printk(KERN_WARNING "%s: detected chipset, but driver not compiled in!\n", dev->name);
d->init_hwif = NULL;
}
if (pci_enable_device(dev)) {
printk(KERN_WARNING "%s: (ide_setup_pci_device:) Could not enable device.\n", d->name);
printk(KERN_WARNING "%s: Could not enable PCI device.\n", dev->name);
return;
}
check_if_enabled:
if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
printk("%s: error accessing PCI regs\n", d->name);
printk("%s: error accessing PCI regs\n", dev->name);
return;
}
if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
......@@ -635,42 +715,38 @@ static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *
* but we'll eventually ignore it again if no drives respond.
*/
if (tried_config++
|| ide_setup_pci_baseregs(dev, d->name)
|| setup_pci_baseregs(dev, dev->name)
|| pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
printk("%s: device disabled (BIOS)\n", d->name);
printk("%s: device disabled (BIOS)\n", dev->name);
return;
}
autodma = 0; /* default DMA off if we had to configure it here */
goto check_if_enabled;
}
if (tried_config)
printk("%s: device enabled (Linux)\n", d->name);
printk("%s: device enabled (Linux)\n", dev->name);
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
/* see comments in hpt34x.c on why..... */
char *chipset_names[] = {"HPT343", "HPT345"};
strcpy(d->name, chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]);
if (d->vendor == PCI_VENDOR_ID_TTI && PCI_DEVICE_ID_TTI_HPT343) {
/* see comments in hpt34x.c to see why... */
d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
}
printk("%s: chipset revision %d\n", d->name, class_rev);
printk("%s: chipset revision %d\n", dev->name, class_rev);
/*
* Can we trust the reported IRQ?
*/
pciirq = dev->irq;
if (dev->class >> 8 == PCI_CLASS_STORAGE_RAID)
{
if (dev->class >> 8 == PCI_CLASS_STORAGE_RAID) {
/* By rights we want to ignore these, but the Promise Fastrak
people have some strange ideas about proprietary so we have
to act otherwise on those. The supertrak however we need
to skip */
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265))
{
if (d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20265) {
printk(KERN_INFO "ide: Found promise 20265 in RAID mode.\n");
if(dev->bus->self && dev->bus->self->vendor == PCI_VENDOR_ID_INTEL &&
dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960)
......@@ -683,176 +759,39 @@ static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *
Suspect a fastrak and fall through */
}
if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
printk("%s: not 100%% native mode: will probe irqs later\n", dev->name);
/*
* This allows offboard ide-pci cards the enable a BIOS,
* verify interrupt settings of split-mirror pci-config
* space, place chipset into init-mode, and/or preserve
* an interrupt if the card is not native ide support.
*/
pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
if (d->init_chipset)
pciirq = d->init_chipset(dev);
else
pciirq = trust_pci_irq(dev);
} else if (tried_config) {
printk("%s: will probe irqs later\n", d->name);
printk("%s: will probe irqs later\n", dev->name);
pciirq = 0;
} else if (!pciirq) {
printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
printk("%s: bad irq (%d): will probe later\n", dev->name, pciirq);
pciirq = 0;
} else {
if (d->init_chipset)
(void) d->init_chipset(dev, d->name);
d->init_chipset(dev);
#ifdef __sparc__
printk("%s: 100%% native mode on irq %s\n",
d->name, __irq_itoa(pciirq));
dev->name, __irq_itoa(pciirq));
#else
printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
printk("%s: 100%% native mode on irq %d\n", dev->name, pciirq);
#endif
}
/*
* Set up the IDE ports
*/
for (port = 0; port <= 1; ++port) {
unsigned long base = 0, ctl = 0;
ide_pci_enablebit_t *e = &(d->enablebits[port]);
/*
* If this is a Promise FakeRaid controller, the 2nd controller will be marked as
* disabled while it is actually there and enabled by the bios for raid purposes.
* Skip the normal "is it enabled" test for those.
*/
if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265)) && (secondpdc++==1) && (port==1) )
goto controller_ok;
if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262)) && (secondpdc++==1) && (port==1) )
goto controller_ok;
if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
continue; /* port not enabled */
controller_ok:
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port) && (class_rev < 0x03))
return;
if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
ctl = dev->resource[(2*port)+1].start;
base = dev->resource[2*port].start;
if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) ||
!(base & PCI_BASE_ADDRESS_IO_MASK)) {
printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@linux-ide.org>.\n", d->name);
#if 0
/* FIXME! This really should check that it really gets the IO/MEM part right! */
continue;
#endif
}
}
if ((ctl && !base) || (base && !ctl)) {
printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
continue;
}
if (!ctl)
ctl = port ? 0x374 : 0x3f4; /* use default value */
if (!base)
base = port ? 0x170 : 0x1f0; /* use default value */
if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
continue; /* no room in ide_hwifs[] */
if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
}
hwif->chipset = ide_pci;
hwif->pci_dev = dev;
hwif->pci_devid = d->devid;
hwif->channel = port;
if (!hwif->irq)
hwif->irq = pciirq;
if (mate) {
hwif->mate = mate;
mate->mate = hwif;
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
hwif->serialized = 1;
mate->serialized = 1;
}
}
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8673F)) {
hwif->irq = hwif->channel ? 15 : 14;
goto bypass_umc_dma;
}
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_MPIIX))
goto bypass_piix_dma;
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDCADMA))
goto bypass_legacy_dma;
if (hwif->udma_four) {
printk("%s: ATA-66/100 forced bit set (WARNING)!!\n", d->name);
} else {
hwif->udma_four = (d->ata66_check) ? d->ata66_check(hwif) : 0;
}
#ifdef CONFIG_BLK_DEV_IDEDMA
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PIIX4NX) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_VIA_IDE) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_MR_IDE) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_VP_IDE))
autodma = 0;
if (autodma)
hwif->autodma = 1;
if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20267) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20268) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20268R) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20269) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20275) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260R) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD646) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD648) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD649) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD680) ||
IDE_PCI_DEVID_EQ(d->devid, DEVID_OSB4) ||
((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
/*
* Set up BM-DMA capability (PnP BIOS should have done this)
* Set up IDE chanells. First the primary, then the secondary.
*/
if (!IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530))
hwif->autodma = 0; /* default DMA off if we had to configure it here */
(void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
dma_base = 0;
}
}
if (dma_base) {
if (d->dma_init) {
d->dma_init(hwif, dma_base);
} else {
ide_setup_dma(hwif, dma_base, 8);
}
} else {
printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
}
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
bypass_legacy_dma:
bypass_piix_dma:
bypass_umc_dma:
if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
d->init_hwif(hwif);
mate = hwif;
at_least_one_hwif_enabled = 1;
}
if (!at_least_one_hwif_enabled)
printk("%s: neither IDE port enabled (BIOS)\n", d->name);
setup_host_channel(dev, d, 0, class_rev, pciirq, &mate, autodma, &pcicmd);
setup_host_channel(dev, d, 1, class_rev, pciirq, &mate, autodma, &pcicmd);
}
static void __init pdc20270_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
......@@ -884,13 +823,13 @@ static void __init pdc20270_device_order_fixup (struct pci_dev *dev, ide_pci_dev
}
}
printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
ide_setup_pci_device(dev, d);
printk("%s: IDE controller on PCI bus %02x dev %02x\n", dev->name, dev->bus->number, dev->devfn);
setup_pci_device(dev, d);
if (!dev2)
return;
d2 = d;
printk("%s: IDE controller on PCI bus %02x dev %02x\n", d2->name, dev2->bus->number, dev2->devfn);
ide_setup_pci_device(dev2, d2);
printk("%s: IDE controller on PCI bus %02x dev %02x\n", dev2->name, dev2->bus->number, dev2->devfn);
setup_pci_device(dev2, d2);
}
static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
......@@ -899,7 +838,6 @@ static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_devic
ide_pci_device_t *d2;
unsigned char pin1 = 0, pin2 = 0;
unsigned int class_rev;
char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
if (PCI_FUNC(dev->devfn) & 1)
return;
......@@ -907,12 +845,10 @@ static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_devic
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
strcpy(d->name, chipset_names[class_rev]);
switch(class_rev) {
case 4:
case 3: printk("%s: IDE controller on PCI slot %s\n", d->name, dev->slot_name);
ide_setup_pci_device(dev, d);
case 3: printk("%s: IDE controller on PCI slot %s\n", dev->name, dev->slot_name);
setup_pci_device(dev, d);
return;
default: break;
}
......@@ -929,7 +865,7 @@ static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_devic
hpt363_shared_irq = (dev->irq == dev2->irq) ? 1 : 0;
if (hpt363_shared_pin && hpt363_shared_irq) {
d->bootable = ON_BOARD;
printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", d->name, pin1, pin2);
printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", dev->name, pin1, pin2);
#if 0
/* I forgot why I did this once, but it fixed something. */
pci_write_config_byte(dev2, PCI_INTERRUPT_PIN, dev->irq);
......@@ -940,48 +876,55 @@ static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_devic
break;
}
}
printk("%s: IDE controller on PCI slot %s\n", d->name, dev->slot_name);
ide_setup_pci_device(dev, d);
printk("%s: IDE controller on PCI slot %s\n", dev->name, dev->slot_name);
setup_pci_device(dev, d);
if (!dev2)
return;
d2 = d;
printk("%s: IDE controller on PCI slot %s\n", d2->name, dev2->slot_name);
ide_setup_pci_device(dev2, d2);
printk("%s: IDE controller on PCI slot %s\n", dev2->name, dev2->slot_name);
setup_pci_device(dev2, d2);
}
/*
* ide_scan_pcibus() gets invoked at boot time from ide.c.
* It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
* This finds all PCI IDE controllers and calls appriopriate initialization
* functions for them.
*/
void __init ide_scan_pcidev (struct pci_dev *dev)
static void __init ide_scan_pcidev(struct pci_dev *dev)
{
ide_pci_devid_t devid;
unsigned short vendor;
unsigned short device;
ide_pci_device_t *d;
devid.vid = dev->vendor;
devid.did = dev->device;
for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
vendor = dev->vendor;
device = dev->device;
/* Look up the chipset information.
*/
d = pci_chipsets;
while (d->vendor && !(d->vendor == vendor && d->device == device))
++d;
if (d->init_hwif == IDE_IGNORE)
printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
printk("%s: has been ignored PCI bus scan\n", dev->name);
else if ((d->vendor == PCI_VENDOR_ID_OPTI && d->device == PCI_DEVICE_ID_OPTI_82C558) && !(PCI_FUNC(dev->devfn) & 1))
return;
else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
else if ((d->vendor == PCI_VENDOR_ID_CONTAQ && d->device == PCI_DEVICE_ID_CONTAQ_82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
return; /* CY82C693 is more than only a IDE controller */
else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_ITE8172G) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
else if ((d->vendor == PCI_VENDOR_ID_ITE && d->device == PCI_DEVICE_ID_ITE_IT8172G) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
return; /* IT8172G is also more than only an IDE controller */
else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
else if ((d->vendor == PCI_VENDOR_ID_UMC && d->device == PCI_DEVICE_ID_UMC_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
return; /* UM8886A/BF pair */
else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
else if ((d->vendor == PCI_VENDOR_ID_TTI && d->device == PCI_DEVICE_ID_TTI_HPT366))
hpt366_device_order_fixup(dev, d);
else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20268R))
else if (d->vendor == PCI_VENDOR_ID_PROMISE && d->device == PCI_DEVICE_ID_PROMISE_20268R)
pdc20270_device_order_fixup(dev, d);
else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
printk("%s: unknown IDE controller on PCI slot %s, VID=%04x, DID=%04x\n",
d->name, dev->slot_name, devid.vid, devid.did);
else if (!(d->vendor == 0 && d->device == 0) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
if (d->vendor == 0 && d->device == 0)
printk("%s: unknown IDE controller on PCI slot %s, vendor=%04x, device=%04x\n",
dev->name, dev->slot_name, vendor, device);
else
printk("%s: IDE controller on PCI slot %s\n", d->name, dev->slot_name);
ide_setup_pci_device(dev, d);
printk("%s: IDE controller on PCI slot %s\n", dev->name, dev->slot_name);
setup_pci_device(dev, d);
}
}
......
drivers/ide/ide-proc.c
View file @ c0bf9449
......@@ -127,242 +127,8 @@ extern byte via_proc;
int (*via_display_info)(char *, char **, off_t, int) = NULL;
#endif /* CONFIG_BLK_DEV_VIA82CXXX */
static int ide_getxdigit(char c)
{
int digit;
if (isdigit(c))
digit = c - '0';
else if (isxdigit(c))
digit = tolower(c) - 'a' + 10;
else
digit = -1;
return digit;
}
static int xx_xx_parse_error (const char *data, unsigned long len, const char *msg)
{
char errbuf[16];
int i;
if (len >= sizeof(errbuf))
len = sizeof(errbuf) - 1;
for (i = 0; i < len; ++i) {
char c = data[i];
if (!c || c == '\n')
c = '\0';
else if (iscntrl(c))
c = '?';
errbuf[i] = c;
}
errbuf[i] = '\0';
printk("proc_ide: error: %s: '%s'\n", msg, errbuf);
return -EINVAL;
}
static struct proc_dir_entry * proc_ide_root = NULL;
static int proc_ide_write_config
(struct file *file, const char *buffer, unsigned long count, void *data)
{
ide_hwif_t *hwif = data;
int for_real = 0;
unsigned long startn = 0, n, flags;
const char *start = NULL, *msg = NULL;
if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
return -EACCES;
/*
* Skip over leading whitespace
*/
while (count && isspace(*buffer)) {
--count;
++buffer;
}
/*
* Do one full pass to verify all parameters,
* then do another to actually write the regs.
*/
save_flags(flags); /* all CPUs */
do {
const char *p;
if (for_real) {
unsigned long timeout = jiffies + (3 * HZ);
ide_hwgroup_t *mygroup = (ide_hwgroup_t *)(hwif->hwgroup);
ide_hwgroup_t *mategroup = NULL;
if (hwif->mate && hwif->mate->hwgroup)
mategroup = (ide_hwgroup_t *)(hwif->mate->hwgroup);
cli(); /* all CPUs; ensure all writes are done together */
while (test_bit(IDE_BUSY, &mygroup->flags) || (mategroup && test_bit(IDE_BUSY, &mategroup->flags))) {
sti(); /* all CPUs */
if (0 < (signed long)(jiffies - timeout)) {
printk("/proc/ide/%s/config: channel(s) busy, cannot write\n", hwif->name);
restore_flags(flags); /* all CPUs */
return -EBUSY;
}
cli(); /* all CPUs */
}
}
p = buffer;
n = count;
while (n > 0) {
int d, digits;
unsigned int reg = 0, val = 0, is_pci;
start = p;
startn = n--;
switch (*p++) {
case 'R': is_pci = 0;
break;
case 'P': is_pci = 1;
#ifdef CONFIG_BLK_DEV_IDEPCI
if (hwif->pci_dev && !IDE_PCI_DEVID_EQ(hwif->pci_devid, IDE_PCI_DEVID_NULL))
break;
#endif /* CONFIG_BLK_DEV_IDEPCI */
msg = "not a PCI device";
goto parse_error;
default: msg = "expected 'R' or 'P'";
goto parse_error;
}
digits = 0;
while (n > 0 && (d = ide_getxdigit(*p)) >= 0) {
reg = (reg << 4) | d;
--n;
++p;
++digits;
}
if (!digits || (digits > 4) || (is_pci && reg > 0xff)) {
msg = "bad/missing register number";
goto parse_error;
}
if (n-- == 0 || *p++ != ':') {
msg = "missing ':'";
goto parse_error;
}
digits = 0;
while (n > 0 && (d = ide_getxdigit(*p)) >= 0) {
val = (val << 4) | d;
--n;
++p;
++digits;
}
if (digits != 2 && digits != 4 && digits != 8) {
msg = "bad data, 2/4/8 digits required";
goto parse_error;
}
if (n > 0 && !isspace(*p)) {
msg = "expected whitespace after data";
goto parse_error;
}
while (n > 0 && isspace(*p)) {
--n;
++p;
}
#ifdef CONFIG_BLK_DEV_IDEPCI
if (is_pci && (reg & ((digits >> 1) - 1))) {
msg = "misaligned access";
goto parse_error;
}
#endif /* CONFIG_BLK_DEV_IDEPCI */
if (for_real) {
#if 0
printk("proc_ide_write_config: type=%c, reg=0x%x, val=0x%x, digits=%d\n", is_pci ? "PCI" : "non-PCI", reg, val, digits);
#endif
if (is_pci) {
#ifdef CONFIG_BLK_DEV_IDEPCI
int rc = 0;
struct pci_dev *dev = hwif->pci_dev;
switch (digits) {
case 2: msg = "byte";
rc = pci_write_config_byte(dev, reg, val);
break;
case 4: msg = "word";
rc = pci_write_config_word(dev, reg, val);
break;
case 8: msg = "dword";
rc = pci_write_config_dword(dev, reg, val);
break;
}
if (rc) {
restore_flags(flags); /* all CPUs */
printk("proc_ide_write_config: error writing %s at bus %02x dev %02x reg 0x%x value 0x%x\n",
msg, dev->bus->number, dev->devfn, reg, val);
printk("proc_ide_write_config: error %d\n", rc);
return -EIO;
}
#endif /* CONFIG_BLK_DEV_IDEPCI */
} else { /* not pci */
#if !defined(__mc68000__) && !defined(CONFIG_APUS)
/*
* Geert Uytterhoeven
*
* unless you can explain me what it really does.
* On m68k, we don't have outw() and outl() yet,
* and I need a good reason to implement it.
*
* BTW, IMHO the main remaining portability problem with the IDE driver
* is that it mixes IO (ioport) and MMIO (iomem) access on different platforms.
*
* I think all accesses should be done using
*
* ide_in[bwl](ide_device_instance, offset)
* ide_out[bwl](ide_device_instance, value, offset)
*
* so the architecture specific code can #define ide_{in,out}[bwl] to the
* appropriate function.
*
*/
switch (digits) {
case 2: outb(val, reg);
break;
case 4: outw(val, reg);
break;
case 8: outl(val, reg);
break;
}
#endif /* !__mc68000__ && !CONFIG_APUS */
}
}
}
} while (!for_real++);
restore_flags(flags); /* all CPUs */
return count;
parse_error:
restore_flags(flags); /* all CPUs */
printk("parse error\n");
return xx_xx_parse_error(start, startn, msg);
}
static int proc_ide_read_config
(char *page, char **start, off_t off, int count, int *eof, void *data)
{
char *out = page;
int len;
#ifdef CONFIG_BLK_DEV_IDEPCI
ide_hwif_t *hwif = data;
struct pci_dev *dev = hwif->pci_dev;
if (!IDE_PCI_DEVID_EQ(hwif->pci_devid, IDE_PCI_DEVID_NULL) && dev && dev->bus) {
int reg = 0;
out += sprintf(out, "pci bus %02x device %02x vid %04x did %04x channel %d\n",
dev->bus->number, dev->devfn, hwif->pci_devid.vid, hwif->pci_devid.did, hwif->channel);
do {
byte val;
int rc = pci_read_config_byte(dev, reg, &val);
if (rc) {
printk("proc_ide_read_config: error %d reading bus %02x dev %02x reg 0x%02x\n",
rc, dev->bus->number, dev->devfn, reg);
out += sprintf(out, "??%c", (++reg & 0xf) ? ' ' : '\n');
} else
out += sprintf(out, "%02x%c", val, (++reg & 0xf) ? ' ' : '\n');
} while (reg < 0x100);
} else
#endif /* CONFIG_BLK_DEV_IDEPCI */
out += sprintf(out, "(none)\n");
len = out - page;
PROC_IDE_READ_RETURN(page,start,off,count,eof,len);
}
static int ide_getdigit(char c)
{
int digit;
......@@ -785,7 +551,6 @@ void destroy_proc_ide_drives(ide_hwif_t *hwif)
static ide_proc_entry_t hwif_entries[] = {
{ "channel", S_IFREG|S_IRUGO, proc_ide_read_channel, NULL },
{ "config", S_IFREG|S_IRUGO|S_IWUSR,proc_ide_read_config, proc_ide_write_config },
{ "mate", S_IFREG|S_IRUGO, proc_ide_read_mate, NULL },
{ "model", S_IFREG|S_IRUGO, proc_ide_read_imodel, NULL },
{ NULL, 0, NULL, NULL }
......
drivers/ide/ide-taskfile.c
View file @ c0bf9449
......@@ -42,6 +42,24 @@
#define DTF(x...)
#endif
/*
* for now, taskfile requests are special :/
*/
static inline char *ide_map_rq(struct request *rq, unsigned long *flags)
{
if (rq->bio)
return bio_kmap_irq(rq->bio, flags) + ide_rq_offset(rq);
else
return rq->buffer + task_rq_offset(rq);
}
static inline void ide_unmap_rq(struct request *rq, char *to,
unsigned long *flags)
{
if (rq->bio)
bio_kunmap_irq(to, flags);
}
inline u32 task_read_24 (ide_drive_t *drive)
{
return (IN_BYTE(IDE_HCYL_REG)<<16) |
......@@ -1137,7 +1155,7 @@ ide_startstop_t bio_mulout_intr (ide_drive_t *drive)
nsect = mcount;
mcount -= nsect;
buffer = ide_map_buffer(rq, &flags);
buffer = bio_kmap_irq(rq->bio, &flags) + ide_rq_offset(rq);
rq->sector += nsect;
rq->nr_sectors -= nsect;
rq->current_nr_sectors -= nsect;
......@@ -1161,7 +1179,7 @@ ide_startstop_t bio_mulout_intr (ide_drive_t *drive)
* re-entering us on the last transfer.
*/
taskfile_output_data(drive, buffer, nsect * SECTOR_WORDS);
ide_unmap_buffer(buffer, &flags);
bio_kunmap_irq(buffer, &flags);
} while (mcount);
drive->io_32bit = io_32bit;
......
drivers/ide/ide.c
View file @ c0bf9449
......@@ -1781,8 +1781,8 @@ void ide_intr (int irq, void *dev_id, struct pt_regs *regs)
* so in that case we just ignore it and hope it goes away.
*/
#ifdef CONFIG_BLK_DEV_IDEPCI
if (IDE_PCI_DEVID_EQ(hwif->pci_devid, IDE_PCI_DEVID_NULL))
#endif /* CONFIG_BLK_DEV_IDEPCI */
if (hwif->pci_dev && !hwif->pci_dev->vendor)
#endif
{
/*
* Probably not a shared PCI interrupt,
......@@ -1794,7 +1794,7 @@ void ide_intr (int irq, void *dev_id, struct pt_regs *regs)
/*
* Whack the status register, just in case we have a leftover pending IRQ.
*/
(void) IN_BYTE(hwif->io_ports[IDE_STATUS_OFFSET]);
IN_BYTE(hwif->io_ports[IDE_STATUS_OFFSET]);
#endif /* CONFIG_BLK_DEV_IDEPCI */
}
goto out_lock;
......@@ -2304,7 +2304,6 @@ void ide_unregister (unsigned int index)
hwif->udma_four = old_hwif.udma_four;
#ifdef CONFIG_BLK_DEV_IDEPCI
hwif->pci_dev = old_hwif.pci_dev;
hwif->pci_devid = old_hwif.pci_devid;
#endif /* CONFIG_BLK_DEV_IDEPCI */
hwif->straight8 = old_hwif.straight8;
hwif->hwif_data = old_hwif.hwif_data;
......@@ -2650,61 +2649,6 @@ void ide_delay_50ms (void)
#endif /* CONFIG_BLK_DEV_IDECS */
}
int ide_reinit_drive (ide_drive_t *drive)
{
switch (drive->media) {
#ifdef CONFIG_BLK_DEV_IDECD
case ide_cdrom:
{
extern int ide_cdrom_reinit(ide_drive_t *drive);
if (ide_cdrom_reinit(drive))
return 1;
break;
}
#endif /* CONFIG_BLK_DEV_IDECD */
#ifdef CONFIG_BLK_DEV_IDEDISK
case ide_disk:
{
extern int idedisk_reinit(ide_drive_t *drive);
if (idedisk_reinit(drive))
return 1;
break;
}
#endif /* CONFIG_BLK_DEV_IDEDISK */
#ifdef CONFIG_BLK_DEV_IDEFLOPPY
case ide_floppy:
{
extern int idefloppy_reinit(ide_drive_t *drive);
if (idefloppy_reinit(drive))
return 1;
break;
}
#endif /* CONFIG_BLK_DEV_IDEFLOPPY */
#ifdef CONFIG_BLK_DEV_IDETAPE
case ide_tape:
{
extern int idetape_reinit(ide_drive_t *drive);
if (idetape_reinit(drive))
return 1;
break;
}
#endif /* CONFIG_BLK_DEV_IDETAPE */
#ifdef CONFIG_BLK_DEV_IDESCSI
/*
* {
* extern int idescsi_reinit(ide_drive_t *drive);
* if (idescsi_reinit(drive))
* return 1;
* break;
* }
*/
#endif /* CONFIG_BLK_DEV_IDESCSI */
default:
return 1;
}
return 0;
}
static int ide_ioctl (struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
......@@ -3559,20 +3503,20 @@ void __init ide_init_builtin_drivers (void)
* Attempt to match drivers for the available drives
*/
#ifdef CONFIG_BLK_DEV_IDEDISK
(void) idedisk_init();
idedisk_init();
#endif /* CONFIG_BLK_DEV_IDEDISK */
#ifdef CONFIG_BLK_DEV_IDECD
(void) ide_cdrom_init();
ide_cdrom_init();
#endif /* CONFIG_BLK_DEV_IDECD */
#ifdef CONFIG_BLK_DEV_IDETAPE
(void) idetape_init();
idetape_init();
#endif /* CONFIG_BLK_DEV_IDETAPE */
#ifdef CONFIG_BLK_DEV_IDEFLOPPY
(void) idefloppy_init();
idefloppy_init();
#endif /* CONFIG_BLK_DEV_IDEFLOPPY */
#ifdef CONFIG_BLK_DEV_IDESCSI
#ifdef CONFIG_SCSI
(void) idescsi_init();
idescsi_init();
#else
#warning ide scsi-emulation selected but no SCSI-subsystem in kernel
#endif
......@@ -3672,6 +3616,9 @@ ide_drive_t *ide_scan_devices (byte media, const char *name, ide_driver_t *drive
return NULL;
}
/*
* This is in fact registering a drive not a driver.
*/
int ide_register_subdriver (ide_drive_t *drive, ide_driver_t *driver)
{
unsigned long flags;
......@@ -3832,7 +3779,6 @@ EXPORT_SYMBOL(ide_unregister);
EXPORT_SYMBOL(ide_setup_ports);
EXPORT_SYMBOL(get_info_ptr);
EXPORT_SYMBOL(current_capacity);
EXPORT_SYMBOL(ide_reinit_drive);
static int ide_notify_reboot (struct notifier_block *this, unsigned long event, void *x)
{
......
drivers/ide/it8172.c
View file @ c0bf9449
......@@ -53,7 +53,6 @@ static int it8172_tune_chipset (ide_drive_t *drive, byte speed);
static int it8172_config_drive_for_dma (ide_drive_t *drive);
static int it8172_dmaproc(ide_dma_action_t func, ide_drive_t *drive);
#endif
unsigned int __init pci_init_it8172 (struct pci_dev *dev, const char *name);
void __init ide_init_it8172 (ide_hwif_t *hwif);
......@@ -232,7 +231,7 @@ static int it8172_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
#endif /* defined(CONFIG_BLK_DEV_IDEDMA) && (CONFIG_IT8172_TUNING) */
unsigned int __init pci_init_it8172 (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_it8172 (struct pci_dev *dev)
{
unsigned char progif;
......
drivers/ide/pdc202xx.c
View file @ c0bf9449
......@@ -1102,7 +1102,7 @@ static int pdc202xx_tristate (ide_drive_t * drive, int state)
return 0;
}
unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_pdc202xx(struct pci_dev *dev)
{
unsigned long high_16 = pci_resource_start(dev, 4);
byte udma_speed_flag = IN_BYTE(high_16 + 0x001f);
......@@ -1112,7 +1112,7 @@ unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
printk("%s: ROM enabled at 0x%08lx\n", dev->name, dev->resource[PCI_ROM_RESOURCE].start);
}
switch (dev->device) {
......@@ -1151,7 +1151,7 @@ unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); /* 0xbc */
if (irq != irq2) {
pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
printk("%s: pci-config space interrupt mirror fixed.\n", name);
printk("%s: pci-config space interrupt mirror fixed.\n", dev->name);
}
}
break;
......@@ -1163,14 +1163,14 @@ unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
printk("%s: (U)DMA Burst Bit %sABLED " \
"Primary %s Mode " \
"Secondary %s Mode.\n",
name,
dev->name,
(udma_speed_flag & 1) ? "EN" : "DIS",
(primary_mode & 1) ? "MASTER" : "PCI",
(secondary_mode & 1) ? "MASTER" : "PCI" );
#ifdef CONFIG_PDC202XX_BURST
if (!(udma_speed_flag & 1)) {
printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", name, udma_speed_flag, (udma_speed_flag|1));
printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", dev->name, udma_speed_flag, (udma_speed_flag|1));
OUT_BYTE(udma_speed_flag|1, high_16 + 0x001f);
printk("%sCTIVE\n", (IN_BYTE(high_16 + 0x001f) & 1) ? "A" : "INA");
}
......@@ -1179,14 +1179,14 @@ unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
#ifdef CONFIG_PDC202XX_MASTER
if (!(primary_mode & 1)) {
printk("%s: FORCING PRIMARY MODE BIT 0x%02x -> 0x%02x ",
name, primary_mode, (primary_mode|1));
dev->name, primary_mode, (primary_mode|1));
OUT_BYTE(primary_mode|1, high_16 + 0x001a);
printk("%s\n", (IN_BYTE(high_16 + 0x001a) & 1) ? "MASTER" : "PCI");
}
if (!(secondary_mode & 1)) {
printk("%s: FORCING SECONDARY MODE BIT 0x%02x -> 0x%02x ",
name, secondary_mode, (secondary_mode|1));
dev->name, secondary_mode, (secondary_mode|1));
OUT_BYTE(secondary_mode|1, high_16 + 0x001b);
printk("%s\n", (IN_BYTE(high_16 + 0x001b) & 1) ? "MASTER" : "PCI");
}
......
drivers/ide/pdc4030.c
View file @ c0bf9449
......@@ -332,14 +332,14 @@ static ide_startstop_t promise_read_intr (ide_drive_t *drive)
if (nsect > sectors_avail)
nsect = sectors_avail;
sectors_avail -= nsect;
to = ide_map_buffer(rq, &flags);
to = bio_kmap_irq(rq->bio, &flags) + ide_rq_offset(rq);
ata_input_data(drive, to, nsect * SECTOR_WORDS);
#ifdef DEBUG_READ
printk(KERN_DEBUG "%s: promise_read: sectors(%ld-%ld), "
"buf=0x%08lx, rem=%ld\n", drive->name, rq->sector,
rq->sector+nsect-1, (unsigned long) to, rq->nr_sectors-nsect);
#endif
ide_unmap_buffer(to, &flags);
bio_kunmap_irq(to, &flags);
rq->sector += nsect;
rq->errors = 0;
rq->nr_sectors -= nsect;
......@@ -437,7 +437,7 @@ int promise_multwrite (ide_drive_t *drive, unsigned int mcount)
nsect = mcount;
mcount -= nsect;
buffer = ide_map_buffer(rq, &flags);
buffer = bio_kmap_irq(rq->bio, flags) + ide_rq_offset(rq);
rq->sector += nsect;
rq->nr_sectors -= nsect;
rq->current_nr_sectors -= nsect;
......@@ -461,7 +461,7 @@ int promise_multwrite (ide_drive_t *drive, unsigned int mcount)
* re-entering us on the last transfer.
*/
taskfile_output_data(drive, buffer, nsect<<7);
ide_unmap_buffer(buffer, &flags);
bio_kunmap_irq(buffer, &flags);
} while (mcount);
return 0;
......
drivers/ide/pdcadma.c
View file @ c0bf9449
......@@ -71,7 +71,7 @@ int pdcadma_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_pdcadma (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_pdcadma(struct pci_dev *dev)
{
#if defined(DISPLAY_PDCADMA_TIMINGS) && defined(CONFIG_PROC_FS)
if (!pdcadma_proc) {
......
drivers/ide/piix.c
View file @ c0bf9449
......@@ -451,7 +451,7 @@ static int piix_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* defined(CONFIG_BLK_DEV_IDEDMA) && (CONFIG_PIIX_TUNING) */
unsigned int __init pci_init_piix (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_piix(struct pci_dev *dev)
{
#if defined(DISPLAY_PIIX_TIMINGS) && defined(CONFIG_PROC_FS)
if (!piix_proc) {
......
drivers/ide/serverworks.c
View file @ c0bf9449
......@@ -547,7 +547,7 @@ static int svwks_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_svwks (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_svwks(struct pci_dev *dev)
{
unsigned int reg;
byte btr;
......
drivers/ide/sis5513.c
View file @ c0bf9449
......@@ -567,7 +567,7 @@ int sis5513_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_sis5513 (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_sis5513(struct pci_dev *dev)
{
struct pci_dev *host;
int i = 0;
......
drivers/ide/sl82c105.c
View file @ c0bf9449
......@@ -223,7 +223,7 @@ static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
/*
* Enable the PCI device
*/
unsigned int __init pci_init_sl82c105(struct pci_dev *dev, const char *msg)
unsigned int __init pci_init_sl82c105(struct pci_dev *dev)
{
unsigned char ctrl_stat;
......
drivers/ide/slc90e66.c
View file @ c0bf9449
......@@ -347,7 +347,7 @@ static int slc90e66_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
}
#endif /* CONFIG_BLK_DEV_IDEDMA */
unsigned int __init pci_init_slc90e66 (struct pci_dev *dev, const char *name)
unsigned int __init pci_init_slc90e66(struct pci_dev *dev)
{
#if defined(DISPLAY_SLC90E66_TIMINGS) && defined(CONFIG_PROC_FS)
if (!slc90e66_proc) {
......
drivers/ide/via82cxxx.c
View file @ c0bf9449
......@@ -393,7 +393,7 @@ int via82cxxx_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
* and initialize its drive independent registers.
*/
unsigned int __init pci_init_via82cxxx(struct pci_dev *dev, const char *name)
unsigned int __init pci_init_via82cxxx(struct pci_dev *dev)
{
struct pci_dev *isa = NULL;
unsigned char t, v;
......
include/linux/ide.h
View file @ c0bf9449
......@@ -521,16 +521,6 @@ typedef void (ide_rw_proc_t) (ide_drive_t *, ide_dma_action_t);
*/
typedef int (ide_busproc_t) (ide_drive_t *, int);
#ifdef CONFIG_BLK_DEV_IDEPCI
typedef struct ide_pci_devid_s {
unsigned short vid;
unsigned short did;
} ide_pci_devid_t;
#define IDE_PCI_DEVID_NULL ((ide_pci_devid_t){0,0})
#define IDE_PCI_DEVID_EQ(a,b) (a.vid == b.vid && a.did == b.did)
#endif /* CONFIG_BLK_DEV_IDEPCI */
typedef struct hwif_s {
struct hwif_s *next; /* for linked-list in ide_hwgroup_t */
struct hwgroup_s *hwgroup; /* actually (ide_hwgroup_t *) */
......@@ -575,8 +565,7 @@ typedef struct hwif_s {
byte channel; /* for dual-port chips: 0=primary, 1=secondary */
#ifdef CONFIG_BLK_DEV_IDEPCI
struct pci_dev *pci_dev; /* for pci chipsets */
ide_pci_devid_t pci_devid; /* for pci chipsets: {VID,DID} */
#endif /* CONFIG_BLK_DEV_IDEPCI */
#endif
#if (DISK_RECOVERY_TIME > 0)
unsigned long last_time; /* time when previous rq was done */
#endif
......@@ -850,34 +839,6 @@ typedef enum {
#define task_rq_offset(rq) \
(((rq)->nr_sectors - (rq)->current_nr_sectors) * SECTOR_SIZE)
extern inline void *ide_map_buffer(struct request *rq, unsigned long *flags)
{
return bio_kmap_irq(rq->bio, flags) + ide_rq_offset(rq);
}
extern inline void ide_unmap_buffer(char *buffer, unsigned long *flags)
{
bio_kunmap_irq(buffer, flags);
}
/*
* for now, taskfile requests are special :/
*/
extern inline char *ide_map_rq(struct request *rq, unsigned long *flags)
{
if (rq->bio)
return ide_map_buffer(rq, flags);
else
return rq->buffer + task_rq_offset(rq);
}
extern inline void ide_unmap_rq(struct request *rq, char *buf,
unsigned long *flags)
{
if (rq->bio)
ide_unmap_buffer(buf, flags);
}
/*
* This function issues a special IDE device request
* onto the request queue.
......@@ -1027,8 +988,6 @@ void ide_init_subdrivers (void);
extern struct block_device_operations ide_fops[];
extern ide_proc_entry_t generic_subdriver_entries[];
extern int ide_reinit_drive (ide_drive_t *drive);
#ifdef CONFIG_BLK_DEV_IDE
/* Probe for devices attached to the systems host controllers.
*/
......@@ -1069,7 +1028,7 @@ extern int ide_replace_subdriver(ide_drive_t *drive, const char *driver);
# define OFF_BOARD NEVER_BOARD
#endif /* CONFIG_BLK_DEV_OFFBOARD */
void ide_scan_pcibus (int scan_direction) __init;
void __init ide_scan_pcibus(int scan_direction);
#endif
#ifdef CONFIG_BLK_DEV_IDEDMA
#define BAD_DMA_DRIVE 0
......
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