Commit c0cba03b authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "Just radeon and nouveau, mostly regressions fixers, and a couple of
  radeon register checker fixes."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/nouveau: fix acpi edid retrieval
  drm/nvc0/disp: fix regression in vblank semaphore release
  drm/nv40/mpeg: fix context handling
  drm/nv40/graph: fix typo in type names
  drm/nv41/vm: fix typo in type name
  drm/radeon/si: add some missing regs to the VM reg checker
  drm/radeon/cayman: add some missing regs to the VM reg checker
  drm/radeon/dce3: switch back to old pll allocation order for discrete
parents cdfe1565 4a48ed23
...@@ -22,6 +22,8 @@ ...@@ -22,6 +22,8 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <subdev/bar.h>
#include <engine/software.h> #include <engine/software.h>
#include <engine/disp.h> #include <engine/disp.h>
...@@ -37,6 +39,7 @@ nv50_disp_sclass[] = { ...@@ -37,6 +39,7 @@ nv50_disp_sclass[] = {
static void static void
nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
{ {
struct nouveau_bar *bar = nouveau_bar(priv);
struct nouveau_disp *disp = &priv->base; struct nouveau_disp *disp = &priv->base;
struct nouveau_software_chan *chan, *temp; struct nouveau_software_chan *chan, *temp;
unsigned long flags; unsigned long flags;
...@@ -46,18 +49,19 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) ...@@ -46,18 +49,19 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
if (chan->vblank.crtc != crtc) if (chan->vblank.crtc != crtc)
continue; continue;
if (nv_device(priv)->chipset == 0x50) {
nv_wr32(priv, 0x001704, chan->vblank.channel); nv_wr32(priv, 0x001704, chan->vblank.channel);
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
bar->flush(bar);
if (nv_device(priv)->chipset == 0x50) {
nv_wr32(priv, 0x001570, chan->vblank.offset); nv_wr32(priv, 0x001570, chan->vblank.offset);
nv_wr32(priv, 0x001574, chan->vblank.value); nv_wr32(priv, 0x001574, chan->vblank.value);
} else { } else {
if (nv_device(priv)->chipset >= 0xc0) { nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
bar->flush(bar);
nv_wr32(priv, 0x06000c, nv_wr32(priv, 0x06000c,
upper_32_bits(chan->vblank.offset)); upper_32_bits(chan->vblank.offset));
} nv_wr32(priv, 0x060010,
nv_wr32(priv, 0x060010, chan->vblank.offset); lower_32_bits(chan->vblank.offset));
nv_wr32(priv, 0x060014, chan->vblank.value); nv_wr32(priv, 0x060014, chan->vblank.value);
} }
......
...@@ -156,8 +156,8 @@ nv40_graph_context_ctor(struct nouveau_object *parent, ...@@ -156,8 +156,8 @@ nv40_graph_context_ctor(struct nouveau_object *parent,
static int static int
nv40_graph_context_fini(struct nouveau_object *object, bool suspend) nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
{ {
struct nv04_graph_priv *priv = (void *)object->engine; struct nv40_graph_priv *priv = (void *)object->engine;
struct nv04_graph_chan *chan = (void *)object; struct nv40_graph_chan *chan = (void *)object;
u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
int ret = 0; int ret = 0;
......
...@@ -38,7 +38,7 @@ struct nv40_mpeg_priv { ...@@ -38,7 +38,7 @@ struct nv40_mpeg_priv {
}; };
struct nv40_mpeg_chan { struct nv40_mpeg_chan {
struct nouveau_mpeg base; struct nouveau_mpeg_chan base;
}; };
/******************************************************************************* /*******************************************************************************
......
...@@ -67,7 +67,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) ...@@ -67,7 +67,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
static void static void
nv41_vm_flush(struct nouveau_vm *vm) nv41_vm_flush(struct nouveau_vm *vm)
{ {
struct nv04_vm_priv *priv = (void *)vm->vmm; struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
mutex_lock(&nv_subdev(priv)->mutex); mutex_lock(&nv_subdev(priv)->mutex);
nv_wr32(priv, 0x100810, 0x00000022); nv_wr32(priv, 0x100810, 0x00000022);
......
...@@ -355,7 +355,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) ...@@ -355,7 +355,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
* valid - it's not (rh#613284) * valid - it's not (rh#613284)
*/ */
if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) { if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) {
if (!(nv_connector->edid = nouveau_acpi_edid(dev, connector))) { if ((nv_connector->edid = nouveau_acpi_edid(dev, connector))) {
status = connector_status_connected; status = connector_status_connected;
goto out; goto out;
} }
......
...@@ -1696,8 +1696,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) ...@@ -1696,8 +1696,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
return ATOM_PPLL2; return ATOM_PPLL2;
DRM_ERROR("unable to allocate a PPLL\n"); DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID; return ATOM_PPLL_INVALID;
} else { } else if (ASIC_IS_AVIVO(rdev)) {
if (ASIC_IS_AVIVO(rdev)) {
/* in DP mode, the DP ref clock can come from either PPLL /* in DP mode, the DP ref clock can come from either PPLL
* depending on the asic: * depending on the asic:
* DCE3: PPLL1 or PPLL2 * DCE3: PPLL1 or PPLL2
...@@ -1715,17 +1714,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) ...@@ -1715,17 +1714,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
} }
/* all other cases */ /* all other cases */
pll_in_use = radeon_get_pll_use_mask(crtc); pll_in_use = radeon_get_pll_use_mask(crtc);
/* the order shouldn't matter here, but we probably
* need this until we have atomic modeset
*/
if (rdev->flags & RADEON_IS_IGP) {
if (!(pll_in_use & (1 << ATOM_PPLL1))) if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1; return ATOM_PPLL1;
if (!(pll_in_use & (1 << ATOM_PPLL2))) if (!(pll_in_use & (1 << ATOM_PPLL2)))
return ATOM_PPLL2; return ATOM_PPLL2;
} else {
if (!(pll_in_use & (1 << ATOM_PPLL2)))
return ATOM_PPLL2;
if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1;
}
DRM_ERROR("unable to allocate a PPLL\n"); DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID; return ATOM_PPLL_INVALID;
} else { } else {
/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
return radeon_crtc->crtc_id; return radeon_crtc->crtc_id;
} }
}
} }
void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
......
...@@ -2725,6 +2725,9 @@ static bool evergreen_vm_reg_valid(u32 reg) ...@@ -2725,6 +2725,9 @@ static bool evergreen_vm_reg_valid(u32 reg)
/* check config regs */ /* check config regs */
switch (reg) { switch (reg) {
case GRBM_GFX_INDEX: case GRBM_GFX_INDEX:
case CP_STRMOUT_CNTL:
case CP_COHER_CNTL:
case CP_COHER_SIZE:
case VGT_VTX_VECT_EJECT_REG: case VGT_VTX_VECT_EJECT_REG:
case VGT_CACHE_INVALIDATION: case VGT_CACHE_INVALIDATION:
case VGT_GS_VERTEX_REUSE: case VGT_GS_VERTEX_REUSE:
......
...@@ -91,6 +91,10 @@ ...@@ -91,6 +91,10 @@
#define FB_READ_EN (1 << 0) #define FB_READ_EN (1 << 0)
#define FB_WRITE_EN (1 << 1) #define FB_WRITE_EN (1 << 1)
#define CP_STRMOUT_CNTL 0x84FC
#define CP_COHER_CNTL 0x85F0
#define CP_COHER_SIZE 0x85F4
#define CP_COHER_BASE 0x85F8 #define CP_COHER_BASE 0x85F8
#define CP_STALLED_STAT1 0x8674 #define CP_STALLED_STAT1 0x8674
#define CP_STALLED_STAT2 0x8678 #define CP_STALLED_STAT2 0x8678
......
...@@ -2474,6 +2474,7 @@ static bool si_vm_reg_valid(u32 reg) ...@@ -2474,6 +2474,7 @@ static bool si_vm_reg_valid(u32 reg)
/* check config regs */ /* check config regs */
switch (reg) { switch (reg) {
case GRBM_GFX_INDEX: case GRBM_GFX_INDEX:
case CP_STRMOUT_CNTL:
case VGT_VTX_VECT_EJECT_REG: case VGT_VTX_VECT_EJECT_REG:
case VGT_CACHE_INVALIDATION: case VGT_CACHE_INVALIDATION:
case VGT_ESGS_RING_SIZE: case VGT_ESGS_RING_SIZE:
......
...@@ -424,6 +424,7 @@ ...@@ -424,6 +424,7 @@
# define RDERR_INT_ENABLE (1 << 0) # define RDERR_INT_ENABLE (1 << 0)
# define GUI_IDLE_INT_ENABLE (1 << 19) # define GUI_IDLE_INT_ENABLE (1 << 19)
#define CP_STRMOUT_CNTL 0x84FC
#define SCRATCH_REG0 0x8500 #define SCRATCH_REG0 0x8500
#define SCRATCH_REG1 0x8504 #define SCRATCH_REG1 0x8504
#define SCRATCH_REG2 0x8508 #define SCRATCH_REG2 0x8508
......
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