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Commit c1bd940a authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/rt5670', 'asoc/topic/rt5677',... 

Merge remote-tracking branches 'asoc/topic/rt5670', 'asoc/topic/rt5677', 'asoc/topic/s6000', 'asoc/topic/samsung' and 'asoc/topic/sh-fsi' into asoc-next
parents b0ae27c4 01957572 f18803a3 1bb60b3a 71864b22 9f98cd69
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Showing with 5147 additions and 852 deletions
Documentation/devicetree/bindings/sound/samsung,odroidx2-max98090.txt 0 → 100644
View file @ c1bd940a
Samsung Exynos Odroid X2/U3 audio complex with MAX98090 codec
Required properties:
- compatible : "samsung,odroidx2-audio" - for Odroid X2 board,
"samsung,odroidu3-audio" - for Odroid U3 board
- samsung,model : the user-visible name of this sound complex
- samsung,i2s-controller : the phandle of the I2S controller
- samsung,audio-codec : the phandle of the MAX98090 audio codec
- samsung,audio-routing : a list of the connections between audio
components; each entry is a pair of strings, the first being the
connection's sink, the second being the connection's source;
valid names for sources and sinks are the MAX98090's pins (as
documented in its binding), and the jacks on the board
For Odroid X2:
* Headphone Jack
* Mic Jack
* DMIC
For Odroid U3:
* Headphone Jack
* Speakers
Example:
sound {
compatible = "samsung,odroidu3-audio";
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&max98090>;
samsung,model = "Odroid-X2";
samsung,audio-routing =
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"IN1", "Mic Jack",
"Mic Jack", "MICBIAS";
};
Documentation/devicetree/bindings/sound/snow.txt
View file @ c1bd940a
......@@ -3,15 +3,20 @@ Audio Binding for Snow boards
Required properties:
- compatible : Can be one of the following,
"google,snow-audio-max98090" or
"google,snow-audio-max98091" or
"google,snow-audio-max98095"
- samsung,i2s-controller: The phandle of the Samsung I2S controller
- samsung,audio-codec: The phandle of the audio codec
Optional:
- samsung,model: The name of the sound-card
Example:
sound {
compatible = "google,snow-audio-max98095";
samsung,model = "Snow-I2S-MAX98095";
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&max98095>;
};
include/linux/platform_data/asoc-s3c.h
View file @ c1bd940a
......@@ -15,15 +15,6 @@
#define S3C64XX_AC97_GPE 1
extern void s3c64xx_ac97_setup_gpio(int);
/*
* The machine init code calls s5p*_spdif_setup_gpio with
* one of these defines in order to select appropriate bank
* of GPIO for S/PDIF pins
*/
#define S5PC100_SPDIF_GPD 0
#define S5PC100_SPDIF_GPG3 1
extern void s5pc100_spdif_setup_gpio(int);
struct samsung_i2s {
/* If the Primary DAI has 5.1 Channels */
#define QUIRK_PRI_6CHAN (1 << 0)
......
include/sound/rt5670.h 0 → 100644
View file @ c1bd940a
/*
* linux/sound/rt5670.h -- Platform data for RT5670
*
* Copyright 2014 Realtek Microelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_RT5670_H
#define __LINUX_SND_RT5670_H
struct rt5670_platform_data {
int jd_mode;
bool in2_diff;
bool dmic_en;
unsigned int dmic1_data_pin;
/* 0 = GPIO6; 1 = IN2P; 3 = GPIO7*/
unsigned int dmic2_data_pin;
/* 0 = GPIO8; 1 = IN3N; */
unsigned int dmic3_data_pin;
/* 0 = GPIO9; 1 = GPIO10; 2 = GPIO5*/
};
#endif
sound/soc/codecs/Kconfig
View file @ c1bd940a
......@@ -80,6 +80,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_RT5640 if I2C
select SND_SOC_RT5645 if I2C
select SND_SOC_RT5651 if I2C
select SND_SOC_RT5670 if I2C
select SND_SOC_RT5677 if I2C
select SND_SOC_SGTL5000 if I2C
select SND_SOC_SI476X if MFD_SI476X_CORE
......@@ -452,9 +453,13 @@ config SND_SOC_RL6231
default y if SND_SOC_RT5640=y
default y if SND_SOC_RT5645=y
default y if SND_SOC_RT5651=y
default y if SND_SOC_RT5670=y
default y if SND_SOC_RT5677=y
default m if SND_SOC_RT5640=m
default m if SND_SOC_RT5645=m
default m if SND_SOC_RT5651=m
default m if SND_SOC_RT5670=m
default m if SND_SOC_RT5677=m
config SND_SOC_RT286
tristate
......@@ -471,6 +476,9 @@ config SND_SOC_RT5645
config SND_SOC_RT5651
tristate
config SND_SOC_RT5670
tristate
config SND_SOC_RT5677
tristate
......
sound/soc/codecs/Makefile
View file @ c1bd940a
......@@ -74,6 +74,7 @@ snd-soc-rt5631-objs := rt5631.o
snd-soc-rt5640-objs := rt5640.o
snd-soc-rt5645-objs := rt5645.o
snd-soc-rt5651-objs := rt5651.o
snd-soc-rt5670-objs := rt5670.o
snd-soc-rt5677-objs := rt5677.o
snd-soc-sgtl5000-objs := sgtl5000.o
snd-soc-alc5623-objs := alc5623.o
......@@ -243,6 +244,7 @@ obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
......
sound/soc/codecs/rt5670-dsp.h 0 → 100644
View file @ c1bd940a
/*
* rt5670-dsp.h -- RT5670 ALSA SoC DSP driver
*
* Copyright 2014 Realtek Microelectronics
* Author: Bard Liao <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5670_DSP_H__
#define __RT5670_DSP_H__
#define RT5670_DSP_CTRL1 0xe0
#define RT5670_DSP_CTRL2 0xe1
#define RT5670_DSP_CTRL3 0xe2
#define RT5670_DSP_CTRL4 0xe3
#define RT5670_DSP_CTRL5 0xe4
/* DSP Control 1 (0xe0) */
#define RT5670_DSP_CMD_MASK (0xff << 8)
#define RT5670_DSP_CMD_PE (0x0d << 8) /* Patch Entry */
#define RT5670_DSP_CMD_MW (0x3b << 8) /* Memory Write */
#define RT5670_DSP_CMD_MR (0x37 << 8) /* Memory Read */
#define RT5670_DSP_CMD_RR (0x60 << 8) /* Register Read */
#define RT5670_DSP_CMD_RW (0x68 << 8) /* Register Write */
#define RT5670_DSP_REG_DATHI (0x26 << 8) /* High Data Addr */
#define RT5670_DSP_REG_DATLO (0x25 << 8) /* Low Data Addr */
#define RT5670_DSP_CLK_MASK (0x3 << 6)
#define RT5670_DSP_CLK_SFT 6
#define RT5670_DSP_CLK_768K (0x0 << 6)
#define RT5670_DSP_CLK_384K (0x1 << 6)
#define RT5670_DSP_CLK_192K (0x2 << 6)
#define RT5670_DSP_CLK_96K (0x3 << 6)
#define RT5670_DSP_BUSY_MASK (0x1 << 5)
#define RT5670_DSP_RW_MASK (0x1 << 4)
#define RT5670_DSP_DL_MASK (0x3 << 2)
#define RT5670_DSP_DL_0 (0x0 << 2)
#define RT5670_DSP_DL_1 (0x1 << 2)
#define RT5670_DSP_DL_2 (0x2 << 2)
#define RT5670_DSP_DL_3 (0x3 << 2)
#define RT5670_DSP_I2C_AL_16 (0x1 << 1)
#define RT5670_DSP_CMD_EN (0x1)
struct rt5670_dsp_param {
u16 cmd_fmt;
u16 addr;
u16 data;
u8 cmd;
};
#endif /* __RT5670_DSP_H__ */
sound/soc/codecs/rt5670.c 0 → 100644
View file @ c1bd940a
/*
* rt5670.c -- RT5670 ALSA SoC audio codec driver
*
* Copyright 2014 Realtek Semiconductor Corp.
* Author: Bard Liao <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/rt5670.h>
#include "rl6231.h"
#include "rt5670.h"
#include "rt5670-dsp.h"
#define RT5670_DEVICE_ID 0x6271
#define RT5670_PR_RANGE_BASE (0xff + 1)
#define RT5670_PR_SPACING 0x100
#define RT5670_PR_BASE (RT5670_PR_RANGE_BASE + (0 * RT5670_PR_SPACING))
static const struct regmap_range_cfg rt5670_ranges[] = {
{ .name = "PR", .range_min = RT5670_PR_BASE,
.range_max = RT5670_PR_BASE + 0xf8,
.selector_reg = RT5670_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5670_PRIV_DATA,
.window_len = 0x1, },
};
static struct reg_default init_list[] = {
{ RT5670_PR_BASE + 0x14, 0x9a8a },
{ RT5670_PR_BASE + 0x38, 0x3ba1 },
{ RT5670_PR_BASE + 0x3d, 0x3640 },
};
#define RT5670_INIT_REG_LEN ARRAY_SIZE(init_list)
static const struct reg_default rt5670_reg[] = {
{ 0x00, 0x0000 },
{ 0x02, 0x8888 },
{ 0x03, 0x8888 },
{ 0x0a, 0x0001 },
{ 0x0b, 0x0827 },
{ 0x0c, 0x0000 },
{ 0x0d, 0x0008 },
{ 0x0e, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x19, 0xafaf },
{ 0x1a, 0xafaf },
{ 0x1b, 0x0011 },
{ 0x1c, 0x2f2f },
{ 0x1d, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x1f, 0x2f2f },
{ 0x20, 0x0000 },
{ 0x26, 0x7860 },
{ 0x27, 0x7860 },
{ 0x28, 0x7871 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5656 },
{ 0x2b, 0x5454 },
{ 0x2c, 0xaaa0 },
{ 0x2d, 0x0000 },
{ 0x2e, 0x2f2f },
{ 0x2f, 0x1002 },
{ 0x30, 0x0000 },
{ 0x31, 0x5f00 },
{ 0x32, 0x0000 },
{ 0x33, 0x0000 },
{ 0x34, 0x0000 },
{ 0x35, 0x0000 },
{ 0x36, 0x0000 },
{ 0x37, 0x0000 },
{ 0x38, 0x0000 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x007f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x007f },
{ 0x45, 0xe00f },
{ 0x4c, 0x5380 },
{ 0x4f, 0x0073 },
{ 0x52, 0x00d3 },
{ 0x53, 0xf0f0 },
{ 0x61, 0x0000 },
{ 0x62, 0x0001 },
{ 0x63, 0x00c3 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x6f, 0x8000 },
{ 0x70, 0x8000 },
{ 0x71, 0x8000 },
{ 0x72, 0x8000 },
{ 0x73, 0x1110 },
{ 0x74, 0x0e00 },
{ 0x75, 0x1505 },
{ 0x76, 0x0015 },
{ 0x77, 0x0c00 },
{ 0x78, 0x4000 },
{ 0x79, 0x0123 },
{ 0x7f, 0x1100 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x83, 0x0000 },
{ 0x84, 0x0000 },
{ 0x85, 0x0000 },
{ 0x86, 0x0008 },
{ 0x87, 0x0000 },
{ 0x88, 0x0000 },
{ 0x89, 0x0000 },
{ 0x8a, 0x0000 },
{ 0x8b, 0x0000 },
{ 0x8c, 0x0007 },
{ 0x8d, 0x0000 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0646 },
{ 0x91, 0x0c06 },
{ 0x93, 0x0000 },
{ 0x94, 0x0000 },
{ 0x95, 0x0000 },
{ 0x97, 0x0000 },
{ 0x98, 0x0000 },
{ 0x99, 0x0000 },
{ 0x9a, 0x2184 },
{ 0x9b, 0x010a },
{ 0x9c, 0x0aea },
{ 0x9d, 0x000c },
{ 0x9e, 0x0400 },
{ 0xae, 0x7000 },
{ 0xaf, 0x0000 },
{ 0xb0, 0x6000 },
{ 0xb1, 0x0000 },
{ 0xb2, 0x0000 },
{ 0xb3, 0x001f },
{ 0xb4, 0x2206 },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xb7, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0000 },
{ 0xc0, 0x0000 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x1813 },
{ 0xd0, 0x0690 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xb320 },
{ 0xd4, 0x0000 },
{ 0xd6, 0x0400 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xdb, 0x0001 },
{ 0xdc, 0x0049 },
{ 0xdd, 0x0009 },
{ 0xe6, 0x8000 },
{ 0xe7, 0x0000 },
{ 0xec, 0xb300 },
{ 0xed, 0x0000 },
{ 0xee, 0xb300 },
{ 0xef, 0x0000 },
{ 0xf8, 0x0000 },
{ 0xf9, 0x0000 },
{ 0xfa, 0x8010 },
{ 0xfb, 0x0033 },
{ 0xfc, 0x0080 },
};
static bool rt5670_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
if ((reg >= rt5670_ranges[i].window_start &&
reg <= rt5670_ranges[i].window_start +
rt5670_ranges[i].window_len) ||
(reg >= rt5670_ranges[i].range_min &&
reg <= rt5670_ranges[i].range_max)) {
return true;
}
}
switch (reg) {
case RT5670_RESET:
case RT5670_PDM_DATA_CTRL1:
case RT5670_PDM1_DATA_CTRL4:
case RT5670_PDM2_DATA_CTRL4:
case RT5670_PRIV_DATA:
case RT5670_ASRC_5:
case RT5670_CJ_CTRL1:
case RT5670_CJ_CTRL2:
case RT5670_CJ_CTRL3:
case RT5670_A_JD_CTRL1:
case RT5670_A_JD_CTRL2:
case RT5670_VAD_CTRL5:
case RT5670_ADC_EQ_CTRL1:
case RT5670_EQ_CTRL1:
case RT5670_ALC_CTRL_1:
case RT5670_IRQ_CTRL1:
case RT5670_IRQ_CTRL2:
case RT5670_INT_IRQ_ST:
case RT5670_IL_CMD:
case RT5670_DSP_CTRL1:
case RT5670_DSP_CTRL2:
case RT5670_DSP_CTRL3:
case RT5670_DSP_CTRL4:
case RT5670_DSP_CTRL5:
case RT5670_VENDOR_ID:
case RT5670_VENDOR_ID1:
case RT5670_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5670_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
if ((reg >= rt5670_ranges[i].window_start &&
reg <= rt5670_ranges[i].window_start +
rt5670_ranges[i].window_len) ||
(reg >= rt5670_ranges[i].range_min &&
reg <= rt5670_ranges[i].range_max)) {
return true;
}
}
switch (reg) {
case RT5670_RESET:
case RT5670_HP_VOL:
case RT5670_LOUT1:
case RT5670_CJ_CTRL1:
case RT5670_CJ_CTRL2:
case RT5670_CJ_CTRL3:
case RT5670_IN2:
case RT5670_INL1_INR1_VOL:
case RT5670_DAC1_DIG_VOL:
case RT5670_DAC2_DIG_VOL:
case RT5670_DAC_CTRL:
case RT5670_STO1_ADC_DIG_VOL:
case RT5670_MONO_ADC_DIG_VOL:
case RT5670_STO2_ADC_DIG_VOL:
case RT5670_ADC_BST_VOL1:
case RT5670_ADC_BST_VOL2:
case RT5670_STO2_ADC_MIXER:
case RT5670_STO1_ADC_MIXER:
case RT5670_MONO_ADC_MIXER:
case RT5670_AD_DA_MIXER:
case RT5670_STO_DAC_MIXER:
case RT5670_DD_MIXER:
case RT5670_DIG_MIXER:
case RT5670_DSP_PATH1:
case RT5670_DSP_PATH2:
case RT5670_DIG_INF1_DATA:
case RT5670_DIG_INF2_DATA:
case RT5670_PDM_OUT_CTRL:
case RT5670_PDM_DATA_CTRL1:
case RT5670_PDM1_DATA_CTRL2:
case RT5670_PDM1_DATA_CTRL3:
case RT5670_PDM1_DATA_CTRL4:
case RT5670_PDM2_DATA_CTRL2:
case RT5670_PDM2_DATA_CTRL3:
case RT5670_PDM2_DATA_CTRL4:
case RT5670_REC_L1_MIXER:
case RT5670_REC_L2_MIXER:
case RT5670_REC_R1_MIXER:
case RT5670_REC_R2_MIXER:
case RT5670_HPO_MIXER:
case RT5670_MONO_MIXER:
case RT5670_OUT_L1_MIXER:
case RT5670_OUT_R1_MIXER:
case RT5670_LOUT_MIXER:
case RT5670_PWR_DIG1:
case RT5670_PWR_DIG2:
case RT5670_PWR_ANLG1:
case RT5670_PWR_ANLG2:
case RT5670_PWR_MIXER:
case RT5670_PWR_VOL:
case RT5670_PRIV_INDEX:
case RT5670_PRIV_DATA:
case RT5670_I2S4_SDP:
case RT5670_I2S1_SDP:
case RT5670_I2S2_SDP:
case RT5670_I2S3_SDP:
case RT5670_ADDA_CLK1:
case RT5670_ADDA_CLK2:
case RT5670_DMIC_CTRL1:
case RT5670_DMIC_CTRL2:
case RT5670_TDM_CTRL_1:
case RT5670_TDM_CTRL_2:
case RT5670_TDM_CTRL_3:
case RT5670_DSP_CLK:
case RT5670_GLB_CLK:
case RT5670_PLL_CTRL1:
case RT5670_PLL_CTRL2:
case RT5670_ASRC_1:
case RT5670_ASRC_2:
case RT5670_ASRC_3:
case RT5670_ASRC_4:
case RT5670_ASRC_5:
case RT5670_ASRC_7:
case RT5670_ASRC_8:
case RT5670_ASRC_9:
case RT5670_ASRC_10:
case RT5670_ASRC_11:
case RT5670_ASRC_12:
case RT5670_ASRC_13:
case RT5670_ASRC_14:
case RT5670_DEPOP_M1:
case RT5670_DEPOP_M2:
case RT5670_DEPOP_M3:
case RT5670_CHARGE_PUMP:
case RT5670_MICBIAS:
case RT5670_A_JD_CTRL1:
case RT5670_A_JD_CTRL2:
case RT5670_VAD_CTRL1:
case RT5670_VAD_CTRL2:
case RT5670_VAD_CTRL3:
case RT5670_VAD_CTRL4:
case RT5670_VAD_CTRL5:
case RT5670_ADC_EQ_CTRL1:
case RT5670_ADC_EQ_CTRL2:
case RT5670_EQ_CTRL1:
case RT5670_EQ_CTRL2:
case RT5670_ALC_DRC_CTRL1:
case RT5670_ALC_DRC_CTRL2:
case RT5670_ALC_CTRL_1:
case RT5670_ALC_CTRL_2:
case RT5670_ALC_CTRL_3:
case RT5670_JD_CTRL:
case RT5670_IRQ_CTRL1:
case RT5670_IRQ_CTRL2:
case RT5670_INT_IRQ_ST:
case RT5670_GPIO_CTRL1:
case RT5670_GPIO_CTRL2:
case RT5670_GPIO_CTRL3:
case RT5670_SCRABBLE_FUN:
case RT5670_SCRABBLE_CTRL:
case RT5670_BASE_BACK:
case RT5670_MP3_PLUS1:
case RT5670_MP3_PLUS2:
case RT5670_ADJ_HPF1:
case RT5670_ADJ_HPF2:
case RT5670_HP_CALIB_AMP_DET:
case RT5670_SV_ZCD1:
case RT5670_SV_ZCD2:
case RT5670_IL_CMD:
case RT5670_IL_CMD2:
case RT5670_IL_CMD3:
case RT5670_DRC_HL_CTRL1:
case RT5670_DRC_HL_CTRL2:
case RT5670_ADC_MONO_HP_CTRL1:
case RT5670_ADC_MONO_HP_CTRL2:
case RT5670_ADC_STO2_HP_CTRL1:
case RT5670_ADC_STO2_HP_CTRL2:
case RT5670_JD_CTRL3:
case RT5670_JD_CTRL4:
case RT5670_DIG_MISC:
case RT5670_DSP_CTRL1:
case RT5670_DSP_CTRL2:
case RT5670_DSP_CTRL3:
case RT5670_DSP_CTRL4:
case RT5670_DSP_CTRL5:
case RT5670_GEN_CTRL2:
case RT5670_GEN_CTRL3:
case RT5670_VENDOR_ID:
case RT5670_VENDOR_ID1:
case RT5670_VENDOR_ID2:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static unsigned int bst_tlv[] = {
TLV_DB_RANGE_HEAD(7),
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
};
/* Interface data select */
static const char * const rt5670_data_select[] = {
"Normal", "Swap", "left copy to right", "right copy to left"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA,
RT5670_IF2_DAC_SEL_SFT, rt5670_data_select);
static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA,
RT5670_IF2_ADC_SEL_SFT, rt5670_data_select);
static const struct snd_kcontrol_new rt5670_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE("HP Playback Switch", RT5670_HP_VOL,
RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
39, 0, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,
RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("OUT Playback Volume", RT5670_LOUT1,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE("DAC2 Playback Switch", RT5670_DAC_CTRL,
RT5670_M_DAC_L2_VOL_SFT, RT5670_M_DAC_R2_VOL_SFT, 1, 1),
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5670_DAC1_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
175, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5670_DAC2_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
175, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5670_CJ_CTRL1,
RT5670_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5670_IN2,
RT5670_BST_SFT1, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5670_INL1_INR1_VOL,
RT5670_INL_VOL_SFT, RT5670_INR_VOL_SFT,
31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5670_STO1_ADC_DIG_VOL,
RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5670_STO1_ADC_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
127, 0, adc_vol_tlv),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5670_MONO_ADC_DIG_VOL,
RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
RT5670_STO1_ADC_L_BST_SFT, RT5670_STO1_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
RT5670_STO2_ADC_L_BST_SFT, RT5670_STO2_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum),
SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
int idx = -EINVAL;
idx = rl6231_calc_dmic_clk(rt5670->sysclk);
if (idx < 0)
dev_err(codec->dev, "Failed to set DMIC clock\n");
else
snd_soc_update_bits(codec, RT5670_DMIC_CTRL1,
RT5670_DMIC_CLK_MASK, idx << RT5670_DMIC_CLK_SFT);
return idx;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
val = snd_soc_read(source->codec, RT5670_GLB_CLK);
val &= RT5670_SCLK_SRC_MASK;
if (val == RT5670_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
unsigned int reg, shift, val;
switch (source->shift) {
case 0:
reg = RT5670_ASRC_3;
shift = 0;
break;
case 1:
reg = RT5670_ASRC_3;
shift = 4;
break;
case 2:
reg = RT5670_ASRC_5;
shift = 12;
break;
case 3:
reg = RT5670_ASRC_2;
shift = 0;
break;
case 8:
reg = RT5670_ASRC_2;
shift = 4;
break;
case 9:
reg = RT5670_ASRC_2;
shift = 8;
break;
case 10:
reg = RT5670_ASRC_2;
shift = 12;
break;
default:
return 0;
}
val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
switch (val) {
case 1:
case 2:
case 3:
case 4:
return 1;
default:
return 0;
}
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5670_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
RT5670_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
RT5670_M_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
RT5670_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
RT5670_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
RT5670_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
RT5670_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
RT5670_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_L2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_R1_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_R2_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
RT5670_M_DAC_L1_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_L1_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_L2_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_R2_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_R1_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_R2_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
RT5670_M_DAC_L2_MONO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_dig_l_mix[] = {
SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5670_DIG_MIXER,
RT5670_M_STO_L_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_L2_DAC_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_R2_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_dig_r_mix[] = {
SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5670_DIG_MIXER,
RT5670_M_STO_R_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_R2_DAC_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
RT5670_M_DAC_L2_DAC_R_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5670_rec_l_mix[] = {
SOC_DAPM_SINGLE("INL Switch", RT5670_REC_L2_MIXER,
RT5670_M_IN_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_L2_MIXER,
RT5670_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_L2_MIXER,
RT5670_M_BST1_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_rec_r_mix[] = {
SOC_DAPM_SINGLE("INR Switch", RT5670_REC_R2_MIXER,
RT5670_M_IN_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_R2_MIXER,
RT5670_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_R2_MIXER,
RT5670_M_BST1_RM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5670_OUT_L1_MIXER,
RT5670_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5670_OUT_L1_MIXER,
RT5670_M_IN_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
RT5670_M_DAC_L2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_OUT_L1_MIXER,
RT5670_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5670_OUT_R1_MIXER,
RT5670_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5670_OUT_R1_MIXER,
RT5670_M_IN_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
RT5670_M_DAC_R2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
RT5670_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpo_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
RT5670_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPVOL Switch", RT5670_HPO_MIXER,
RT5670_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpvoll_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
RT5670_M_DACL1_HML_SFT, 1, 1),
SOC_DAPM_SINGLE("INL Switch", RT5670_HPO_MIXER,
RT5670_M_INL1_HML_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpvolr_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
RT5670_M_DACR1_HMR_SFT, 1, 1),
SOC_DAPM_SINGLE("INR Switch", RT5670_HPO_MIXER,
RT5670_M_INR1_HMR_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_LOUT_MIXER,
RT5670_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
RT5670_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX L Switch", RT5670_LOUT_MIXER,
RT5670_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTMIX R Switch", RT5670_LOUT_MIXER,
RT5670_M_OV_R_LM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpl_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_HPO_MIXER,
RT5670_M_DACL1_HML_SFT, 1, 1),
SOC_DAPM_SINGLE("INL1 Switch", RT5670_HPO_MIXER,
RT5670_M_INL1_HML_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5670_hpr_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_HPO_MIXER,
RT5670_M_DACR1_HMR_SFT, 1, 1),
SOC_DAPM_SINGLE("INR1 Switch", RT5670_HPO_MIXER,
RT5670_M_INR1_HMR_SFT, 1, 1),
};
static const struct snd_kcontrol_new lout_l_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
RT5670_L_MUTE_SFT, 1, 1);
static const struct snd_kcontrol_new lout_r_enable_control =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
RT5670_R_MUTE_SFT, 1, 1);
/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
static const char * const rt5670_dac1_src[] = {
"IF1 DAC", "IF2 DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dac1l_enum, RT5670_AD_DA_MIXER,
RT5670_DAC1_L_SEL_SFT, rt5670_dac1_src);
static const struct snd_kcontrol_new rt5670_dac1l_mux =
SOC_DAPM_ENUM("DAC1 L source", rt5670_dac1l_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_dac1r_enum, RT5670_AD_DA_MIXER,
RT5670_DAC1_R_SEL_SFT, rt5670_dac1_src);
static const struct snd_kcontrol_new rt5670_dac1r_mux =
SOC_DAPM_ENUM("DAC1 R source", rt5670_dac1r_enum);
/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
/* TODO Use SOC_VALUE_ENUM_SINGLE_DECL */
static const char * const rt5670_dac12_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC",
"Bass", "VAD_ADC", "IF4 DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dac2l_enum, RT5670_DAC_CTRL,
RT5670_DAC2_L_SEL_SFT, rt5670_dac12_src);
static const struct snd_kcontrol_new rt5670_dac_l2_mux =
SOC_DAPM_ENUM("DAC2 L source", rt5670_dac2l_enum);
static const char * const rt5670_dacr2_src[] = {
"IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dac2r_enum, RT5670_DAC_CTRL,
RT5670_DAC2_R_SEL_SFT, rt5670_dacr2_src);
static const struct snd_kcontrol_new rt5670_dac_r2_mux =
SOC_DAPM_ENUM("DAC2 R source", rt5670_dac2r_enum);
/*RxDP source*/ /* MX-2D [15:13] */
static const char * const rt5670_rxdp_src[] = {
"IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
"Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
};
static SOC_ENUM_SINGLE_DECL(rt5670_rxdp_enum, RT5670_DSP_PATH1,
RT5670_RXDP_SEL_SFT, rt5670_rxdp_src);
static const struct snd_kcontrol_new rt5670_rxdp_mux =
SOC_DAPM_ENUM("DAC2 L source", rt5670_rxdp_enum);
/* MX-2D [1] [0] */
static const char * const rt5670_dsp_bypass_src[] = {
"DSP", "Bypass"
};
static SOC_ENUM_SINGLE_DECL(rt5670_dsp_ul_enum, RT5670_DSP_PATH1,
RT5670_DSP_UL_SFT, rt5670_dsp_bypass_src);
static const struct snd_kcontrol_new rt5670_dsp_ul_mux =
SOC_DAPM_ENUM("DSP UL source", rt5670_dsp_ul_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_dsp_dl_enum, RT5670_DSP_PATH1,
RT5670_DSP_DL_SFT, rt5670_dsp_bypass_src);
static const struct snd_kcontrol_new rt5670_dsp_dl_mux =
SOC_DAPM_ENUM("DSP DL source", rt5670_dsp_dl_enum);
/* Stereo2 ADC source */
/* MX-26 [15] */
static const char * const rt5670_stereo2_adc_lr_src[] = {
"L", "LR"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_lr_enum, RT5670_STO2_ADC_MIXER,
RT5670_STO2_ADC_SRC_SFT, rt5670_stereo2_adc_lr_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_lr_mux =
SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5670_stereo2_adc_lr_enum);
/* Stereo1 ADC source */
/* MX-27 MX-26 [12] */
static const char * const rt5670_stereo_adc1_src[] = {
"DAC MIX", "ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc1_enum, RT5670_STO1_ADC_MIXER,
RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
static const struct snd_kcontrol_new rt5670_sto_adc_l1_mux =
SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5670_stereo1_adc1_enum);
static const struct snd_kcontrol_new rt5670_sto_adc_r1_mux =
SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5670_stereo1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc1_enum, RT5670_STO2_ADC_MIXER,
RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_l1_mux =
SOC_DAPM_ENUM("Stereo2 ADC L1 source", rt5670_stereo2_adc1_enum);
static const struct snd_kcontrol_new rt5670_sto2_adc_r1_mux =
SOC_DAPM_ENUM("Stereo2 ADC R1 source", rt5670_stereo2_adc1_enum);
/* MX-27 MX-26 [11] */
static const char * const rt5670_stereo_adc2_src[] = {
"DAC MIX", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc2_enum, RT5670_STO1_ADC_MIXER,
RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
static const struct snd_kcontrol_new rt5670_sto_adc_l2_mux =
SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5670_stereo1_adc2_enum);
static const struct snd_kcontrol_new rt5670_sto_adc_r2_mux =
SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5670_stereo1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc2_enum, RT5670_STO2_ADC_MIXER,
RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_l2_mux =
SOC_DAPM_ENUM("Stereo2 ADC L2 source", rt5670_stereo2_adc2_enum);
static const struct snd_kcontrol_new rt5670_sto2_adc_r2_mux =
SOC_DAPM_ENUM("Stereo2 ADC R2 source", rt5670_stereo2_adc2_enum);
/* MX-27 MX26 [10] */
static const char * const rt5670_stereo_adc_src[] = {
"ADC1L ADC2R", "ADC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc_enum, RT5670_STO1_ADC_MIXER,
RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
static const struct snd_kcontrol_new rt5670_sto_adc_mux =
SOC_DAPM_ENUM("Stereo1 ADC source", rt5670_stereo1_adc_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_enum, RT5670_STO2_ADC_MIXER,
RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
static const struct snd_kcontrol_new rt5670_sto2_adc_mux =
SOC_DAPM_ENUM("Stereo2 ADC source", rt5670_stereo2_adc_enum);
/* MX-27 MX-26 [9:8] */
static const char * const rt5670_stereo_dmic_src[] = {
"DMIC1", "DMIC2", "DMIC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_dmic_enum, RT5670_STO1_ADC_MIXER,
RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
static const struct snd_kcontrol_new rt5670_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC source", rt5670_stereo1_dmic_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_dmic_enum, RT5670_STO2_ADC_MIXER,
RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
static const struct snd_kcontrol_new rt5670_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC source", rt5670_stereo2_dmic_enum);
/* MX-27 [0] */
static const char * const rt5670_stereo_dmic3_src[] = {
"DMIC3", "PDM ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_stereo_dmic3_enum, RT5670_STO1_ADC_MIXER,
RT5670_DMIC3_SRC_SFT, rt5670_stereo_dmic3_src);
static const struct snd_kcontrol_new rt5670_sto_dmic3_mux =
SOC_DAPM_ENUM("Stereo DMIC3 source", rt5670_stereo_dmic3_enum);
/* Mono ADC source */
/* MX-28 [12] */
static const char * const rt5670_mono_adc_l1_src[] = {
"Mono DAC MIXL", "ADC1"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l1_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_L1_SRC_SFT, rt5670_mono_adc_l1_src);
static const struct snd_kcontrol_new rt5670_mono_adc_l1_mux =
SOC_DAPM_ENUM("Mono ADC1 left source", rt5670_mono_adc_l1_enum);
/* MX-28 [11] */
static const char * const rt5670_mono_adc_l2_src[] = {
"Mono DAC MIXL", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l2_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_L2_SRC_SFT, rt5670_mono_adc_l2_src);
static const struct snd_kcontrol_new rt5670_mono_adc_l2_mux =
SOC_DAPM_ENUM("Mono ADC2 left source", rt5670_mono_adc_l2_enum);
/* MX-28 [9:8] */
static const char * const rt5670_mono_dmic_src[] = {
"DMIC1", "DMIC2", "DMIC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_l_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_DMIC_L_SRC_SFT, rt5670_mono_dmic_src);
static const struct snd_kcontrol_new rt5670_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC left source", rt5670_mono_dmic_l_enum);
/* MX-28 [1:0] */
static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_r_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_DMIC_R_SRC_SFT, rt5670_mono_dmic_src);
static const struct snd_kcontrol_new rt5670_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC Right source", rt5670_mono_dmic_r_enum);
/* MX-28 [4] */
static const char * const rt5670_mono_adc_r1_src[] = {
"Mono DAC MIXR", "ADC2"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r1_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_R1_SRC_SFT, rt5670_mono_adc_r1_src);
static const struct snd_kcontrol_new rt5670_mono_adc_r1_mux =
SOC_DAPM_ENUM("Mono ADC1 right source", rt5670_mono_adc_r1_enum);
/* MX-28 [3] */
static const char * const rt5670_mono_adc_r2_src[] = {
"Mono DAC MIXR", "DMIC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r2_enum, RT5670_MONO_ADC_MIXER,
RT5670_MONO_ADC_R2_SRC_SFT, rt5670_mono_adc_r2_src);
static const struct snd_kcontrol_new rt5670_mono_adc_r2_mux =
SOC_DAPM_ENUM("Mono ADC2 right source", rt5670_mono_adc_r2_enum);
/* MX-2D [3:2] */
static const char * const rt5670_txdp_slot_src[] = {
"Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
};
static SOC_ENUM_SINGLE_DECL(rt5670_txdp_slot_enum, RT5670_DSP_PATH1,
RT5670_TXDP_SLOT_SEL_SFT, rt5670_txdp_slot_src);
static const struct snd_kcontrol_new rt5670_txdp_slot_mux =
SOC_DAPM_ENUM("TxDP Slot source", rt5670_txdp_slot_enum);
/* MX-2F [15] */
static const char * const rt5670_if1_adc2_in_src[] = {
"IF_ADC2", "VAD_ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in_enum, RT5670_DIG_INF1_DATA,
RT5670_IF1_ADC2_IN_SFT, rt5670_if1_adc2_in_src);
static const struct snd_kcontrol_new rt5670_if1_adc2_in_mux =
SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5670_if1_adc2_in_enum);
/* MX-2F [14:12] */
static const char * const rt5670_if2_adc_in_src[] = {
"IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_in_enum, RT5670_DIG_INF1_DATA,
RT5670_IF2_ADC_IN_SFT, rt5670_if2_adc_in_src);
static const struct snd_kcontrol_new rt5670_if2_adc_in_mux =
SOC_DAPM_ENUM("IF2 ADC IN source", rt5670_if2_adc_in_enum);
/* MX-30 [5:4] */
static const char * const rt5670_if4_adc_in_src[] = {
"IF_ADC1", "IF_ADC2", "IF_ADC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if4_adc_in_enum, RT5670_DIG_INF2_DATA,
RT5670_IF4_ADC_IN_SFT, rt5670_if4_adc_in_src);
static const struct snd_kcontrol_new rt5670_if4_adc_in_mux =
SOC_DAPM_ENUM("IF4 ADC IN source", rt5670_if4_adc_in_enum);
/* MX-31 [15] [13] [11] [9] */
static const char * const rt5670_pdm_src[] = {
"Mono DAC", "Stereo DAC"
};
static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_l_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM1_L_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm1_l_mux =
SOC_DAPM_ENUM("PDM1 L source", rt5670_pdm1_l_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_r_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM1_R_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm1_r_mux =
SOC_DAPM_ENUM("PDM1 R source", rt5670_pdm1_r_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_l_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM2_L_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm2_l_mux =
SOC_DAPM_ENUM("PDM2 L source", rt5670_pdm2_l_enum);
static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_r_enum, RT5670_PDM_OUT_CTRL,
RT5670_PDM2_R_SFT, rt5670_pdm_src);
static const struct snd_kcontrol_new rt5670_pdm2_r_mux =
SOC_DAPM_ENUM("PDM2 R source", rt5670_pdm2_r_enum);
/* MX-FA [12] */
static const char * const rt5670_if1_adc1_in1_src[] = {
"IF_ADC1", "IF1_ADC3"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in1_enum, RT5670_DIG_MISC,
RT5670_IF1_ADC1_IN1_SFT, rt5670_if1_adc1_in1_src);
static const struct snd_kcontrol_new rt5670_if1_adc1_in1_mux =
SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5670_if1_adc1_in1_enum);
/* MX-FA [11] */
static const char * const rt5670_if1_adc1_in2_src[] = {
"IF1_ADC1_IN1", "IF1_ADC4"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in2_enum, RT5670_DIG_MISC,
RT5670_IF1_ADC1_IN2_SFT, rt5670_if1_adc1_in2_src);
static const struct snd_kcontrol_new rt5670_if1_adc1_in2_mux =
SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5670_if1_adc1_in2_enum);
/* MX-FA [10] */
static const char * const rt5670_if1_adc2_in1_src[] = {
"IF1_ADC2_IN", "IF1_ADC4"
};
static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in1_enum, RT5670_DIG_MISC,
RT5670_IF1_ADC2_IN1_SFT, rt5670_if1_adc2_in1_src);
static const struct snd_kcontrol_new rt5670_if1_adc2_in1_mux =
SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5670_if1_adc2_in1_enum);
/* MX-9D [9:8] */
static const char * const rt5670_vad_adc_src[] = {
"Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
};
static SOC_ENUM_SINGLE_DECL(rt5670_vad_adc_enum, RT5670_VAD_CTRL4,
RT5670_VAD_SEL_SFT, rt5670_vad_adc_src);
static const struct snd_kcontrol_new rt5670_vad_adc_mux =
SOC_DAPM_ENUM("VAD ADC source", rt5670_vad_adc_enum);
static int rt5670_hp_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5670->regmap, RT5670_CHARGE_PUMP,
RT5670_PM_HP_MASK, RT5670_PM_HP_HV);
regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
0x0400, 0x0400);
/* headphone amp power on */
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
RT5670_PWR_HA | RT5670_PWR_FV1 |
RT5670_PWR_FV2, RT5670_PWR_HA |
RT5670_PWR_FV1 | RT5670_PWR_FV2);
/* depop parameters */
regmap_write(rt5670->regmap, RT5670_DEPOP_M2, 0x3100);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8009);
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_HP_DCC_INT1, 0x9f00);
mdelay(20);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x0004);
msleep(30);
break;
default:
return 0;
}
return 0;
}
static int rt5670_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* headphone unmute sequence */
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_MAMP_INT_REG2, 0xb400);
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x805d);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
0x0300, 0x0300);
regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
RT5670_L_MUTE | RT5670_R_MUTE, 0);
msleep(80);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
break;
case SND_SOC_DAPM_PRE_PMD:
/* headphone mute sequence */
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_MAMP_INT_REG2, 0xb400);
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x803d);
mdelay(10);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
mdelay(10);
regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
RT5670_L_MUTE | RT5670_R_MUTE,
RT5670_L_MUTE | RT5670_R_MUTE);
msleep(20);
regmap_update_bits(rt5670->regmap,
RT5670_GEN_CTRL2, 0x0300, 0x0);
regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0707);
regmap_write(rt5670->regmap, RT5670_PR_BASE +
RT5670_MAMP_INT_REG2, 0xfc00);
break;
default:
return 0;
}
return 0;
}
static int rt5670_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
RT5670_PWR_BST1_P, RT5670_PWR_BST1_P);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
RT5670_PWR_BST1_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5670_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
RT5670_PWR_BST2_P, RT5670_PWR_BST2_P);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
RT5670_PWR_BST2_P, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5670_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
RT5670_PWR_PLL_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S DSP", RT5670_PWR_DIG2,
RT5670_PWR_I2S_DSP_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5670_PWR_VOL,
RT5670_PWR_MIC_DET_BIT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5670_ASRC_1,
11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5670_ASRC_1,
12, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5670_ASRC_1,
10, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5670_ASRC_1,
9, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5670_ASRC_1,
8, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5670_ASRC_1,
3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5670_ASRC_1,
2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5670_ASRC_1,
1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5670_ASRC_1,
0, 0, NULL, 0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5670_PWR_ANLG2,
RT5670_PWR_MB1_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("DMIC L3"),
SND_SOC_DAPM_INPUT("DMIC R3"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5670_DMIC_CTRL1,
RT5670_DMIC_1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5670_DMIC_CTRL1,
RT5670_DMIC_2_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5670_DMIC_CTRL1,
RT5670_DMIC_3_EN_SFT, 0, NULL, 0),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5670_PWR_ANLG2, RT5670_PWR_BST1_BIT,
0, NULL, 0, rt5670_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5670_PWR_ANLG2, RT5670_PWR_BST2_BIT,
0, NULL, 0, rt5670_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Input Volume */
SND_SOC_DAPM_PGA("INL VOL", RT5670_PWR_VOL,
RT5670_PWR_IN_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR VOL", RT5670_PWR_VOL,
RT5670_PWR_IN_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5670_PWR_MIXER, RT5670_PWR_RM_L_BIT, 0,
rt5670_rec_l_mix, ARRAY_SIZE(rt5670_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5670_PWR_MIXER, RT5670_PWR_RM_R_BIT, 0,
rt5670_rec_r_mix, ARRAY_SIZE(rt5670_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5670_PWR_DIG1,
RT5670_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5670_PWR_DIG1,
RT5670_PWR_ADC_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC clock", RT5670_PR_BASE +
RT5670_CHOP_DAC_ADC, 12, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto1_dmic_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_l2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_r2_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_l1_mux),
SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto_adc_r1_mux),
SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_dmic_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_l2_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_r2_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_l1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_r1_mux),
SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
&rt5670_sto2_adc_lr_mux),
SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_dmic_l_mux),
SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_dmic_r_mux),
SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_l2_mux),
SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_l1_mux),
SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_r1_mux),
SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_mono_adc_r2_mux),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_S2F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", RT5670_STO1_ADC_DIG_VOL,
RT5670_L_MUTE_SFT, 1, rt5670_sto1_adc_l_mix,
ARRAY_SIZE(rt5670_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", RT5670_STO1_ADC_DIG_VOL,
RT5670_R_MUTE_SFT, 1, rt5670_sto1_adc_r_mix,
ARRAY_SIZE(rt5670_sto1_adc_r_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_sto2_adc_l_mix,
ARRAY_SIZE(rt5670_sto2_adc_l_mix)),
SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_sto2_adc_r_mix,
ARRAY_SIZE(rt5670_sto2_adc_r_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5670_MONO_ADC_DIG_VOL,
RT5670_L_MUTE_SFT, 1, rt5670_mono_adc_l_mix,
ARRAY_SIZE(rt5670_mono_adc_l_mix)),
SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5670_PWR_DIG2,
RT5670_PWR_ADC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5670_MONO_ADC_DIG_VOL,
RT5670_R_MUTE_SFT, 1, rt5670_mono_adc_r_mix,
ARRAY_SIZE(rt5670_mono_adc_r_mix)),
/* ADC PGA */
SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DSP */
SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
&rt5670_txdp_slot_mux),
SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dsp_ul_mux),
SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dsp_dl_mux),
SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
&rt5670_rxdp_mux),
/* IF2 Mux */
SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if2_adc_in_mux),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5670_PWR_DIG1,
RT5670_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("I2S2", RT5670_PWR_DIG1,
RT5670_PWR_I2S2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc1_in1_mux),
SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc1_in2_mux),
SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc2_in_mux),
SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_if1_adc2_in1_mux),
SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
&rt5670_vad_adc_mux),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
RT5670_GPIO_CTRL1, RT5670_I2S2_PIN_SFT, 1),
/* Audio DSP */
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
rt5670_dac_l_mix, ARRAY_SIZE(rt5670_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
rt5670_dac_r_mix, ARRAY_SIZE(rt5670_dac_r_mix)),
SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DAC2 channel Mux */
SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dac_l2_mux),
SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
&rt5670_dac_r2_mux),
SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
RT5670_PWR_DAC_L2_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
RT5670_PWR_DAC_R2_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1l_mux),
SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1r_mux),
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5670_PWR_DIG2,
RT5670_PWR_DAC_S1F_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5670_PWR_DIG2,
RT5670_PWR_DAC_MF_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5670_PWR_DIG2,
RT5670_PWR_DAC_MF_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_sto_dac_l_mix,
ARRAY_SIZE(rt5670_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_sto_dac_r_mix,
ARRAY_SIZE(rt5670_sto_dac_r_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_mono_dac_l_mix,
ARRAY_SIZE(rt5670_mono_dac_l_mix)),
SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_mono_dac_r_mix,
ARRAY_SIZE(rt5670_mono_dac_r_mix)),
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5670_dig_l_mix,
ARRAY_SIZE(rt5670_dig_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5670_dig_r_mix,
ARRAY_SIZE(rt5670_dig_r_mix)),
/* DACs */
SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5670_PWR_DIG1,
RT5670_PWR_DAC_L1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
RT5670_PWR_DAC_R1_BIT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
RT5670_PWR_DAC_L2_BIT, 0),
SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
RT5670_PWR_DAC_R2_BIT, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("OUT MIXL", RT5670_PWR_MIXER, RT5670_PWR_OM_L_BIT,
0, rt5670_out_l_mix, ARRAY_SIZE(rt5670_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5670_PWR_MIXER, RT5670_PWR_OM_R_BIT,
0, rt5670_out_r_mix, ARRAY_SIZE(rt5670_out_r_mix)),
/* Ouput Volume */
SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5670_PWR_VOL,
RT5670_PWR_HV_L_BIT, 0,
rt5670_hpvoll_mix, ARRAY_SIZE(rt5670_hpvoll_mix)),
SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5670_PWR_VOL,
RT5670_PWR_HV_R_BIT, 0,
rt5670_hpvolr_mix, ARRAY_SIZE(rt5670_hpvolr_mix)),
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
rt5670_hpo_mix, ARRAY_SIZE(rt5670_hpo_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", RT5670_PWR_ANLG1, RT5670_PWR_LM_BIT,
0, rt5670_lout_mix, ARRAY_SIZE(rt5670_lout_mix)),
SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 0, 0,
rt5670_hp_power_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("HP L Amp", RT5670_PWR_ANLG1,
RT5670_PWR_HP_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("HP R Amp", RT5670_PWR_ANLG1,
RT5670_PWR_HP_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
rt5670_hp_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
&lout_l_enable_control),
SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
&lout_r_enable_control),
SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
/* PDM */
SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5670_PWR_DIG2,
RT5670_PWR_PDM1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5670_PWR_DIG2,
RT5670_PWR_PDM2_BIT, 0, NULL, 0),
SND_SOC_DAPM_MUX("PDM1 L Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM1_L_SFT, 1, &rt5670_pdm1_l_mux),
SND_SOC_DAPM_MUX("PDM1 R Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM1_R_SFT, 1, &rt5670_pdm1_r_mux),
SND_SOC_DAPM_MUX("PDM2 L Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM2_L_SFT, 1, &rt5670_pdm2_l_mux),
SND_SOC_DAPM_MUX("PDM2 R Mux", RT5670_PDM_OUT_CTRL,
RT5670_M_PDM2_R_SFT, 1, &rt5670_pdm2_r_mux),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
SND_SOC_DAPM_OUTPUT("PDM1L"),
SND_SOC_DAPM_OUTPUT("PDM1R"),
SND_SOC_DAPM_OUTPUT("PDM2L"),
SND_SOC_DAPM_OUTPUT("PDM2R"),
};
static const struct snd_soc_dapm_route rt5670_dapm_routes[] = {
{ "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
{ "ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc },
{ "ADC Mono Left Filter", NULL, "ADC MONO L ASRC", is_using_asrc },
{ "ADC Mono Right Filter", NULL, "ADC MONO R ASRC", is_using_asrc },
{ "DAC Mono Left Filter", NULL, "DAC MONO L ASRC", is_using_asrc },
{ "DAC Mono Right Filter", NULL, "DAC MONO R ASRC", is_using_asrc },
{ "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
{ "I2S1", NULL, "I2S1 ASRC" },
{ "I2S2", NULL, "I2S2 ASRC" },
{ "DMIC1", NULL, "DMIC L1" },
{ "DMIC1", NULL, "DMIC R1" },
{ "DMIC2", NULL, "DMIC L2" },
{ "DMIC2", NULL, "DMIC R2" },
{ "DMIC3", NULL, "DMIC L3" },
{ "DMIC3", NULL, "DMIC R3" },
{ "BST1", NULL, "IN1P" },
{ "BST1", NULL, "IN1N" },
{ "BST1", NULL, "Mic Det Power" },
{ "BST2", NULL, "IN2P" },
{ "BST2", NULL, "IN2N" },
{ "INL VOL", NULL, "IN2P" },
{ "INR VOL", NULL, "IN2N" },
{ "RECMIXL", "INL Switch", "INL VOL" },
{ "RECMIXL", "BST2 Switch", "BST2" },
{ "RECMIXL", "BST1 Switch", "BST1" },
{ "RECMIXR", "INR Switch", "INR VOL" },
{ "RECMIXR", "BST2 Switch", "BST2" },
{ "RECMIXR", "BST1 Switch", "BST1" },
{ "ADC 1", NULL, "RECMIXL" },
{ "ADC 1", NULL, "ADC 1 power" },
{ "ADC 1", NULL, "ADC clock" },
{ "ADC 2", NULL, "RECMIXR" },
{ "ADC 2", NULL, "ADC 2 power" },
{ "ADC 2", NULL, "ADC clock" },
{ "DMIC L1", NULL, "DMIC CLK" },
{ "DMIC L1", NULL, "DMIC1 Power" },
{ "DMIC R1", NULL, "DMIC CLK" },
{ "DMIC R1", NULL, "DMIC1 Power" },
{ "DMIC L2", NULL, "DMIC CLK" },
{ "DMIC L2", NULL, "DMIC2 Power" },
{ "DMIC R2", NULL, "DMIC CLK" },
{ "DMIC R2", NULL, "DMIC2 Power" },
{ "DMIC L3", NULL, "DMIC CLK" },
{ "DMIC L3", NULL, "DMIC3 Power" },
{ "DMIC R3", NULL, "DMIC CLK" },
{ "DMIC R3", NULL, "DMIC3 Power" },
{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
{ "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
{ "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
{ "ADC 1_2", NULL, "ADC 1" },
{ "ADC 1_2", NULL, "ADC 2" },
{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC L1 Mux", "ADC", "ADC 1_2" },
{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
{ "Mono ADC L1 Mux", "ADC1", "ADC 1" },
{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Mono ADC R1 Mux", "ADC2", "ADC 2" },
{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
{ "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
{ "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
{ "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
{ "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
{ "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
{ "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
{ "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
{ "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
{ "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo2 ADC L1 Mux", "ADC", "ADC 1_2" },
{ "Stereo2 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
{ "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
{ "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
{ "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
{ "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux" },
{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
{ "Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter" },
{ "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
{ "Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter" },
{ "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
{ "VAD ADC Mux", "Sto2 ADC L", "Sto2 ADC MIXL" },
{ "VAD_ADC", NULL, "VAD ADC Mux" },
{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
{ "IF_ADC2", NULL, "Mono ADC MIXL" },
{ "IF_ADC2", NULL, "Mono ADC MIXR" },
{ "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
{ "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
{ "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
{ "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF1_ADC3" },
{ "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
{ "IF1 ADC1 IN2 Mux", "IF1_ADC4", "IF1_ADC4" },
{ "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
{ "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
{ "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
{ "IF1 ADC2 IN1 Mux", "IF1_ADC4", "IF1_ADC4" },
{ "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
{ "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
{ "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXL" },
{ "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXR" },
{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
{ "RxDP Mux", "IF2 DAC", "IF2 DAC" },
{ "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
{ "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
{ "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
{ "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
{ "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
{ "RxDP Mux", "DAC1", "DAC MIX" },
{ "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
{ "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
{ "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
{ "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
{ "DSP UL Mux", "Bypass", "TDM Data Mux" },
{ "DSP UL Mux", NULL, "I2S DSP" },
{ "DSP DL Mux", "Bypass", "RxDP Mux" },
{ "DSP DL Mux", NULL, "I2S DSP" },
{ "TxDP_ADC_L", NULL, "DSP UL Mux" },
{ "TxDP_ADC_R", NULL, "DSP UL Mux" },
{ "TxDC_DAC", NULL, "DSP DL Mux" },
{ "TxDP_ADC", NULL, "TxDP_ADC_L" },
{ "TxDP_ADC", NULL, "TxDP_ADC_R" },
{ "IF1 ADC", NULL, "I2S1" },
{ "IF1 ADC", NULL, "IF1_ADC1" },
{ "IF1 ADC", NULL, "IF1_ADC2" },
{ "IF1 ADC", NULL, "IF_ADC3" },
{ "IF1 ADC", NULL, "TxDP_ADC" },
{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
{ "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
{ "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
{ "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
{ "IF2 ADC L", NULL, "IF2 ADC Mux" },
{ "IF2 ADC R", NULL, "IF2 ADC Mux" },
{ "IF2 ADC", NULL, "I2S2" },
{ "IF2 ADC", NULL, "IF2 ADC L" },
{ "IF2 ADC", NULL, "IF2 ADC R" },
{ "AIF1TX", NULL, "IF1 ADC" },
{ "AIF2TX", NULL, "IF2 ADC" },
{ "IF1 DAC1", NULL, "AIF1RX" },
{ "IF1 DAC2", NULL, "AIF1RX" },
{ "IF2 DAC", NULL, "AIF2RX" },
{ "IF1 DAC1", NULL, "I2S1" },
{ "IF1 DAC2", NULL, "I2S1" },
{ "IF2 DAC", NULL, "I2S2" },
{ "IF1 DAC2 L", NULL, "IF1 DAC2" },
{ "IF1 DAC2 R", NULL, "IF1 DAC2" },
{ "IF1 DAC1 L", NULL, "IF1 DAC1" },
{ "IF1 DAC1 R", NULL, "IF1 DAC1" },
{ "IF2 DAC L", NULL, "IF2 DAC" },
{ "IF2 DAC R", NULL, "IF2 DAC" },
{ "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
{ "DAC1 MIXL", NULL, "DAC Stereo1 Filter" },
{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
{ "DAC1 MIXR", NULL, "DAC Stereo1 Filter" },
{ "DAC MIX", NULL, "DAC1 MIXL" },
{ "DAC MIX", NULL, "DAC1 MIXR" },
{ "Audio DSP", NULL, "DAC1 MIXL" },
{ "Audio DSP", NULL, "DAC1 MIXR" },
{ "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
{ "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
{ "DAC L2 Volume", NULL, "DAC L2 Mux" },
{ "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
{ "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
{ "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
{ "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
{ "DAC R2 Volume", NULL, "DAC R2 Mux" },
{ "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "Stereo DAC MIXL", NULL, "DAC Stereo1 Filter" },
{ "Stereo DAC MIXL", NULL, "DAC L1 Power" },
{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "Stereo DAC MIXR", NULL, "DAC Stereo1 Filter" },
{ "Stereo DAC MIXR", NULL, "DAC R1 Power" },
{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
{ "Mono DAC MIXL", NULL, "DAC Mono Left Filter" },
{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
{ "Mono DAC MIXR", NULL, "DAC Mono Right Filter" },
{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
{ "DAC L1", NULL, "DAC L1 Power" },
{ "DAC L1", NULL, "Stereo DAC MIXL" },
{ "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC R1", NULL, "DAC R1 Power" },
{ "DAC R1", NULL, "Stereo DAC MIXR" },
{ "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC L2", NULL, "Mono DAC MIXL" },
{ "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
{ "DAC R2", NULL, "Mono DAC MIXR" },
{ "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
{ "OUT MIXL", "BST1 Switch", "BST1" },
{ "OUT MIXL", "INL Switch", "INL VOL" },
{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },
{ "OUT MIXR", "BST2 Switch", "BST2" },
{ "OUT MIXR", "INR Switch", "INR VOL" },
{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },
{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
{ "HPOVOL MIXL", "INL Switch", "INL VOL" },
{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
{ "HPOVOL MIXR", "INR Switch", "INR VOL" },
{ "DAC 2", NULL, "DAC L2" },
{ "DAC 2", NULL, "DAC R2" },
{ "DAC 1", NULL, "DAC L1" },
{ "DAC 1", NULL, "DAC R1" },
{ "HPOVOL", NULL, "HPOVOL MIXL" },
{ "HPOVOL", NULL, "HPOVOL MIXR" },
{ "HPO MIX", "DAC1 Switch", "DAC 1" },
{ "HPO MIX", "HPVOL Switch", "HPOVOL" },
{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },
{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },
{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
{ "PDM1 L Mux", NULL, "PDM1 Power" },
{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
{ "PDM1 R Mux", NULL, "PDM1 Power" },
{ "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
{ "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
{ "PDM2 L Mux", NULL, "PDM2 Power" },
{ "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
{ "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
{ "PDM2 R Mux", NULL, "PDM2 Power" },
{ "HP Amp", NULL, "HPO MIX" },
{ "HP Amp", NULL, "Mic Det Power" },
{ "HPOL", NULL, "HP Amp" },
{ "HPOL", NULL, "HP L Amp" },
{ "HPOL", NULL, "Improve HP Amp Drv" },
{ "HPOR", NULL, "HP Amp" },
{ "HPOR", NULL, "HP R Amp" },
{ "HPOR", NULL, "Improve HP Amp Drv" },
{ "LOUT Amp", NULL, "LOUT MIX" },
{ "LOUT L Playback", "Switch", "LOUT Amp" },
{ "LOUT R Playback", "Switch", "LOUT Amp" },
{ "LOUTL", NULL, "LOUT L Playback" },
{ "LOUTR", NULL, "LOUT R Playback" },
{ "LOUTL", NULL, "Improve HP Amp Drv" },
{ "LOUTR", NULL, "Improve HP Amp Drv" },
{ "PDM1L", NULL, "PDM1 L Mux" },
{ "PDM1R", NULL, "PDM1 R Mux" },
{ "PDM2L", NULL, "PDM2 L Mux" },
{ "PDM2R", NULL, "PDM2 R Mux" },
};
static int rt5670_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5670->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5670->sysclk, rt5670->lrck[dai->id]);
if (pre_div < 0) {
dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
rt5670->lrck[dai->id], dai->id);
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32;
rt5670->bclk[dai->id] = rt5670->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5670->bclk[dai->id], rt5670->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_width(params)) {
case 16:
break;
case 20:
val_len |= RT5670_I2S_DL_20;
break;
case 24:
val_len |= RT5670_I2S_DL_24;
break;
case 8:
val_len |= RT5670_I2S_DL_8;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5670_AIF1:
mask_clk = RT5670_I2S_BCLK_MS1_MASK | RT5670_I2S_PD1_MASK;
val_clk = bclk_ms << RT5670_I2S_BCLK_MS1_SFT |
pre_div << RT5670_I2S_PD1_SFT;
snd_soc_update_bits(codec, RT5670_I2S1_SDP,
RT5670_I2S_DL_MASK, val_len);
snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
break;
case RT5670_AIF2:
mask_clk = RT5670_I2S_BCLK_MS2_MASK | RT5670_I2S_PD2_MASK;
val_clk = bclk_ms << RT5670_I2S_BCLK_MS2_SFT |
pre_div << RT5670_I2S_PD2_SFT;
snd_soc_update_bits(codec, RT5670_I2S2_SDP,
RT5670_I2S_DL_MASK, val_len);
snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
break;
default:
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5670_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5670->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5670_I2S_MS_S;
rt5670->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5670_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5670_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5670_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5670_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
switch (dai->id) {
case RT5670_AIF1:
snd_soc_update_bits(codec, RT5670_I2S1_SDP,
RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
RT5670_I2S_DF_MASK, reg_val);
break;
case RT5670_AIF2:
snd_soc_update_bits(codec, RT5670_I2S2_SDP,
RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
RT5670_I2S_DF_MASK, reg_val);
break;
default:
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
return 0;
}
static int rt5670_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
unsigned int reg_val = 0;
if (freq == rt5670->sysclk && clk_id == rt5670->sysclk_src)
return 0;
switch (clk_id) {
case RT5670_SCLK_S_MCLK:
reg_val |= RT5670_SCLK_SRC_MCLK;
break;
case RT5670_SCLK_S_PLL1:
reg_val |= RT5670_SCLK_SRC_PLL1;
break;
case RT5670_SCLK_S_RCCLK:
reg_val |= RT5670_SCLK_SRC_RCCLK;
break;
default:
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_update_bits(codec, RT5670_GLB_CLK,
RT5670_SCLK_SRC_MASK, reg_val);
rt5670->sysclk = freq;
rt5670->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5670_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5670->pll_src && freq_in == rt5670->pll_in &&
freq_out == rt5670->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(codec->dev, "PLL disabled\n");
rt5670->pll_in = 0;
rt5670->pll_out = 0;
snd_soc_update_bits(codec, RT5670_GLB_CLK,
RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5670_PLL1_S_MCLK:
snd_soc_update_bits(codec, RT5670_GLB_CLK,
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_MCLK);
break;
case RT5670_PLL1_S_BCLK1:
case RT5670_PLL1_S_BCLK2:
case RT5670_PLL1_S_BCLK3:
case RT5670_PLL1_S_BCLK4:
switch (dai->id) {
case RT5670_AIF1:
snd_soc_update_bits(codec, RT5670_GLB_CLK,
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK1);
break;
case RT5670_AIF2:
snd_soc_update_bits(codec, RT5670_GLB_CLK,
RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK2);
break;
default:
dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
return -EINVAL;
}
break;
default:
dev_err(codec->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
return ret;
}
dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_write(codec, RT5670_PLL_CTRL1,
pll_code.n_code << RT5670_PLL_N_SFT | pll_code.k_code);
snd_soc_write(codec, RT5670_PLL_CTRL2,
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5670_PLL_M_SFT |
pll_code.m_bp << RT5670_PLL_M_BP_SFT);
rt5670->pll_in = freq_in;
rt5670->pll_out = freq_out;
rt5670->pll_src = source;
return 0;
}
static int rt5670_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct snd_soc_codec *codec = dai->codec;
unsigned int val = 0;
if (rx_mask || tx_mask)
val |= (1 << 14);
switch (slots) {
case 4:
val |= (1 << 12);
break;
case 6:
val |= (2 << 12);
break;
case 8:
val |= (3 << 12);
break;
case 2:
break;
default:
return -EINVAL;
}
switch (slot_width) {
case 20:
val |= (1 << 10);
break;
case 24:
val |= (2 << 10);
break;
case 32:
val |= (3 << 10);
break;
case 16:
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5670_TDM_CTRL_1, 0x7c00, val);
return 0;
}
static int rt5670_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
RT5670_PWR_VREF1 | RT5670_PWR_MB |
RT5670_PWR_BG | RT5670_PWR_VREF2,
RT5670_PWR_VREF1 | RT5670_PWR_MB |
RT5670_PWR_BG | RT5670_PWR_VREF2);
mdelay(10);
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
RT5670_PWR_FV1 | RT5670_PWR_FV2,
RT5670_PWR_FV1 | RT5670_PWR_FV2);
snd_soc_update_bits(codec, RT5670_CHARGE_PUMP,
RT5670_OSW_L_MASK | RT5670_OSW_R_MASK,
RT5670_OSW_L_DIS | RT5670_OSW_R_DIS);
snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x1);
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
RT5670_LDO_SEL_MASK, 0x3);
}
break;
case SND_SOC_BIAS_STANDBY:
snd_soc_write(codec, RT5670_PWR_DIG1, 0x0000);
snd_soc_write(codec, RT5670_PWR_DIG2, 0x0001);
snd_soc_write(codec, RT5670_PWR_VOL, 0x0000);
snd_soc_write(codec, RT5670_PWR_MIXER, 0x0001);
snd_soc_write(codec, RT5670_PWR_ANLG1, 0x2800);
snd_soc_write(codec, RT5670_PWR_ANLG2, 0x0004);
snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x0);
snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
RT5670_LDO_SEL_MASK, 0x1);
break;
default:
break;
}
codec->dapm.bias_level = level;
return 0;
}
static int rt5670_probe(struct snd_soc_codec *codec)
{
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
rt5670->codec = codec;
return 0;
}
static int rt5670_remove(struct snd_soc_codec *codec)
{
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
regmap_write(rt5670->regmap, RT5670_RESET, 0);
return 0;
}
#ifdef CONFIG_PM
static int rt5670_suspend(struct snd_soc_codec *codec)
{
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
regcache_cache_only(rt5670->regmap, true);
regcache_mark_dirty(rt5670->regmap);
return 0;
}
static int rt5670_resume(struct snd_soc_codec *codec)
{
struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
regcache_cache_only(rt5670->regmap, false);
regcache_sync(rt5670->regmap);
return 0;
}
#else
#define rt5670_suspend NULL
#define rt5670_resume NULL
#endif
#define RT5670_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5670_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
static struct snd_soc_dai_ops rt5670_aif_dai_ops = {
.hw_params = rt5670_hw_params,
.set_fmt = rt5670_set_dai_fmt,
.set_sysclk = rt5670_set_dai_sysclk,
.set_tdm_slot = rt5670_set_tdm_slot,
.set_pll = rt5670_set_dai_pll,
};
static struct snd_soc_dai_driver rt5670_dai[] = {
{
.name = "rt5670-aif1",
.id = RT5670_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.ops = &rt5670_aif_dai_ops,
},
{
.name = "rt5670-aif2",
.id = RT5670_AIF2,
.playback = {
.stream_name = "AIF2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.capture = {
.stream_name = "AIF2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5670_STEREO_RATES,
.formats = RT5670_FORMATS,
},
.ops = &rt5670_aif_dai_ops,
},
};
static struct snd_soc_codec_driver soc_codec_dev_rt5670 = {
.probe = rt5670_probe,
.remove = rt5670_remove,
.suspend = rt5670_suspend,
.resume = rt5670_resume,
.set_bias_level = rt5670_set_bias_level,
.idle_bias_off = true,
.controls = rt5670_snd_controls,
.num_controls = ARRAY_SIZE(rt5670_snd_controls),
.dapm_widgets = rt5670_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5670_dapm_widgets),
.dapm_routes = rt5670_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5670_dapm_routes),
};
static const struct regmap_config rt5670_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = RT5670_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5670_ranges) *
RT5670_PR_SPACING),
.volatile_reg = rt5670_volatile_register,
.readable_reg = rt5670_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt5670_reg,
.num_reg_defaults = ARRAY_SIZE(rt5670_reg),
.ranges = rt5670_ranges,
.num_ranges = ARRAY_SIZE(rt5670_ranges),
};
static const struct i2c_device_id rt5670_i2c_id[] = {
{ "rt5670", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);
static int rt5670_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct rt5670_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5670_priv *rt5670;
int ret;
unsigned int val;
rt5670 = devm_kzalloc(&i2c->dev,
sizeof(struct rt5670_priv),
GFP_KERNEL);
if (NULL == rt5670)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5670);
if (pdata)
rt5670->pdata = *pdata;
rt5670->regmap = devm_regmap_init_i2c(i2c, &rt5670_regmap);
if (IS_ERR(rt5670->regmap)) {
ret = PTR_ERR(rt5670->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val);
if (val != RT5670_DEVICE_ID) {
dev_err(&i2c->dev,
"Device with ID register %x is not rt5670/72\n", val);
return -ENODEV;
}
regmap_write(rt5670->regmap, RT5670_RESET, 0);
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
RT5670_PWR_HP_L | RT5670_PWR_HP_R |
RT5670_PWR_VREF2, RT5670_PWR_VREF2);
msleep(100);
regmap_write(rt5670->regmap, RT5670_RESET, 0);
ret = regmap_register_patch(rt5670->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
if (rt5670->pdata.in2_diff)
regmap_update_bits(rt5670->regmap, RT5670_IN2,
RT5670_IN_DF2, RT5670_IN_DF2);
if (i2c->irq) {
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
}
if (rt5670->pdata.jd_mode) {
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
RT5670_PWR_MB, RT5670_PWR_MB);
regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2,
RT5670_PWR_JD1, RT5670_PWR_JD1);
regmap_update_bits(rt5670->regmap, RT5670_IRQ_CTRL1,
RT5670_JD1_1_EN_MASK, RT5670_JD1_1_EN);
regmap_update_bits(rt5670->regmap, RT5670_JD_CTRL3,
RT5670_JD_TRI_CBJ_SEL_MASK |
RT5670_JD_TRI_HPO_SEL_MASK,
RT5670_JD_CBJ_JD1_1 | RT5670_JD_HPO_JD1_1);
switch (rt5670->pdata.jd_mode) {
case 1:
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
RT5670_JD1_MODE_MASK,
RT5670_JD1_MODE_0);
break;
case 2:
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
RT5670_JD1_MODE_MASK,
RT5670_JD1_MODE_1);
break;
case 3:
regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
RT5670_JD1_MODE_MASK,
RT5670_JD1_MODE_2);
break;
default:
break;
}
}
if (rt5670->pdata.dmic_en) {
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP2_PIN_MASK,
RT5670_GP2_PIN_DMIC1_SCL);
switch (rt5670->pdata.dmic1_data_pin) {
case RT5670_DMIC_DATA_IN2P:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_1_DP_MASK,
RT5670_DMIC_1_DP_IN2P);
break;
case RT5670_DMIC_DATA_GPIO6:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_1_DP_MASK,
RT5670_DMIC_1_DP_GPIO6);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP6_PIN_MASK,
RT5670_GP6_PIN_DMIC1_SDA);
break;
case RT5670_DMIC_DATA_GPIO7:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_1_DP_MASK,
RT5670_DMIC_1_DP_GPIO7);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP7_PIN_MASK,
RT5670_GP7_PIN_DMIC1_SDA);
break;
default:
break;
}
switch (rt5670->pdata.dmic2_data_pin) {
case RT5670_DMIC_DATA_IN3N:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_2_DP_MASK,
RT5670_DMIC_2_DP_IN3N);
break;
case RT5670_DMIC_DATA_GPIO8:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
RT5670_DMIC_2_DP_MASK,
RT5670_DMIC_2_DP_GPIO8);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP8_PIN_MASK,
RT5670_GP8_PIN_DMIC2_SDA);
break;
default:
break;
}
switch (rt5670->pdata.dmic3_data_pin) {
case RT5670_DMIC_DATA_GPIO5:
regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL2,
RT5670_DMIC_3_DP_MASK,
RT5670_DMIC_3_DP_GPIO5);
regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
RT5670_GP5_PIN_MASK,
RT5670_GP5_PIN_DMIC3_SDA);
break;
case RT5670_DMIC_DATA_GPIO9:
case RT5670_DMIC_DATA_GPIO10:
dev_err(&i2c->dev,
"Always use GPIO5 as DMIC3 data pin\n");
break;
default:
break;
}
}
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5670,
rt5670_dai, ARRAY_SIZE(rt5670_dai));
if (ret < 0)
goto err;
return 0;
err:
return ret;
}
static int rt5670_i2c_remove(struct i2c_client *i2c)
{
snd_soc_unregister_codec(&i2c->dev);
return 0;
}
static struct i2c_driver rt5670_i2c_driver = {
.driver = {
.name = "rt5670",
.owner = THIS_MODULE,
},
.probe = rt5670_i2c_probe,
.remove = rt5670_i2c_remove,
.id_table = rt5670_i2c_id,
};
module_i2c_driver(rt5670_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5670 driver");
MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
MODULE_LICENSE("GPL v2");
sound/soc/codecs/rt5670.h 0 → 100644
View file @ c1bd940a
/*
* rt5670.h -- RT5670 ALSA SoC audio driver
*
* Copyright 2014 Realtek Microelectronics
* Author: Bard Liao <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5670_H__
#define __RT5670_H__
#include <sound/rt5670.h>
/* Info */
#define RT5670_RESET 0x00
#define RT5670_VENDOR_ID 0xfd
#define RT5670_VENDOR_ID1 0xfe
#define RT5670_VENDOR_ID2 0xff
/* I/O - Output */
#define RT5670_HP_VOL 0x02
#define RT5670_LOUT1 0x03
/* I/O - Input */
#define RT5670_CJ_CTRL1 0x0a
#define RT5670_CJ_CTRL2 0x0b
#define RT5670_CJ_CTRL3 0x0c
#define RT5670_IN2 0x0e
#define RT5670_INL1_INR1_VOL 0x0f
/* I/O - ADC/DAC/DMIC */
#define RT5670_DAC1_DIG_VOL 0x19
#define RT5670_DAC2_DIG_VOL 0x1a
#define RT5670_DAC_CTRL 0x1b
#define RT5670_STO1_ADC_DIG_VOL 0x1c
#define RT5670_MONO_ADC_DIG_VOL 0x1d
#define RT5670_ADC_BST_VOL1 0x1e
#define RT5670_STO2_ADC_DIG_VOL 0x1f
/* Mixer - D-D */
#define RT5670_ADC_BST_VOL2 0x20
#define RT5670_STO2_ADC_MIXER 0x26
#define RT5670_STO1_ADC_MIXER 0x27
#define RT5670_MONO_ADC_MIXER 0x28
#define RT5670_AD_DA_MIXER 0x29
#define RT5670_STO_DAC_MIXER 0x2a
#define RT5670_DD_MIXER 0x2b
#define RT5670_DIG_MIXER 0x2c
#define RT5670_DSP_PATH1 0x2d
#define RT5670_DSP_PATH2 0x2e
#define RT5670_DIG_INF1_DATA 0x2f
#define RT5670_DIG_INF2_DATA 0x30
/* Mixer - PDM */
#define RT5670_PDM_OUT_CTRL 0x31
#define RT5670_PDM_DATA_CTRL1 0x32
#define RT5670_PDM1_DATA_CTRL2 0x33
#define RT5670_PDM1_DATA_CTRL3 0x34
#define RT5670_PDM1_DATA_CTRL4 0x35
#define RT5670_PDM2_DATA_CTRL2 0x36
#define RT5670_PDM2_DATA_CTRL3 0x37
#define RT5670_PDM2_DATA_CTRL4 0x38
/* Mixer - ADC */
#define RT5670_REC_L1_MIXER 0x3b
#define RT5670_REC_L2_MIXER 0x3c
#define RT5670_REC_R1_MIXER 0x3d
#define RT5670_REC_R2_MIXER 0x3e
/* Mixer - DAC */
#define RT5670_HPO_MIXER 0x45
#define RT5670_MONO_MIXER 0x4c
#define RT5670_OUT_L1_MIXER 0x4f
#define RT5670_OUT_R1_MIXER 0x52
#define RT5670_LOUT_MIXER 0x53
/* Power */
#define RT5670_PWR_DIG1 0x61
#define RT5670_PWR_DIG2 0x62
#define RT5670_PWR_ANLG1 0x63
#define RT5670_PWR_ANLG2 0x64
#define RT5670_PWR_MIXER 0x65
#define RT5670_PWR_VOL 0x66
/* Private Register Control */
#define RT5670_PRIV_INDEX 0x6a
#define RT5670_PRIV_DATA 0x6c
/* Format - ADC/DAC */
#define RT5670_I2S4_SDP 0x6f
#define RT5670_I2S1_SDP 0x70
#define RT5670_I2S2_SDP 0x71
#define RT5670_I2S3_SDP 0x72
#define RT5670_ADDA_CLK1 0x73
#define RT5670_ADDA_CLK2 0x74
#define RT5670_DMIC_CTRL1 0x75
#define RT5670_DMIC_CTRL2 0x76
/* Format - TDM Control */
#define RT5670_TDM_CTRL_1 0x77
#define RT5670_TDM_CTRL_2 0x78
#define RT5670_TDM_CTRL_3 0x79
/* Function - Analog */
#define RT5670_DSP_CLK 0x7f
#define RT5670_GLB_CLK 0x80
#define RT5670_PLL_CTRL1 0x81
#define RT5670_PLL_CTRL2 0x82
#define RT5670_ASRC_1 0x83
#define RT5670_ASRC_2 0x84
#define RT5670_ASRC_3 0x85
#define RT5670_ASRC_4 0x86
#define RT5670_ASRC_5 0x87
#define RT5670_ASRC_7 0x89
#define RT5670_ASRC_8 0x8a
#define RT5670_ASRC_9 0x8b
#define RT5670_ASRC_10 0x8c
#define RT5670_ASRC_11 0x8d
#define RT5670_DEPOP_M1 0x8e
#define RT5670_DEPOP_M2 0x8f
#define RT5670_DEPOP_M3 0x90
#define RT5670_CHARGE_PUMP 0x91
#define RT5670_MICBIAS 0x93
#define RT5670_A_JD_CTRL1 0x94
#define RT5670_A_JD_CTRL2 0x95
#define RT5670_ASRC_12 0x97
#define RT5670_ASRC_13 0x98
#define RT5670_ASRC_14 0x99
#define RT5670_VAD_CTRL1 0x9a
#define RT5670_VAD_CTRL2 0x9b
#define RT5670_VAD_CTRL3 0x9c
#define RT5670_VAD_CTRL4 0x9d
#define RT5670_VAD_CTRL5 0x9e
/* Function - Digital */
#define RT5670_ADC_EQ_CTRL1 0xae
#define RT5670_ADC_EQ_CTRL2 0xaf
#define RT5670_EQ_CTRL1 0xb0
#define RT5670_EQ_CTRL2 0xb1
#define RT5670_ALC_DRC_CTRL1 0xb2
#define RT5670_ALC_DRC_CTRL2 0xb3
#define RT5670_ALC_CTRL_1 0xb4
#define RT5670_ALC_CTRL_2 0xb5
#define RT5670_ALC_CTRL_3 0xb6
#define RT5670_ALC_CTRL_4 0xb7
#define RT5670_JD_CTRL 0xbb
#define RT5670_IRQ_CTRL1 0xbd
#define RT5670_IRQ_CTRL2 0xbe
#define RT5670_INT_IRQ_ST 0xbf
#define RT5670_GPIO_CTRL1 0xc0
#define RT5670_GPIO_CTRL2 0xc1
#define RT5670_GPIO_CTRL3 0xc2
#define RT5670_SCRABBLE_FUN 0xcd
#define RT5670_SCRABBLE_CTRL 0xce
#define RT5670_BASE_BACK 0xcf
#define RT5670_MP3_PLUS1 0xd0
#define RT5670_MP3_PLUS2 0xd1
#define RT5670_ADJ_HPF1 0xd3
#define RT5670_ADJ_HPF2 0xd4
#define RT5670_HP_CALIB_AMP_DET 0xd6
#define RT5670_SV_ZCD1 0xd9
#define RT5670_SV_ZCD2 0xda
#define RT5670_IL_CMD 0xdb
#define RT5670_IL_CMD2 0xdc
#define RT5670_IL_CMD3 0xdd
#define RT5670_DRC_HL_CTRL1 0xe6
#define RT5670_DRC_HL_CTRL2 0xe7
#define RT5670_ADC_MONO_HP_CTRL1 0xec
#define RT5670_ADC_MONO_HP_CTRL2 0xed
#define RT5670_ADC_STO2_HP_CTRL1 0xee
#define RT5670_ADC_STO2_HP_CTRL2 0xef
#define RT5670_JD_CTRL3 0xf8
#define RT5670_JD_CTRL4 0xf9
/* General Control */
#define RT5670_DIG_MISC 0xfa
#define RT5670_GEN_CTRL2 0xfb
#define RT5670_GEN_CTRL3 0xfc
/* Index of Codec Private Register definition */
#define RT5670_DIG_VOL 0x00
#define RT5670_PR_ALC_CTRL_1 0x01
#define RT5670_PR_ALC_CTRL_2 0x02
#define RT5670_PR_ALC_CTRL_3 0x03
#define RT5670_PR_ALC_CTRL_4 0x04
#define RT5670_PR_ALC_CTRL_5 0x05
#define RT5670_PR_ALC_CTRL_6 0x06
#define RT5670_BIAS_CUR1 0x12
#define RT5670_BIAS_CUR3 0x14
#define RT5670_CLSD_INT_REG1 0x1c
#define RT5670_MAMP_INT_REG2 0x37
#define RT5670_CHOP_DAC_ADC 0x3d
#define RT5670_MIXER_INT_REG 0x3f
#define RT5670_3D_SPK 0x63
#define RT5670_WND_1 0x6c
#define RT5670_WND_2 0x6d
#define RT5670_WND_3 0x6e
#define RT5670_WND_4 0x6f
#define RT5670_WND_5 0x70
#define RT5670_WND_8 0x73
#define RT5670_DIP_SPK_INF 0x75
#define RT5670_HP_DCC_INT1 0x77
#define RT5670_EQ_BW_LOP 0xa0
#define RT5670_EQ_GN_LOP 0xa1
#define RT5670_EQ_FC_BP1 0xa2
#define RT5670_EQ_BW_BP1 0xa3
#define RT5670_EQ_GN_BP1 0xa4
#define RT5670_EQ_FC_BP2 0xa5
#define RT5670_EQ_BW_BP2 0xa6
#define RT5670_EQ_GN_BP2 0xa7
#define RT5670_EQ_FC_BP3 0xa8
#define RT5670_EQ_BW_BP3 0xa9
#define RT5670_EQ_GN_BP3 0xaa
#define RT5670_EQ_FC_BP4 0xab
#define RT5670_EQ_BW_BP4 0xac
#define RT5670_EQ_GN_BP4 0xad
#define RT5670_EQ_FC_HIP1 0xae
#define RT5670_EQ_GN_HIP1 0xaf
#define RT5670_EQ_FC_HIP2 0xb0
#define RT5670_EQ_BW_HIP2 0xb1
#define RT5670_EQ_GN_HIP2 0xb2
#define RT5670_EQ_PRE_VOL 0xb3
#define RT5670_EQ_PST_VOL 0xb4
/* global definition */
#define RT5670_L_MUTE (0x1 << 15)
#define RT5670_L_MUTE_SFT 15
#define RT5670_VOL_L_MUTE (0x1 << 14)
#define RT5670_VOL_L_SFT 14
#define RT5670_R_MUTE (0x1 << 7)
#define RT5670_R_MUTE_SFT 7
#define RT5670_VOL_R_MUTE (0x1 << 6)
#define RT5670_VOL_R_SFT 6
#define RT5670_L_VOL_MASK (0x3f << 8)
#define RT5670_L_VOL_SFT 8
#define RT5670_R_VOL_MASK (0x3f)
#define RT5670_R_VOL_SFT 0
/* Combo Jack Control 1 (0x0a) */
#define RT5670_CBJ_BST1_MASK (0xf << 12)
#define RT5670_CBJ_BST1_SFT (12)
#define RT5670_CBJ_JD_HP_EN (0x1 << 9)
#define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
#define RT5670_CBJ_BST1_EN (0x1 << 2)
/* Combo Jack Control 1 (0x0b) */
#define RT5670_CBJ_MN_JD (0x1 << 12)
#define RT5670_CAPLESS_EN (0x1 << 11)
#define RT5670_CBJ_DET_MODE (0x1 << 7)
/* IN2 Control (0x0e) */
#define RT5670_BST_MASK1 (0xf<<12)
#define RT5670_BST_SFT1 12
#define RT5670_BST_MASK2 (0xf<<8)
#define RT5670_BST_SFT2 8
#define RT5670_IN_DF1 (0x1 << 7)
#define RT5670_IN_SFT1 7
#define RT5670_IN_DF2 (0x1 << 6)
#define RT5670_IN_SFT2 6
/* INL and INR Volume Control (0x0f) */
#define RT5670_INL_SEL_MASK (0x1 << 15)
#define RT5670_INL_SEL_SFT 15
#define RT5670_INL_SEL_IN4P (0x0 << 15)
#define RT5670_INL_SEL_MONOP (0x1 << 15)
#define RT5670_INL_VOL_MASK (0x1f << 8)
#define RT5670_INL_VOL_SFT 8
#define RT5670_INR_SEL_MASK (0x1 << 7)
#define RT5670_INR_SEL_SFT 7
#define RT5670_INR_SEL_IN4N (0x0 << 7)
#define RT5670_INR_SEL_MONON (0x1 << 7)
#define RT5670_INR_VOL_MASK (0x1f)
#define RT5670_INR_VOL_SFT 0
/* Sidetone Control (0x18) */
#define RT5670_ST_SEL_MASK (0x7 << 9)
#define RT5670_ST_SEL_SFT 9
#define RT5670_M_ST_DACR2 (0x1 << 8)
#define RT5670_M_ST_DACR2_SFT 8
#define RT5670_M_ST_DACL2 (0x1 << 7)
#define RT5670_M_ST_DACL2_SFT 7
#define RT5670_ST_EN (0x1 << 6)
#define RT5670_ST_EN_SFT 6
/* DAC1 Digital Volume (0x19) */
#define RT5670_DAC_L1_VOL_MASK (0xff << 8)
#define RT5670_DAC_L1_VOL_SFT 8
#define RT5670_DAC_R1_VOL_MASK (0xff)
#define RT5670_DAC_R1_VOL_SFT 0
/* DAC2 Digital Volume (0x1a) */
#define RT5670_DAC_L2_VOL_MASK (0xff << 8)
#define RT5670_DAC_L2_VOL_SFT 8
#define RT5670_DAC_R2_VOL_MASK (0xff)
#define RT5670_DAC_R2_VOL_SFT 0
/* DAC2 Control (0x1b) */
#define RT5670_M_DAC_L2_VOL (0x1 << 13)
#define RT5670_M_DAC_L2_VOL_SFT 13
#define RT5670_M_DAC_R2_VOL (0x1 << 12)
#define RT5670_M_DAC_R2_VOL_SFT 12
#define RT5670_DAC2_L_SEL_MASK (0x7 << 4)
#define RT5670_DAC2_L_SEL_SFT 4
#define RT5670_DAC2_R_SEL_MASK (0x7 << 0)
#define RT5670_DAC2_R_SEL_SFT 0
/* ADC Digital Volume Control (0x1c) */
#define RT5670_ADC_L_VOL_MASK (0x7f << 8)
#define RT5670_ADC_L_VOL_SFT 8
#define RT5670_ADC_R_VOL_MASK (0x7f)
#define RT5670_ADC_R_VOL_SFT 0
/* Mono ADC Digital Volume Control (0x1d) */
#define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
#define RT5670_MONO_ADC_L_VOL_SFT 8
#define RT5670_MONO_ADC_R_VOL_MASK (0x7f)
#define RT5670_MONO_ADC_R_VOL_SFT 0
/* ADC Boost Volume Control (0x1e) */
#define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
#define RT5670_STO1_ADC_L_BST_SFT 14
#define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
#define RT5670_STO1_ADC_R_BST_SFT 12
#define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
#define RT5670_STO1_ADC_COMP_SFT 10
#define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
#define RT5670_STO2_ADC_L_BST_SFT 8
#define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6)
#define RT5670_STO2_ADC_R_BST_SFT 6
#define RT5670_STO2_ADC_COMP_MASK (0x3 << 4)
#define RT5670_STO2_ADC_COMP_SFT 4
/* Stereo2 ADC Mixer Control (0x26) */
#define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
#define RT5670_STO2_ADC_SRC_SFT 15
/* Stereo ADC Mixer Control (0x26 0x27) */
#define RT5670_M_ADC_L1 (0x1 << 14)
#define RT5670_M_ADC_L1_SFT 14
#define RT5670_M_ADC_L2 (0x1 << 13)
#define RT5670_M_ADC_L2_SFT 13
#define RT5670_ADC_1_SRC_MASK (0x1 << 12)
#define RT5670_ADC_1_SRC_SFT 12
#define RT5670_ADC_1_SRC_ADC (0x1 << 12)
#define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
#define RT5670_ADC_2_SRC_MASK (0x1 << 11)
#define RT5670_ADC_2_SRC_SFT 11
#define RT5670_ADC_SRC_MASK (0x1 << 10)
#define RT5670_ADC_SRC_SFT 10
#define RT5670_DMIC_SRC_MASK (0x3 << 8)
#define RT5670_DMIC_SRC_SFT 8
#define RT5670_M_ADC_R1 (0x1 << 6)
#define RT5670_M_ADC_R1_SFT 6
#define RT5670_M_ADC_R2 (0x1 << 5)
#define RT5670_M_ADC_R2_SFT 5
#define RT5670_DMIC3_SRC_MASK (0x1 << 1)
#define RT5670_DMIC3_SRC_SFT 0
/* Mono ADC Mixer Control (0x28) */
#define RT5670_M_MONO_ADC_L1 (0x1 << 14)
#define RT5670_M_MONO_ADC_L1_SFT 14
#define RT5670_M_MONO_ADC_L2 (0x1 << 13)
#define RT5670_M_MONO_ADC_L2_SFT 13
#define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
#define RT5670_MONO_ADC_L1_SRC_SFT 12
#define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
#define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
#define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
#define RT5670_MONO_ADC_L2_SRC_SFT 11
#define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
#define RT5670_MONO_ADC_L_SRC_SFT 10
#define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
#define RT5670_MONO_DMIC_L_SRC_SFT 8
#define RT5670_M_MONO_ADC_R1 (0x1 << 6)
#define RT5670_M_MONO_ADC_R1_SFT 6
#define RT5670_M_MONO_ADC_R2 (0x1 << 5)
#define RT5670_M_MONO_ADC_R2_SFT 5
#define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
#define RT5670_MONO_ADC_R1_SRC_SFT 4
#define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
#define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
#define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
#define RT5670_MONO_ADC_R2_SRC_SFT 3
#define RT5670_MONO_DMIC_R_SRC_MASK (0x3)
#define RT5670_MONO_DMIC_R_SRC_SFT 0
/* ADC Mixer to DAC Mixer Control (0x29) */
#define RT5670_M_ADCMIX_L (0x1 << 15)
#define RT5670_M_ADCMIX_L_SFT 15
#define RT5670_M_DAC1_L (0x1 << 14)
#define RT5670_M_DAC1_L_SFT 14
#define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
#define RT5670_DAC1_R_SEL_SFT 10
#define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
#define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
#define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
#define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
#define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
#define RT5670_DAC1_L_SEL_SFT 8
#define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
#define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
#define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
#define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
#define RT5670_M_ADCMIX_R (0x1 << 7)
#define RT5670_M_ADCMIX_R_SFT 7
#define RT5670_M_DAC1_R (0x1 << 6)
#define RT5670_M_DAC1_R_SFT 6
/* Stereo DAC Mixer Control (0x2a) */
#define RT5670_M_DAC_L1 (0x1 << 14)
#define RT5670_M_DAC_L1_SFT 14
#define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
#define RT5670_DAC_L1_STO_L_VOL_SFT 13
#define RT5670_M_DAC_L2 (0x1 << 12)
#define RT5670_M_DAC_L2_SFT 12
#define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
#define RT5670_DAC_L2_STO_L_VOL_SFT 11
#define RT5670_M_DAC_R1_STO_L (0x1 << 9)
#define RT5670_M_DAC_R1_STO_L_SFT 9
#define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
#define RT5670_DAC_R1_STO_L_VOL_SFT 8
#define RT5670_M_DAC_R1 (0x1 << 6)
#define RT5670_M_DAC_R1_SFT 6
#define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
#define RT5670_DAC_R1_STO_R_VOL_SFT 5
#define RT5670_M_DAC_R2 (0x1 << 4)
#define RT5670_M_DAC_R2_SFT 4
#define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
#define RT5670_DAC_R2_STO_R_VOL_SFT 3
#define RT5670_M_DAC_L1_STO_R (0x1 << 1)
#define RT5670_M_DAC_L1_STO_R_SFT 1
#define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
#define RT5670_DAC_L1_STO_R_VOL_SFT 0
/* Mono DAC Mixer Control (0x2b) */
#define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
#define RT5670_M_DAC_L1_MONO_L_SFT 14
#define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
#define RT5670_DAC_L1_MONO_L_VOL_SFT 13
#define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
#define RT5670_M_DAC_L2_MONO_L_SFT 12
#define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
#define RT5670_DAC_L2_MONO_L_VOL_SFT 11
#define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
#define RT5670_M_DAC_R2_MONO_L_SFT 10
#define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
#define RT5670_DAC_R2_MONO_L_VOL_SFT 9
#define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
#define RT5670_M_DAC_R1_MONO_R_SFT 6
#define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
#define RT5670_DAC_R1_MONO_R_VOL_SFT 5
#define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
#define RT5670_M_DAC_R2_MONO_R_SFT 4
#define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
#define RT5670_DAC_R2_MONO_R_VOL_SFT 3
#define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
#define RT5670_M_DAC_L2_MONO_R_SFT 2
#define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
#define RT5670_DAC_L2_MONO_R_VOL_SFT 1
/* Digital Mixer Control (0x2c) */
#define RT5670_M_STO_L_DAC_L (0x1 << 15)
#define RT5670_M_STO_L_DAC_L_SFT 15
#define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
#define RT5670_STO_L_DAC_L_VOL_SFT 14
#define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
#define RT5670_M_DAC_L2_DAC_L_SFT 13
#define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
#define RT5670_DAC_L2_DAC_L_VOL_SFT 12
#define RT5670_M_STO_R_DAC_R (0x1 << 11)
#define RT5670_M_STO_R_DAC_R_SFT 11
#define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
#define RT5670_STO_R_DAC_R_VOL_SFT 10
#define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
#define RT5670_M_DAC_R2_DAC_R_SFT 9
#define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
#define RT5670_DAC_R2_DAC_R_VOL_SFT 8
#define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
#define RT5670_M_DAC_R2_DAC_L_SFT 7
#define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
#define RT5670_DAC_R2_DAC_L_VOL_SFT 6
#define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
#define RT5670_M_DAC_L2_DAC_R_SFT 5
#define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
#define RT5670_DAC_L2_DAC_R_VOL_SFT 4
/* DSP Path Control 1 (0x2d) */
#define RT5670_RXDP_SEL_MASK (0x7 << 13)
#define RT5670_RXDP_SEL_SFT 13
#define RT5670_RXDP_SRC_MASK (0x3 << 11)
#define RT5670_RXDP_SRC_SFT 11
#define RT5670_RXDP_SRC_NOR (0x0 << 11)
#define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
#define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
#define RT5670_TXDP_SRC_MASK (0x3 << 4)
#define RT5670_TXDP_SRC_SFT 4
#define RT5670_TXDP_SRC_NOR (0x0 << 4)
#define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
#define RT5670_TXDP_SRC_DIV3 (0x2 << 4)
#define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2)
#define RT5670_TXDP_SLOT_SEL_SFT 2
#define RT5670_DSP_UL_SEL (0x1 << 1)
#define RT5670_DSP_UL_SFT 1
#define RT5670_DSP_DL_SEL 0x1
#define RT5670_DSP_DL_SFT 0
/* DSP Path Control 2 (0x2e) */
#define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
#define RT5670_TXDP_L_VOL_SFT 8
#define RT5670_TXDP_R_VOL_MASK (0x7f)
#define RT5670_TXDP_R_VOL_SFT 0
/* Digital Interface Data Control (0x2f) */
#define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
#define RT5670_IF1_ADC2_IN_SFT 15
#define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
#define RT5670_IF2_ADC_IN_SFT 12
#define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
#define RT5670_IF2_DAC_SEL_SFT 10
#define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
#define RT5670_IF2_ADC_SEL_SFT 8
/* Digital Interface Data Control (0x30) */
#define RT5670_IF4_ADC_IN_MASK (0x3 << 4)
#define RT5670_IF4_ADC_IN_SFT 4
/* PDM Output Control (0x31) */
#define RT5670_PDM1_L_MASK (0x1 << 15)
#define RT5670_PDM1_L_SFT 15
#define RT5670_M_PDM1_L (0x1 << 14)
#define RT5670_M_PDM1_L_SFT 14
#define RT5670_PDM1_R_MASK (0x1 << 13)
#define RT5670_PDM1_R_SFT 13
#define RT5670_M_PDM1_R (0x1 << 12)
#define RT5670_M_PDM1_R_SFT 12
#define RT5670_PDM2_L_MASK (0x1 << 11)
#define RT5670_PDM2_L_SFT 11
#define RT5670_M_PDM2_L (0x1 << 10)
#define RT5670_M_PDM2_L_SFT 10
#define RT5670_PDM2_R_MASK (0x1 << 9)
#define RT5670_PDM2_R_SFT 9
#define RT5670_M_PDM2_R (0x1 << 8)
#define RT5670_M_PDM2_R_SFT 8
#define RT5670_PDM2_BUSY (0x1 << 7)
#define RT5670_PDM1_BUSY (0x1 << 6)
#define RT5670_PDM_PATTERN (0x1 << 5)
#define RT5670_PDM_GAIN (0x1 << 4)
#define RT5670_PDM_DIV_MASK (0x3)
/* REC Left Mixer Control 1 (0x3b) */
#define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
#define RT5670_G_HP_L_RM_L_SFT 13
#define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
#define RT5670_G_IN_L_RM_L_SFT 10
#define RT5670_G_BST4_RM_L_MASK (0x7 << 7)
#define RT5670_G_BST4_RM_L_SFT 7
#define RT5670_G_BST3_RM_L_MASK (0x7 << 4)
#define RT5670_G_BST3_RM_L_SFT 4
#define RT5670_G_BST2_RM_L_MASK (0x7 << 1)
#define RT5670_G_BST2_RM_L_SFT 1
/* REC Left Mixer Control 2 (0x3c) */
#define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
#define RT5670_G_BST1_RM_L_SFT 13
#define RT5670_M_IN_L_RM_L (0x1 << 5)
#define RT5670_M_IN_L_RM_L_SFT 5
#define RT5670_M_BST2_RM_L (0x1 << 3)
#define RT5670_M_BST2_RM_L_SFT 3
#define RT5670_M_BST1_RM_L (0x1 << 1)
#define RT5670_M_BST1_RM_L_SFT 1
/* REC Right Mixer Control 1 (0x3d) */
#define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
#define RT5670_G_HP_R_RM_R_SFT 13
#define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
#define RT5670_G_IN_R_RM_R_SFT 10
#define RT5670_G_BST4_RM_R_MASK (0x7 << 7)
#define RT5670_G_BST4_RM_R_SFT 7
#define RT5670_G_BST3_RM_R_MASK (0x7 << 4)
#define RT5670_G_BST3_RM_R_SFT 4
#define RT5670_G_BST2_RM_R_MASK (0x7 << 1)
#define RT5670_G_BST2_RM_R_SFT 1
/* REC Right Mixer Control 2 (0x3e) */
#define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
#define RT5670_G_BST1_RM_R_SFT 13
#define RT5670_M_IN_R_RM_R (0x1 << 5)
#define RT5670_M_IN_R_RM_R_SFT 5
#define RT5670_M_BST2_RM_R (0x1 << 3)
#define RT5670_M_BST2_RM_R_SFT 3
#define RT5670_M_BST1_RM_R (0x1 << 1)
#define RT5670_M_BST1_RM_R_SFT 1
/* HPMIX Control (0x45) */
#define RT5670_M_DAC2_HM (0x1 << 15)
#define RT5670_M_DAC2_HM_SFT 15
#define RT5670_M_HPVOL_HM (0x1 << 14)
#define RT5670_M_HPVOL_HM_SFT 14
#define RT5670_M_DAC1_HM (0x1 << 13)
#define RT5670_M_DAC1_HM_SFT 13
#define RT5670_G_HPOMIX_MASK (0x1 << 12)
#define RT5670_G_HPOMIX_SFT 12
#define RT5670_M_INR1_HMR (0x1 << 3)
#define RT5670_M_INR1_HMR_SFT 3
#define RT5670_M_DACR1_HMR (0x1 << 2)
#define RT5670_M_DACR1_HMR_SFT 2
#define RT5670_M_INL1_HML (0x1 << 1)
#define RT5670_M_INL1_HML_SFT 1
#define RT5670_M_DACL1_HML (0x1)
#define RT5670_M_DACL1_HML_SFT 0
/* Mono Output Mixer Control (0x4c) */
#define RT5670_M_DAC_R2_MA (0x1 << 15)
#define RT5670_M_DAC_R2_MA_SFT 15
#define RT5670_M_DAC_L2_MA (0x1 << 14)
#define RT5670_M_DAC_L2_MA_SFT 14
#define RT5670_M_OV_R_MM (0x1 << 13)
#define RT5670_M_OV_R_MM_SFT 13
#define RT5670_M_OV_L_MM (0x1 << 12)
#define RT5670_M_OV_L_MM_SFT 12
#define RT5670_G_MONOMIX_MASK (0x1 << 10)
#define RT5670_G_MONOMIX_SFT 10
#define RT5670_M_DAC_R2_MM (0x1 << 9)
#define RT5670_M_DAC_R2_MM_SFT 9
#define RT5670_M_DAC_L2_MM (0x1 << 8)
#define RT5670_M_DAC_L2_MM_SFT 8
#define RT5670_M_BST4_MM (0x1 << 7)
#define RT5670_M_BST4_MM_SFT 7
/* Output Left Mixer Control 1 (0x4d) */
#define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
#define RT5670_G_BST3_OM_L_SFT 13
#define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
#define RT5670_G_BST2_OM_L_SFT 10
#define RT5670_G_BST1_OM_L_MASK (0x7 << 7)
#define RT5670_G_BST1_OM_L_SFT 7
#define RT5670_G_IN_L_OM_L_MASK (0x7 << 4)
#define RT5670_G_IN_L_OM_L_SFT 4
#define RT5670_G_RM_L_OM_L_MASK (0x7 << 1)
#define RT5670_G_RM_L_OM_L_SFT 1
/* Output Left Mixer Control 2 (0x4e) */
#define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
#define RT5670_G_DAC_R2_OM_L_SFT 13
#define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
#define RT5670_G_DAC_L2_OM_L_SFT 10
#define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7)
#define RT5670_G_DAC_L1_OM_L_SFT 7
/* Output Left Mixer Control 3 (0x4f) */
#define RT5670_M_BST1_OM_L (0x1 << 5)
#define RT5670_M_BST1_OM_L_SFT 5
#define RT5670_M_IN_L_OM_L (0x1 << 4)
#define RT5670_M_IN_L_OM_L_SFT 4
#define RT5670_M_DAC_L2_OM_L (0x1 << 1)
#define RT5670_M_DAC_L2_OM_L_SFT 1
#define RT5670_M_DAC_L1_OM_L (0x1)
#define RT5670_M_DAC_L1_OM_L_SFT 0
/* Output Right Mixer Control 1 (0x50) */
#define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
#define RT5670_G_BST4_OM_R_SFT 13
#define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
#define RT5670_G_BST2_OM_R_SFT 10
#define RT5670_G_BST1_OM_R_MASK (0x7 << 7)
#define RT5670_G_BST1_OM_R_SFT 7
#define RT5670_G_IN_R_OM_R_MASK (0x7 << 4)
#define RT5670_G_IN_R_OM_R_SFT 4
#define RT5670_G_RM_R_OM_R_MASK (0x7 << 1)
#define RT5670_G_RM_R_OM_R_SFT 1
/* Output Right Mixer Control 2 (0x51) */
#define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
#define RT5670_G_DAC_L2_OM_R_SFT 13
#define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
#define RT5670_G_DAC_R2_OM_R_SFT 10
#define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7)
#define RT5670_G_DAC_R1_OM_R_SFT 7
/* Output Right Mixer Control 3 (0x52) */
#define RT5670_M_BST2_OM_R (0x1 << 6)
#define RT5670_M_BST2_OM_R_SFT 6
#define RT5670_M_IN_R_OM_R (0x1 << 4)
#define RT5670_M_IN_R_OM_R_SFT 4
#define RT5670_M_DAC_R2_OM_R (0x1 << 1)
#define RT5670_M_DAC_R2_OM_R_SFT 1
#define RT5670_M_DAC_R1_OM_R (0x1)
#define RT5670_M_DAC_R1_OM_R_SFT 0
/* LOUT Mixer Control (0x53) */
#define RT5670_M_DAC_L1_LM (0x1 << 15)
#define RT5670_M_DAC_L1_LM_SFT 15
#define RT5670_M_DAC_R1_LM (0x1 << 14)
#define RT5670_M_DAC_R1_LM_SFT 14
#define RT5670_M_OV_L_LM (0x1 << 13)
#define RT5670_M_OV_L_LM_SFT 13
#define RT5670_M_OV_R_LM (0x1 << 12)
#define RT5670_M_OV_R_LM_SFT 12
#define RT5670_G_LOUTMIX_MASK (0x1 << 11)
#define RT5670_G_LOUTMIX_SFT 11
/* Power Management for Digital 1 (0x61) */
#define RT5670_PWR_I2S1 (0x1 << 15)
#define RT5670_PWR_I2S1_BIT 15
#define RT5670_PWR_I2S2 (0x1 << 14)
#define RT5670_PWR_I2S2_BIT 14
#define RT5670_PWR_DAC_L1 (0x1 << 12)
#define RT5670_PWR_DAC_L1_BIT 12
#define RT5670_PWR_DAC_R1 (0x1 << 11)
#define RT5670_PWR_DAC_R1_BIT 11
#define RT5670_PWR_DAC_L2 (0x1 << 7)
#define RT5670_PWR_DAC_L2_BIT 7
#define RT5670_PWR_DAC_R2 (0x1 << 6)
#define RT5670_PWR_DAC_R2_BIT 6
#define RT5670_PWR_ADC_L (0x1 << 2)
#define RT5670_PWR_ADC_L_BIT 2
#define RT5670_PWR_ADC_R (0x1 << 1)
#define RT5670_PWR_ADC_R_BIT 1
#define RT5670_PWR_CLS_D (0x1)
#define RT5670_PWR_CLS_D_BIT 0
/* Power Management for Digital 2 (0x62) */
#define RT5670_PWR_ADC_S1F (0x1 << 15)
#define RT5670_PWR_ADC_S1F_BIT 15
#define RT5670_PWR_ADC_MF_L (0x1 << 14)
#define RT5670_PWR_ADC_MF_L_BIT 14
#define RT5670_PWR_ADC_MF_R (0x1 << 13)
#define RT5670_PWR_ADC_MF_R_BIT 13
#define RT5670_PWR_I2S_DSP (0x1 << 12)
#define RT5670_PWR_I2S_DSP_BIT 12
#define RT5670_PWR_DAC_S1F (0x1 << 11)
#define RT5670_PWR_DAC_S1F_BIT 11
#define RT5670_PWR_DAC_MF_L (0x1 << 10)
#define RT5670_PWR_DAC_MF_L_BIT 10
#define RT5670_PWR_DAC_MF_R (0x1 << 9)
#define RT5670_PWR_DAC_MF_R_BIT 9
#define RT5670_PWR_ADC_S2F (0x1 << 8)
#define RT5670_PWR_ADC_S2F_BIT 8
#define RT5670_PWR_PDM1 (0x1 << 7)
#define RT5670_PWR_PDM1_BIT 7
#define RT5670_PWR_PDM2 (0x1 << 6)
#define RT5670_PWR_PDM2_BIT 6
/* Power Management for Analog 1 (0x63) */
#define RT5670_PWR_VREF1 (0x1 << 15)
#define RT5670_PWR_VREF1_BIT 15
#define RT5670_PWR_FV1 (0x1 << 14)
#define RT5670_PWR_FV1_BIT 14
#define RT5670_PWR_MB (0x1 << 13)
#define RT5670_PWR_MB_BIT 13
#define RT5670_PWR_LM (0x1 << 12)
#define RT5670_PWR_LM_BIT 12
#define RT5670_PWR_BG (0x1 << 11)
#define RT5670_PWR_BG_BIT 11
#define RT5670_PWR_HP_L (0x1 << 7)
#define RT5670_PWR_HP_L_BIT 7
#define RT5670_PWR_HP_R (0x1 << 6)
#define RT5670_PWR_HP_R_BIT 6
#define RT5670_PWR_HA (0x1 << 5)
#define RT5670_PWR_HA_BIT 5
#define RT5670_PWR_VREF2 (0x1 << 4)
#define RT5670_PWR_VREF2_BIT 4
#define RT5670_PWR_FV2 (0x1 << 3)
#define RT5670_PWR_FV2_BIT 3
#define RT5670_LDO_SEL_MASK (0x3)
#define RT5670_LDO_SEL_SFT 0
/* Power Management for Analog 2 (0x64) */
#define RT5670_PWR_BST1 (0x1 << 15)
#define RT5670_PWR_BST1_BIT 15
#define RT5670_PWR_BST2 (0x1 << 13)
#define RT5670_PWR_BST2_BIT 13
#define RT5670_PWR_MB1 (0x1 << 11)
#define RT5670_PWR_MB1_BIT 11
#define RT5670_PWR_MB2 (0x1 << 10)
#define RT5670_PWR_MB2_BIT 10
#define RT5670_PWR_PLL (0x1 << 9)
#define RT5670_PWR_PLL_BIT 9
#define RT5670_PWR_BST1_P (0x1 << 6)
#define RT5670_PWR_BST1_P_BIT 6
#define RT5670_PWR_BST2_P (0x1 << 4)
#define RT5670_PWR_BST2_P_BIT 4
#define RT5670_PWR_JD1 (0x1 << 2)
#define RT5670_PWR_JD1_BIT 2
#define RT5670_PWR_JD (0x1 << 1)
#define RT5670_PWR_JD_BIT 1
/* Power Management for Mixer (0x65) */
#define RT5670_PWR_OM_L (0x1 << 15)
#define RT5670_PWR_OM_L_BIT 15
#define RT5670_PWR_OM_R (0x1 << 14)
#define RT5670_PWR_OM_R_BIT 14
#define RT5670_PWR_RM_L (0x1 << 11)
#define RT5670_PWR_RM_L_BIT 11
#define RT5670_PWR_RM_R (0x1 << 10)
#define RT5670_PWR_RM_R_BIT 10
/* Power Management for Volume (0x66) */
#define RT5670_PWR_HV_L (0x1 << 11)
#define RT5670_PWR_HV_L_BIT 11
#define RT5670_PWR_HV_R (0x1 << 10)
#define RT5670_PWR_HV_R_BIT 10
#define RT5670_PWR_IN_L (0x1 << 9)
#define RT5670_PWR_IN_L_BIT 9
#define RT5670_PWR_IN_R (0x1 << 8)
#define RT5670_PWR_IN_R_BIT 8
#define RT5670_PWR_MIC_DET (0x1 << 5)
#define RT5670_PWR_MIC_DET_BIT 5
/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
#define RT5670_I2S_MS_MASK (0x1 << 15)
#define RT5670_I2S_MS_SFT 15
#define RT5670_I2S_MS_M (0x0 << 15)
#define RT5670_I2S_MS_S (0x1 << 15)
#define RT5670_I2S_IF_MASK (0x7 << 12)
#define RT5670_I2S_IF_SFT 12
#define RT5670_I2S_O_CP_MASK (0x3 << 10)
#define RT5670_I2S_O_CP_SFT 10
#define RT5670_I2S_O_CP_OFF (0x0 << 10)
#define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
#define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
#define RT5670_I2S_I_CP_MASK (0x3 << 8)
#define RT5670_I2S_I_CP_SFT 8
#define RT5670_I2S_I_CP_OFF (0x0 << 8)
#define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
#define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
#define RT5670_I2S_BP_MASK (0x1 << 7)
#define RT5670_I2S_BP_SFT 7
#define RT5670_I2S_BP_NOR (0x0 << 7)
#define RT5670_I2S_BP_INV (0x1 << 7)
#define RT5670_I2S_DL_MASK (0x3 << 2)
#define RT5670_I2S_DL_SFT 2
#define RT5670_I2S_DL_16 (0x0 << 2)
#define RT5670_I2S_DL_20 (0x1 << 2)
#define RT5670_I2S_DL_24 (0x2 << 2)
#define RT5670_I2S_DL_8 (0x3 << 2)
#define RT5670_I2S_DF_MASK (0x3)
#define RT5670_I2S_DF_SFT 0
#define RT5670_I2S_DF_I2S (0x0)
#define RT5670_I2S_DF_LEFT (0x1)
#define RT5670_I2S_DF_PCM_A (0x2)
#define RT5670_I2S_DF_PCM_B (0x3)
/* I2S2 Audio Serial Data Port Control (0x71) */
#define RT5670_I2S2_SDI_MASK (0x1 << 6)
#define RT5670_I2S2_SDI_SFT 6
#define RT5670_I2S2_SDI_I2S1 (0x0 << 6)
#define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
/* ADC/DAC Clock Control 1 (0x73) */
#define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
#define RT5670_I2S_BCLK_MS1_SFT 15
#define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
#define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
#define RT5670_I2S_PD1_MASK (0x7 << 12)
#define RT5670_I2S_PD1_SFT 12
#define RT5670_I2S_PD1_1 (0x0 << 12)
#define RT5670_I2S_PD1_2 (0x1 << 12)
#define RT5670_I2S_PD1_3 (0x2 << 12)
#define RT5670_I2S_PD1_4 (0x3 << 12)
#define RT5670_I2S_PD1_6 (0x4 << 12)
#define RT5670_I2S_PD1_8 (0x5 << 12)
#define RT5670_I2S_PD1_12 (0x6 << 12)
#define RT5670_I2S_PD1_16 (0x7 << 12)
#define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
#define RT5670_I2S_BCLK_MS2_SFT 11
#define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
#define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
#define RT5670_I2S_PD2_MASK (0x7 << 8)
#define RT5670_I2S_PD2_SFT 8
#define RT5670_I2S_PD2_1 (0x0 << 8)
#define RT5670_I2S_PD2_2 (0x1 << 8)
#define RT5670_I2S_PD2_3 (0x2 << 8)
#define RT5670_I2S_PD2_4 (0x3 << 8)
#define RT5670_I2S_PD2_6 (0x4 << 8)
#define RT5670_I2S_PD2_8 (0x5 << 8)
#define RT5670_I2S_PD2_12 (0x6 << 8)
#define RT5670_I2S_PD2_16 (0x7 << 8)
#define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
#define RT5670_I2S_BCLK_MS3_SFT 7
#define RT5670_I2S_BCLK_MS3_32 (0x0 << 7)
#define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
#define RT5670_I2S_PD3_MASK (0x7 << 4)
#define RT5670_I2S_PD3_SFT 4
#define RT5670_I2S_PD3_1 (0x0 << 4)
#define RT5670_I2S_PD3_2 (0x1 << 4)
#define RT5670_I2S_PD3_3 (0x2 << 4)
#define RT5670_I2S_PD3_4 (0x3 << 4)
#define RT5670_I2S_PD3_6 (0x4 << 4)
#define RT5670_I2S_PD3_8 (0x5 << 4)
#define RT5670_I2S_PD3_12 (0x6 << 4)
#define RT5670_I2S_PD3_16 (0x7 << 4)
#define RT5670_DAC_OSR_MASK (0x3 << 2)
#define RT5670_DAC_OSR_SFT 2
#define RT5670_DAC_OSR_128 (0x0 << 2)
#define RT5670_DAC_OSR_64 (0x1 << 2)
#define RT5670_DAC_OSR_32 (0x2 << 2)
#define RT5670_DAC_OSR_16 (0x3 << 2)
#define RT5670_ADC_OSR_MASK (0x3)
#define RT5670_ADC_OSR_SFT 0
#define RT5670_ADC_OSR_128 (0x0)
#define RT5670_ADC_OSR_64 (0x1)
#define RT5670_ADC_OSR_32 (0x2)
#define RT5670_ADC_OSR_16 (0x3)
/* ADC/DAC Clock Control 2 (0x74) */
#define RT5670_DAC_L_OSR_MASK (0x3 << 14)
#define RT5670_DAC_L_OSR_SFT 14
#define RT5670_DAC_L_OSR_128 (0x0 << 14)
#define RT5670_DAC_L_OSR_64 (0x1 << 14)
#define RT5670_DAC_L_OSR_32 (0x2 << 14)
#define RT5670_DAC_L_OSR_16 (0x3 << 14)
#define RT5670_ADC_R_OSR_MASK (0x3 << 12)
#define RT5670_ADC_R_OSR_SFT 12
#define RT5670_ADC_R_OSR_128 (0x0 << 12)
#define RT5670_ADC_R_OSR_64 (0x1 << 12)
#define RT5670_ADC_R_OSR_32 (0x2 << 12)
#define RT5670_ADC_R_OSR_16 (0x3 << 12)
#define RT5670_DAHPF_EN (0x1 << 11)
#define RT5670_DAHPF_EN_SFT 11
#define RT5670_ADHPF_EN (0x1 << 10)
#define RT5670_ADHPF_EN_SFT 10
/* Digital Microphone Control (0x75) */
#define RT5670_DMIC_1_EN_MASK (0x1 << 15)
#define RT5670_DMIC_1_EN_SFT 15
#define RT5670_DMIC_1_DIS (0x0 << 15)
#define RT5670_DMIC_1_EN (0x1 << 15)
#define RT5670_DMIC_2_EN_MASK (0x1 << 14)
#define RT5670_DMIC_2_EN_SFT 14
#define RT5670_DMIC_2_DIS (0x0 << 14)
#define RT5670_DMIC_2_EN (0x1 << 14)
#define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
#define RT5670_DMIC_1L_LH_SFT 13
#define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
#define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
#define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
#define RT5670_DMIC_1R_LH_SFT 12
#define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
#define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
#define RT5670_DMIC_2_DP_MASK (0x1 << 10)
#define RT5670_DMIC_2_DP_SFT 10
#define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
#define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
#define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
#define RT5670_DMIC_2L_LH_SFT 9
#define RT5670_DMIC_2L_LH_FALLING (0x0 << 9)
#define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
#define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
#define RT5670_DMIC_2R_LH_SFT 8
#define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
#define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
#define RT5670_DMIC_CLK_MASK (0x7 << 5)
#define RT5670_DMIC_CLK_SFT 5
#define RT5670_DMIC_3_EN_MASK (0x1 << 4)
#define RT5670_DMIC_3_EN_SFT 4
#define RT5670_DMIC_3_DIS (0x0 << 4)
#define RT5670_DMIC_3_EN (0x1 << 4)
#define RT5670_DMIC_1_DP_MASK (0x3 << 0)
#define RT5670_DMIC_1_DP_SFT 0
#define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0)
#define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
#define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0)
/* Digital Microphone Control2 (0x76) */
#define RT5670_DMIC_3_DP_MASK (0x3 << 6)
#define RT5670_DMIC_3_DP_SFT 6
#define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6)
#define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
#define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6)
/* Global Clock Control (0x80) */
#define RT5670_SCLK_SRC_MASK (0x3 << 14)
#define RT5670_SCLK_SRC_SFT 14
#define RT5670_SCLK_SRC_MCLK (0x0 << 14)
#define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
#define RT5670_PLL1_SRC_MASK (0x3 << 12)
#define RT5670_PLL1_SRC_SFT 12
#define RT5670_PLL1_SRC_MCLK (0x0 << 12)
#define RT5670_PLL1_SRC_BCLK1 (0x1 << 12)
#define RT5670_PLL1_SRC_BCLK2 (0x2 << 12)
#define RT5670_PLL1_SRC_BCLK3 (0x3 << 12)
#define RT5670_PLL1_PD_MASK (0x1 << 3)
#define RT5670_PLL1_PD_SFT 3
#define RT5670_PLL1_PD_1 (0x0 << 3)
#define RT5670_PLL1_PD_2 (0x1 << 3)
#define RT5670_PLL_INP_MAX 40000000
#define RT5670_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x81) */
#define RT5670_PLL_N_MAX 0x1ff
#define RT5670_PLL_N_MASK (RT5670_PLL_N_MAX << 7)
#define RT5670_PLL_N_SFT 7
#define RT5670_PLL_K_MAX 0x1f
#define RT5670_PLL_K_MASK (RT5670_PLL_K_MAX)
#define RT5670_PLL_K_SFT 0
/* PLL M/N/K Code Control 2 (0x82) */
#define RT5670_PLL_M_MAX 0xf
#define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12)
#define RT5670_PLL_M_SFT 12
#define RT5670_PLL_M_BP (0x1 << 11)
#define RT5670_PLL_M_BP_SFT 11
/* ASRC Control 1 (0x83) */
#define RT5670_STO_T_MASK (0x1 << 15)
#define RT5670_STO_T_SFT 15
#define RT5670_STO_T_SCLK (0x0 << 15)
#define RT5670_STO_T_LRCK1 (0x1 << 15)
#define RT5670_M1_T_MASK (0x1 << 14)
#define RT5670_M1_T_SFT 14
#define RT5670_M1_T_I2S2 (0x0 << 14)
#define RT5670_M1_T_I2S2_D3 (0x1 << 14)
#define RT5670_I2S2_F_MASK (0x1 << 12)
#define RT5670_I2S2_F_SFT 12
#define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
#define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
#define RT5670_DMIC_1_M_MASK (0x1 << 9)
#define RT5670_DMIC_1_M_SFT 9
#define RT5670_DMIC_1_M_NOR (0x0 << 9)
#define RT5670_DMIC_1_M_ASYN (0x1 << 9)
#define RT5670_DMIC_2_M_MASK (0x1 << 8)
#define RT5670_DMIC_2_M_SFT 8
#define RT5670_DMIC_2_M_NOR (0x0 << 8)
#define RT5670_DMIC_2_M_ASYN (0x1 << 8)
/* ASRC Control 2 (0x84) */
#define RT5670_MDA_L_M_MASK (0x1 << 15)
#define RT5670_MDA_L_M_SFT 15
#define RT5670_MDA_L_M_NOR (0x0 << 15)
#define RT5670_MDA_L_M_ASYN (0x1 << 15)
#define RT5670_MDA_R_M_MASK (0x1 << 14)
#define RT5670_MDA_R_M_SFT 14
#define RT5670_MDA_R_M_NOR (0x0 << 14)
#define RT5670_MDA_R_M_ASYN (0x1 << 14)
#define RT5670_MAD_L_M_MASK (0x1 << 13)
#define RT5670_MAD_L_M_SFT 13
#define RT5670_MAD_L_M_NOR (0x0 << 13)
#define RT5670_MAD_L_M_ASYN (0x1 << 13)
#define RT5670_MAD_R_M_MASK (0x1 << 12)
#define RT5670_MAD_R_M_SFT 12
#define RT5670_MAD_R_M_NOR (0x0 << 12)
#define RT5670_MAD_R_M_ASYN (0x1 << 12)
#define RT5670_ADC_M_MASK (0x1 << 11)
#define RT5670_ADC_M_SFT 11
#define RT5670_ADC_M_NOR (0x0 << 11)
#define RT5670_ADC_M_ASYN (0x1 << 11)
#define RT5670_STO_DAC_M_MASK (0x1 << 5)
#define RT5670_STO_DAC_M_SFT 5
#define RT5670_STO_DAC_M_NOR (0x0 << 5)
#define RT5670_STO_DAC_M_ASYN (0x1 << 5)
#define RT5670_I2S1_R_D_MASK (0x1 << 4)
#define RT5670_I2S1_R_D_SFT 4
#define RT5670_I2S1_R_D_DIS (0x0 << 4)
#define RT5670_I2S1_R_D_EN (0x1 << 4)
#define RT5670_I2S2_R_D_MASK (0x1 << 3)
#define RT5670_I2S2_R_D_SFT 3
#define RT5670_I2S2_R_D_DIS (0x0 << 3)
#define RT5670_I2S2_R_D_EN (0x1 << 3)
#define RT5670_PRE_SCLK_MASK (0x3)
#define RT5670_PRE_SCLK_SFT 0
#define RT5670_PRE_SCLK_512 (0x0)
#define RT5670_PRE_SCLK_1024 (0x1)
#define RT5670_PRE_SCLK_2048 (0x2)
/* ASRC Control 3 (0x85) */
#define RT5670_I2S1_RATE_MASK (0xf << 12)
#define RT5670_I2S1_RATE_SFT 12
#define RT5670_I2S2_RATE_MASK (0xf << 8)
#define RT5670_I2S2_RATE_SFT 8
/* ASRC Control 4 (0x89) */
#define RT5670_I2S1_PD_MASK (0x7 << 12)
#define RT5670_I2S1_PD_SFT 12
#define RT5670_I2S2_PD_MASK (0x7 << 8)
#define RT5670_I2S2_PD_SFT 8
/* HPOUT Over Current Detection (0x8b) */
#define RT5670_HP_OVCD_MASK (0x1 << 10)
#define RT5670_HP_OVCD_SFT 10
#define RT5670_HP_OVCD_DIS (0x0 << 10)
#define RT5670_HP_OVCD_EN (0x1 << 10)
#define RT5670_HP_OC_TH_MASK (0x3 << 8)
#define RT5670_HP_OC_TH_SFT 8
#define RT5670_HP_OC_TH_90 (0x0 << 8)
#define RT5670_HP_OC_TH_105 (0x1 << 8)
#define RT5670_HP_OC_TH_120 (0x2 << 8)
#define RT5670_HP_OC_TH_135 (0x3 << 8)
/* Class D Over Current Control (0x8c) */
#define RT5670_CLSD_OC_MASK (0x1 << 9)
#define RT5670_CLSD_OC_SFT 9
#define RT5670_CLSD_OC_PU (0x0 << 9)
#define RT5670_CLSD_OC_PD (0x1 << 9)
#define RT5670_AUTO_PD_MASK (0x1 << 8)
#define RT5670_AUTO_PD_SFT 8
#define RT5670_AUTO_PD_DIS (0x0 << 8)
#define RT5670_AUTO_PD_EN (0x1 << 8)
#define RT5670_CLSD_OC_TH_MASK (0x3f)
#define RT5670_CLSD_OC_TH_SFT 0
/* Class D Output Control (0x8d) */
#define RT5670_CLSD_RATIO_MASK (0xf << 12)
#define RT5670_CLSD_RATIO_SFT 12
#define RT5670_CLSD_OM_MASK (0x1 << 11)
#define RT5670_CLSD_OM_SFT 11
#define RT5670_CLSD_OM_MONO (0x0 << 11)
#define RT5670_CLSD_OM_STO (0x1 << 11)
#define RT5670_CLSD_SCH_MASK (0x1 << 10)
#define RT5670_CLSD_SCH_SFT 10
#define RT5670_CLSD_SCH_L (0x0 << 10)
#define RT5670_CLSD_SCH_S (0x1 << 10)
/* Depop Mode Control 1 (0x8e) */
#define RT5670_SMT_TRIG_MASK (0x1 << 15)
#define RT5670_SMT_TRIG_SFT 15
#define RT5670_SMT_TRIG_DIS (0x0 << 15)
#define RT5670_SMT_TRIG_EN (0x1 << 15)
#define RT5670_HP_L_SMT_MASK (0x1 << 9)
#define RT5670_HP_L_SMT_SFT 9
#define RT5670_HP_L_SMT_DIS (0x0 << 9)
#define RT5670_HP_L_SMT_EN (0x1 << 9)
#define RT5670_HP_R_SMT_MASK (0x1 << 8)
#define RT5670_HP_R_SMT_SFT 8
#define RT5670_HP_R_SMT_DIS (0x0 << 8)
#define RT5670_HP_R_SMT_EN (0x1 << 8)
#define RT5670_HP_CD_PD_MASK (0x1 << 7)
#define RT5670_HP_CD_PD_SFT 7
#define RT5670_HP_CD_PD_DIS (0x0 << 7)
#define RT5670_HP_CD_PD_EN (0x1 << 7)
#define RT5670_RSTN_MASK (0x1 << 6)
#define RT5670_RSTN_SFT 6
#define RT5670_RSTN_DIS (0x0 << 6)
#define RT5670_RSTN_EN (0x1 << 6)
#define RT5670_RSTP_MASK (0x1 << 5)
#define RT5670_RSTP_SFT 5
#define RT5670_RSTP_DIS (0x0 << 5)
#define RT5670_RSTP_EN (0x1 << 5)
#define RT5670_HP_CO_MASK (0x1 << 4)
#define RT5670_HP_CO_SFT 4
#define RT5670_HP_CO_DIS (0x0 << 4)
#define RT5670_HP_CO_EN (0x1 << 4)
#define RT5670_HP_CP_MASK (0x1 << 3)
#define RT5670_HP_CP_SFT 3
#define RT5670_HP_CP_PD (0x0 << 3)
#define RT5670_HP_CP_PU (0x1 << 3)
#define RT5670_HP_SG_MASK (0x1 << 2)
#define RT5670_HP_SG_SFT 2
#define RT5670_HP_SG_DIS (0x0 << 2)
#define RT5670_HP_SG_EN (0x1 << 2)
#define RT5670_HP_DP_MASK (0x1 << 1)
#define RT5670_HP_DP_SFT 1
#define RT5670_HP_DP_PD (0x0 << 1)
#define RT5670_HP_DP_PU (0x1 << 1)
#define RT5670_HP_CB_MASK (0x1)
#define RT5670_HP_CB_SFT 0
#define RT5670_HP_CB_PD (0x0)
#define RT5670_HP_CB_PU (0x1)
/* Depop Mode Control 2 (0x8f) */
#define RT5670_DEPOP_MASK (0x1 << 13)
#define RT5670_DEPOP_SFT 13
#define RT5670_DEPOP_AUTO (0x0 << 13)
#define RT5670_DEPOP_MAN (0x1 << 13)
#define RT5670_RAMP_MASK (0x1 << 12)
#define RT5670_RAMP_SFT 12
#define RT5670_RAMP_DIS (0x0 << 12)
#define RT5670_RAMP_EN (0x1 << 12)
#define RT5670_BPS_MASK (0x1 << 11)
#define RT5670_BPS_SFT 11
#define RT5670_BPS_DIS (0x0 << 11)
#define RT5670_BPS_EN (0x1 << 11)
#define RT5670_FAST_UPDN_MASK (0x1 << 10)
#define RT5670_FAST_UPDN_SFT 10
#define RT5670_FAST_UPDN_DIS (0x0 << 10)
#define RT5670_FAST_UPDN_EN (0x1 << 10)
#define RT5670_MRES_MASK (0x3 << 8)
#define RT5670_MRES_SFT 8
#define RT5670_MRES_15MO (0x0 << 8)
#define RT5670_MRES_25MO (0x1 << 8)
#define RT5670_MRES_35MO (0x2 << 8)
#define RT5670_MRES_45MO (0x3 << 8)
#define RT5670_VLO_MASK (0x1 << 7)
#define RT5670_VLO_SFT 7
#define RT5670_VLO_3V (0x0 << 7)
#define RT5670_VLO_32V (0x1 << 7)
#define RT5670_DIG_DP_MASK (0x1 << 6)
#define RT5670_DIG_DP_SFT 6
#define RT5670_DIG_DP_DIS (0x0 << 6)
#define RT5670_DIG_DP_EN (0x1 << 6)
#define RT5670_DP_TH_MASK (0x3 << 4)
#define RT5670_DP_TH_SFT 4
/* Depop Mode Control 3 (0x90) */
#define RT5670_CP_SYS_MASK (0x7 << 12)
#define RT5670_CP_SYS_SFT 12
#define RT5670_CP_FQ1_MASK (0x7 << 8)
#define RT5670_CP_FQ1_SFT 8
#define RT5670_CP_FQ2_MASK (0x7 << 4)
#define RT5670_CP_FQ2_SFT 4
#define RT5670_CP_FQ3_MASK (0x7)
#define RT5670_CP_FQ3_SFT 0
#define RT5670_CP_FQ_1_5_KHZ 0
#define RT5670_CP_FQ_3_KHZ 1
#define RT5670_CP_FQ_6_KHZ 2
#define RT5670_CP_FQ_12_KHZ 3
#define RT5670_CP_FQ_24_KHZ 4
#define RT5670_CP_FQ_48_KHZ 5
#define RT5670_CP_FQ_96_KHZ 6
#define RT5670_CP_FQ_192_KHZ 7
/* HPOUT charge pump (0x91) */
#define RT5670_OSW_L_MASK (0x1 << 11)
#define RT5670_OSW_L_SFT 11
#define RT5670_OSW_L_DIS (0x0 << 11)
#define RT5670_OSW_L_EN (0x1 << 11)
#define RT5670_OSW_R_MASK (0x1 << 10)
#define RT5670_OSW_R_SFT 10
#define RT5670_OSW_R_DIS (0x0 << 10)
#define RT5670_OSW_R_EN (0x1 << 10)
#define RT5670_PM_HP_MASK (0x3 << 8)
#define RT5670_PM_HP_SFT 8
#define RT5670_PM_HP_LV (0x0 << 8)
#define RT5670_PM_HP_MV (0x1 << 8)
#define RT5670_PM_HP_HV (0x2 << 8)
#define RT5670_IB_HP_MASK (0x3 << 6)
#define RT5670_IB_HP_SFT 6
#define RT5670_IB_HP_125IL (0x0 << 6)
#define RT5670_IB_HP_25IL (0x1 << 6)
#define RT5670_IB_HP_5IL (0x2 << 6)
#define RT5670_IB_HP_1IL (0x3 << 6)
/* PV detection and SPK gain control (0x92) */
#define RT5670_PVDD_DET_MASK (0x1 << 15)
#define RT5670_PVDD_DET_SFT 15
#define RT5670_PVDD_DET_DIS (0x0 << 15)
#define RT5670_PVDD_DET_EN (0x1 << 15)
#define RT5670_SPK_AG_MASK (0x1 << 14)
#define RT5670_SPK_AG_SFT 14
#define RT5670_SPK_AG_DIS (0x0 << 14)
#define RT5670_SPK_AG_EN (0x1 << 14)
/* Micbias Control (0x93) */
#define RT5670_MIC1_BS_MASK (0x1 << 15)
#define RT5670_MIC1_BS_SFT 15
#define RT5670_MIC1_BS_9AV (0x0 << 15)
#define RT5670_MIC1_BS_75AV (0x1 << 15)
#define RT5670_MIC2_BS_MASK (0x1 << 14)
#define RT5670_MIC2_BS_SFT 14
#define RT5670_MIC2_BS_9AV (0x0 << 14)
#define RT5670_MIC2_BS_75AV (0x1 << 14)
#define RT5670_MIC1_CLK_MASK (0x1 << 13)
#define RT5670_MIC1_CLK_SFT 13
#define RT5670_MIC1_CLK_DIS (0x0 << 13)
#define RT5670_MIC1_CLK_EN (0x1 << 13)
#define RT5670_MIC2_CLK_MASK (0x1 << 12)
#define RT5670_MIC2_CLK_SFT 12
#define RT5670_MIC2_CLK_DIS (0x0 << 12)
#define RT5670_MIC2_CLK_EN (0x1 << 12)
#define RT5670_MIC1_OVCD_MASK (0x1 << 11)
#define RT5670_MIC1_OVCD_SFT 11
#define RT5670_MIC1_OVCD_DIS (0x0 << 11)
#define RT5670_MIC1_OVCD_EN (0x1 << 11)
#define RT5670_MIC1_OVTH_MASK (0x3 << 9)
#define RT5670_MIC1_OVTH_SFT 9
#define RT5670_MIC1_OVTH_600UA (0x0 << 9)
#define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
#define RT5670_MIC1_OVTH_2000UA (0x2 << 9)
#define RT5670_MIC2_OVCD_MASK (0x1 << 8)
#define RT5670_MIC2_OVCD_SFT 8
#define RT5670_MIC2_OVCD_DIS (0x0 << 8)
#define RT5670_MIC2_OVCD_EN (0x1 << 8)
#define RT5670_MIC2_OVTH_MASK (0x3 << 6)
#define RT5670_MIC2_OVTH_SFT 6
#define RT5670_MIC2_OVTH_600UA (0x0 << 6)
#define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
#define RT5670_MIC2_OVTH_2000UA (0x2 << 6)
#define RT5670_PWR_MB_MASK (0x1 << 5)
#define RT5670_PWR_MB_SFT 5
#define RT5670_PWR_MB_PD (0x0 << 5)
#define RT5670_PWR_MB_PU (0x1 << 5)
#define RT5670_PWR_CLK25M_MASK (0x1 << 4)
#define RT5670_PWR_CLK25M_SFT 4
#define RT5670_PWR_CLK25M_PD (0x0 << 4)
#define RT5670_PWR_CLK25M_PU (0x1 << 4)
/* Analog JD Control 1 (0x94) */
#define RT5670_JD1_MODE_MASK (0x3 << 0)
#define RT5670_JD1_MODE_0 (0x0 << 0)
#define RT5670_JD1_MODE_1 (0x1 << 0)
#define RT5670_JD1_MODE_2 (0x2 << 0)
/* VAD Control 4 (0x9d) */
#define RT5670_VAD_SEL_MASK (0x3 << 8)
#define RT5670_VAD_SEL_SFT 8
/* EQ Control 1 (0xb0) */
#define RT5670_EQ_SRC_MASK (0x1 << 15)
#define RT5670_EQ_SRC_SFT 15
#define RT5670_EQ_SRC_DAC (0x0 << 15)
#define RT5670_EQ_SRC_ADC (0x1 << 15)
#define RT5670_EQ_UPD (0x1 << 14)
#define RT5670_EQ_UPD_BIT 14
#define RT5670_EQ_CD_MASK (0x1 << 13)
#define RT5670_EQ_CD_SFT 13
#define RT5670_EQ_CD_DIS (0x0 << 13)
#define RT5670_EQ_CD_EN (0x1 << 13)
#define RT5670_EQ_DITH_MASK (0x3 << 8)
#define RT5670_EQ_DITH_SFT 8
#define RT5670_EQ_DITH_NOR (0x0 << 8)
#define RT5670_EQ_DITH_LSB (0x1 << 8)
#define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
#define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
/* EQ Control 2 (0xb1) */
#define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
#define RT5670_EQ_HPF1_M_SFT 8
#define RT5670_EQ_HPF1_M_HI (0x0 << 8)
#define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
#define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
#define RT5670_EQ_LPF1_M_SFT 7
#define RT5670_EQ_LPF1_M_LO (0x0 << 7)
#define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
#define RT5670_EQ_HPF2_MASK (0x1 << 6)
#define RT5670_EQ_HPF2_SFT 6
#define RT5670_EQ_HPF2_DIS (0x0 << 6)
#define RT5670_EQ_HPF2_EN (0x1 << 6)
#define RT5670_EQ_HPF1_MASK (0x1 << 5)
#define RT5670_EQ_HPF1_SFT 5
#define RT5670_EQ_HPF1_DIS (0x0 << 5)
#define RT5670_EQ_HPF1_EN (0x1 << 5)
#define RT5670_EQ_BPF4_MASK (0x1 << 4)
#define RT5670_EQ_BPF4_SFT 4
#define RT5670_EQ_BPF4_DIS (0x0 << 4)
#define RT5670_EQ_BPF4_EN (0x1 << 4)
#define RT5670_EQ_BPF3_MASK (0x1 << 3)
#define RT5670_EQ_BPF3_SFT 3
#define RT5670_EQ_BPF3_DIS (0x0 << 3)
#define RT5670_EQ_BPF3_EN (0x1 << 3)
#define RT5670_EQ_BPF2_MASK (0x1 << 2)
#define RT5670_EQ_BPF2_SFT 2
#define RT5670_EQ_BPF2_DIS (0x0 << 2)
#define RT5670_EQ_BPF2_EN (0x1 << 2)
#define RT5670_EQ_BPF1_MASK (0x1 << 1)
#define RT5670_EQ_BPF1_SFT 1
#define RT5670_EQ_BPF1_DIS (0x0 << 1)
#define RT5670_EQ_BPF1_EN (0x1 << 1)
#define RT5670_EQ_LPF_MASK (0x1)
#define RT5670_EQ_LPF_SFT 0
#define RT5670_EQ_LPF_DIS (0x0)
#define RT5670_EQ_LPF_EN (0x1)
#define RT5670_EQ_CTRL_MASK (0x7f)
/* Memory Test (0xb2) */
#define RT5670_MT_MASK (0x1 << 15)
#define RT5670_MT_SFT 15
#define RT5670_MT_DIS (0x0 << 15)
#define RT5670_MT_EN (0x1 << 15)
/* DRC/AGC Control 1 (0xb4) */
#define RT5670_DRC_AGC_P_MASK (0x1 << 15)
#define RT5670_DRC_AGC_P_SFT 15
#define RT5670_DRC_AGC_P_DAC (0x0 << 15)
#define RT5670_DRC_AGC_P_ADC (0x1 << 15)
#define RT5670_DRC_AGC_MASK (0x1 << 14)
#define RT5670_DRC_AGC_SFT 14
#define RT5670_DRC_AGC_DIS (0x0 << 14)
#define RT5670_DRC_AGC_EN (0x1 << 14)
#define RT5670_DRC_AGC_UPD (0x1 << 13)
#define RT5670_DRC_AGC_UPD_BIT 13
#define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
#define RT5670_DRC_AGC_AR_SFT 8
#define RT5670_DRC_AGC_R_MASK (0x7 << 5)
#define RT5670_DRC_AGC_R_SFT 5
#define RT5670_DRC_AGC_R_48K (0x1 << 5)
#define RT5670_DRC_AGC_R_96K (0x2 << 5)
#define RT5670_DRC_AGC_R_192K (0x3 << 5)
#define RT5670_DRC_AGC_R_441K (0x5 << 5)
#define RT5670_DRC_AGC_R_882K (0x6 << 5)
#define RT5670_DRC_AGC_R_1764K (0x7 << 5)
#define RT5670_DRC_AGC_RC_MASK (0x1f)
#define RT5670_DRC_AGC_RC_SFT 0
/* DRC/AGC Control 2 (0xb5) */
#define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
#define RT5670_DRC_AGC_POB_SFT 8
#define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
#define RT5670_DRC_AGC_CP_SFT 7
#define RT5670_DRC_AGC_CP_DIS (0x0 << 7)
#define RT5670_DRC_AGC_CP_EN (0x1 << 7)
#define RT5670_DRC_AGC_CPR_MASK (0x3 << 5)
#define RT5670_DRC_AGC_CPR_SFT 5
#define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5)
#define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
#define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5)
#define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5)
#define RT5670_DRC_AGC_PRB_MASK (0x1f)
#define RT5670_DRC_AGC_PRB_SFT 0
/* DRC/AGC Control 3 (0xb6) */
#define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
#define RT5670_DRC_AGC_NGB_SFT 12
#define RT5670_DRC_AGC_TAR_MASK (0x1f << 7)
#define RT5670_DRC_AGC_TAR_SFT 7
#define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
#define RT5670_DRC_AGC_NG_SFT 6
#define RT5670_DRC_AGC_NG_DIS (0x0 << 6)
#define RT5670_DRC_AGC_NG_EN (0x1 << 6)
#define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
#define RT5670_DRC_AGC_NGH_SFT 5
#define RT5670_DRC_AGC_NGH_DIS (0x0 << 5)
#define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
#define RT5670_DRC_AGC_NGT_MASK (0x1f)
#define RT5670_DRC_AGC_NGT_SFT 0
/* Jack Detect Control (0xbb) */
#define RT5670_JD_MASK (0x7 << 13)
#define RT5670_JD_SFT 13
#define RT5670_JD_DIS (0x0 << 13)
#define RT5670_JD_GPIO1 (0x1 << 13)
#define RT5670_JD_JD1_IN4P (0x2 << 13)
#define RT5670_JD_JD2_IN4N (0x3 << 13)
#define RT5670_JD_GPIO2 (0x4 << 13)
#define RT5670_JD_GPIO3 (0x5 << 13)
#define RT5670_JD_GPIO4 (0x6 << 13)
#define RT5670_JD_HP_MASK (0x1 << 11)
#define RT5670_JD_HP_SFT 11
#define RT5670_JD_HP_DIS (0x0 << 11)
#define RT5670_JD_HP_EN (0x1 << 11)
#define RT5670_JD_HP_TRG_MASK (0x1 << 10)
#define RT5670_JD_HP_TRG_SFT 10
#define RT5670_JD_HP_TRG_LO (0x0 << 10)
#define RT5670_JD_HP_TRG_HI (0x1 << 10)
#define RT5670_JD_SPL_MASK (0x1 << 9)
#define RT5670_JD_SPL_SFT 9
#define RT5670_JD_SPL_DIS (0x0 << 9)
#define RT5670_JD_SPL_EN (0x1 << 9)
#define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
#define RT5670_JD_SPL_TRG_SFT 8
#define RT5670_JD_SPL_TRG_LO (0x0 << 8)
#define RT5670_JD_SPL_TRG_HI (0x1 << 8)
#define RT5670_JD_SPR_MASK (0x1 << 7)
#define RT5670_JD_SPR_SFT 7
#define RT5670_JD_SPR_DIS (0x0 << 7)
#define RT5670_JD_SPR_EN (0x1 << 7)
#define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
#define RT5670_JD_SPR_TRG_SFT 6
#define RT5670_JD_SPR_TRG_LO (0x0 << 6)
#define RT5670_JD_SPR_TRG_HI (0x1 << 6)
#define RT5670_JD_MO_MASK (0x1 << 5)
#define RT5670_JD_MO_SFT 5
#define RT5670_JD_MO_DIS (0x0 << 5)
#define RT5670_JD_MO_EN (0x1 << 5)
#define RT5670_JD_MO_TRG_MASK (0x1 << 4)
#define RT5670_JD_MO_TRG_SFT 4
#define RT5670_JD_MO_TRG_LO (0x0 << 4)
#define RT5670_JD_MO_TRG_HI (0x1 << 4)
#define RT5670_JD_LO_MASK (0x1 << 3)
#define RT5670_JD_LO_SFT 3
#define RT5670_JD_LO_DIS (0x0 << 3)
#define RT5670_JD_LO_EN (0x1 << 3)
#define RT5670_JD_LO_TRG_MASK (0x1 << 2)
#define RT5670_JD_LO_TRG_SFT 2
#define RT5670_JD_LO_TRG_LO (0x0 << 2)
#define RT5670_JD_LO_TRG_HI (0x1 << 2)
#define RT5670_JD1_IN4P_MASK (0x1 << 1)
#define RT5670_JD1_IN4P_SFT 1
#define RT5670_JD1_IN4P_DIS (0x0 << 1)
#define RT5670_JD1_IN4P_EN (0x1 << 1)
#define RT5670_JD2_IN4N_MASK (0x1)
#define RT5670_JD2_IN4N_SFT 0
#define RT5670_JD2_IN4N_DIS (0x0)
#define RT5670_JD2_IN4N_EN (0x1)
/* IRQ Control 1 (0xbd) */
#define RT5670_IRQ_JD_MASK (0x1 << 15)
#define RT5670_IRQ_JD_SFT 15
#define RT5670_IRQ_JD_BP (0x0 << 15)
#define RT5670_IRQ_JD_NOR (0x1 << 15)
#define RT5670_IRQ_OT_MASK (0x1 << 14)
#define RT5670_IRQ_OT_SFT 14
#define RT5670_IRQ_OT_BP (0x0 << 14)
#define RT5670_IRQ_OT_NOR (0x1 << 14)
#define RT5670_JD_STKY_MASK (0x1 << 13)
#define RT5670_JD_STKY_SFT 13
#define RT5670_JD_STKY_DIS (0x0 << 13)
#define RT5670_JD_STKY_EN (0x1 << 13)
#define RT5670_OT_STKY_MASK (0x1 << 12)
#define RT5670_OT_STKY_SFT 12
#define RT5670_OT_STKY_DIS (0x0 << 12)
#define RT5670_OT_STKY_EN (0x1 << 12)
#define RT5670_JD_P_MASK (0x1 << 11)
#define RT5670_JD_P_SFT 11
#define RT5670_JD_P_NOR (0x0 << 11)
#define RT5670_JD_P_INV (0x1 << 11)
#define RT5670_OT_P_MASK (0x1 << 10)
#define RT5670_OT_P_SFT 10
#define RT5670_OT_P_NOR (0x0 << 10)
#define RT5670_OT_P_INV (0x1 << 10)
#define RT5670_JD1_1_EN_MASK (0x1 << 9)
#define RT5670_JD1_1_EN_SFT 9
#define RT5670_JD1_1_DIS (0x0 << 9)
#define RT5670_JD1_1_EN (0x1 << 9)
/* IRQ Control 2 (0xbe) */
#define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
#define RT5670_IRQ_MB1_OC_SFT 15
#define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
#define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
#define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
#define RT5670_IRQ_MB2_OC_SFT 14
#define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
#define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
#define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
#define RT5670_MB1_OC_STKY_SFT 11
#define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
#define RT5670_MB1_OC_STKY_EN (0x1 << 11)
#define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
#define RT5670_MB2_OC_STKY_SFT 10
#define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
#define RT5670_MB2_OC_STKY_EN (0x1 << 10)
#define RT5670_MB1_OC_P_MASK (0x1 << 7)
#define RT5670_MB1_OC_P_SFT 7
#define RT5670_MB1_OC_P_NOR (0x0 << 7)
#define RT5670_MB1_OC_P_INV (0x1 << 7)
#define RT5670_MB2_OC_P_MASK (0x1 << 6)
#define RT5670_MB2_OC_P_SFT 6
#define RT5670_MB2_OC_P_NOR (0x0 << 6)
#define RT5670_MB2_OC_P_INV (0x1 << 6)
#define RT5670_MB1_OC_CLR (0x1 << 3)
#define RT5670_MB1_OC_CLR_SFT 3
#define RT5670_MB2_OC_CLR (0x1 << 2)
#define RT5670_MB2_OC_CLR_SFT 2
/* GPIO Control 1 (0xc0) */
#define RT5670_GP1_PIN_MASK (0x1 << 15)
#define RT5670_GP1_PIN_SFT 15
#define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5670_GP1_PIN_IRQ (0x1 << 15)
#define RT5670_GP2_PIN_MASK (0x1 << 14)
#define RT5670_GP2_PIN_SFT 14
#define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
#define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
#define RT5670_GP3_PIN_MASK (0x3 << 12)
#define RT5670_GP3_PIN_SFT 12
#define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
#define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
#define RT5670_GP3_PIN_IRQ (0x2 << 12)
#define RT5670_GP4_PIN_MASK (0x1 << 11)
#define RT5670_GP4_PIN_SFT 11
#define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
#define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
#define RT5670_DP_SIG_MASK (0x1 << 10)
#define RT5670_DP_SIG_SFT 10
#define RT5670_DP_SIG_TEST (0x0 << 10)
#define RT5670_DP_SIG_AP (0x1 << 10)
#define RT5670_GPIO_M_MASK (0x1 << 9)
#define RT5670_GPIO_M_SFT 9
#define RT5670_GPIO_M_FLT (0x0 << 9)
#define RT5670_GPIO_M_PH (0x1 << 9)
#define RT5670_I2S2_PIN_MASK (0x1 << 8)
#define RT5670_I2S2_PIN_SFT 8
#define RT5670_I2S2_PIN_I2S (0x0 << 8)
#define RT5670_I2S2_PIN_GPIO (0x1 << 8)
#define RT5670_GP5_PIN_MASK (0x1 << 7)
#define RT5670_GP5_PIN_SFT 7
#define RT5670_GP5_PIN_GPIO5 (0x0 << 7)
#define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
#define RT5670_GP6_PIN_MASK (0x1 << 6)
#define RT5670_GP6_PIN_SFT 6
#define RT5670_GP6_PIN_GPIO6 (0x0 << 6)
#define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
#define RT5670_GP7_PIN_MASK (0x3 << 4)
#define RT5670_GP7_PIN_SFT 4
#define RT5670_GP7_PIN_GPIO7 (0x0 << 4)
#define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
#define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4)
#define RT5670_GP8_PIN_MASK (0x1 << 3)
#define RT5670_GP8_PIN_SFT 3
#define RT5670_GP8_PIN_GPIO8 (0x0 << 3)
#define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
#define RT5670_GP9_PIN_MASK (0x1 << 2)
#define RT5670_GP9_PIN_SFT 2
#define RT5670_GP9_PIN_GPIO9 (0x0 << 2)
#define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
#define RT5670_GP10_PIN_MASK (0x3)
#define RT5670_GP10_PIN_SFT 0
#define RT5670_GP10_PIN_GPIO9 (0x0)
#define RT5670_GP10_PIN_DMIC3_SDA (0x1)
#define RT5670_GP10_PIN_PDM_ADT2 (0x2)
/* GPIO Control 2 (0xc1) */
#define RT5670_GP4_PF_MASK (0x1 << 11)
#define RT5670_GP4_PF_SFT 11
#define RT5670_GP4_PF_IN (0x0 << 11)
#define RT5670_GP4_PF_OUT (0x1 << 11)
#define RT5670_GP4_OUT_MASK (0x1 << 10)
#define RT5670_GP4_OUT_SFT 10
#define RT5670_GP4_OUT_LO (0x0 << 10)
#define RT5670_GP4_OUT_HI (0x1 << 10)
#define RT5670_GP4_P_MASK (0x1 << 9)
#define RT5670_GP4_P_SFT 9
#define RT5670_GP4_P_NOR (0x0 << 9)
#define RT5670_GP4_P_INV (0x1 << 9)
#define RT5670_GP3_PF_MASK (0x1 << 8)
#define RT5670_GP3_PF_SFT 8
#define RT5670_GP3_PF_IN (0x0 << 8)
#define RT5670_GP3_PF_OUT (0x1 << 8)
#define RT5670_GP3_OUT_MASK (0x1 << 7)
#define RT5670_GP3_OUT_SFT 7
#define RT5670_GP3_OUT_LO (0x0 << 7)
#define RT5670_GP3_OUT_HI (0x1 << 7)
#define RT5670_GP3_P_MASK (0x1 << 6)
#define RT5670_GP3_P_SFT 6
#define RT5670_GP3_P_NOR (0x0 << 6)
#define RT5670_GP3_P_INV (0x1 << 6)
#define RT5670_GP2_PF_MASK (0x1 << 5)
#define RT5670_GP2_PF_SFT 5
#define RT5670_GP2_PF_IN (0x0 << 5)
#define RT5670_GP2_PF_OUT (0x1 << 5)
#define RT5670_GP2_OUT_MASK (0x1 << 4)
#define RT5670_GP2_OUT_SFT 4
#define RT5670_GP2_OUT_LO (0x0 << 4)
#define RT5670_GP2_OUT_HI (0x1 << 4)
#define RT5670_GP2_P_MASK (0x1 << 3)
#define RT5670_GP2_P_SFT 3
#define RT5670_GP2_P_NOR (0x0 << 3)
#define RT5670_GP2_P_INV (0x1 << 3)
#define RT5670_GP1_PF_MASK (0x1 << 2)
#define RT5670_GP1_PF_SFT 2
#define RT5670_GP1_PF_IN (0x0 << 2)
#define RT5670_GP1_PF_OUT (0x1 << 2)
#define RT5670_GP1_OUT_MASK (0x1 << 1)
#define RT5670_GP1_OUT_SFT 1
#define RT5670_GP1_OUT_LO (0x0 << 1)
#define RT5670_GP1_OUT_HI (0x1 << 1)
#define RT5670_GP1_P_MASK (0x1)
#define RT5670_GP1_P_SFT 0
#define RT5670_GP1_P_NOR (0x0)
#define RT5670_GP1_P_INV (0x1)
/* Scramble Function (0xcd) */
#define RT5670_SCB_KEY_MASK (0xff)
#define RT5670_SCB_KEY_SFT 0
/* Scramble Control (0xce) */
#define RT5670_SCB_SWAP_MASK (0x1 << 15)
#define RT5670_SCB_SWAP_SFT 15
#define RT5670_SCB_SWAP_DIS (0x0 << 15)
#define RT5670_SCB_SWAP_EN (0x1 << 15)
#define RT5670_SCB_MASK (0x1 << 14)
#define RT5670_SCB_SFT 14
#define RT5670_SCB_DIS (0x0 << 14)
#define RT5670_SCB_EN (0x1 << 14)
/* Baseback Control (0xcf) */
#define RT5670_BB_MASK (0x1 << 15)
#define RT5670_BB_SFT 15
#define RT5670_BB_DIS (0x0 << 15)
#define RT5670_BB_EN (0x1 << 15)
#define RT5670_BB_CT_MASK (0x7 << 12)
#define RT5670_BB_CT_SFT 12
#define RT5670_BB_CT_A (0x0 << 12)
#define RT5670_BB_CT_B (0x1 << 12)
#define RT5670_BB_CT_C (0x2 << 12)
#define RT5670_BB_CT_D (0x3 << 12)
#define RT5670_M_BB_L_MASK (0x1 << 9)
#define RT5670_M_BB_L_SFT 9
#define RT5670_M_BB_R_MASK (0x1 << 8)
#define RT5670_M_BB_R_SFT 8
#define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
#define RT5670_M_BB_HPF_L_SFT 7
#define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
#define RT5670_M_BB_HPF_R_SFT 6
#define RT5670_G_BB_BST_MASK (0x3f)
#define RT5670_G_BB_BST_SFT 0
/* MP3 Plus Control 1 (0xd0) */
#define RT5670_M_MP3_L_MASK (0x1 << 15)
#define RT5670_M_MP3_L_SFT 15
#define RT5670_M_MP3_R_MASK (0x1 << 14)
#define RT5670_M_MP3_R_SFT 14
#define RT5670_M_MP3_MASK (0x1 << 13)
#define RT5670_M_MP3_SFT 13
#define RT5670_M_MP3_DIS (0x0 << 13)
#define RT5670_M_MP3_EN (0x1 << 13)
#define RT5670_EG_MP3_MASK (0x1f << 8)
#define RT5670_EG_MP3_SFT 8
#define RT5670_MP3_HLP_MASK (0x1 << 7)
#define RT5670_MP3_HLP_SFT 7
#define RT5670_MP3_HLP_DIS (0x0 << 7)
#define RT5670_MP3_HLP_EN (0x1 << 7)
#define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
#define RT5670_M_MP3_ORG_L_SFT 6
#define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
#define RT5670_M_MP3_ORG_R_SFT 5
/* MP3 Plus Control 2 (0xd1) */
#define RT5670_MP3_WT_MASK (0x1 << 13)
#define RT5670_MP3_WT_SFT 13
#define RT5670_MP3_WT_1_4 (0x0 << 13)
#define RT5670_MP3_WT_1_2 (0x1 << 13)
#define RT5670_OG_MP3_MASK (0x1f << 8)
#define RT5670_OG_MP3_SFT 8
#define RT5670_HG_MP3_MASK (0x3f)
#define RT5670_HG_MP3_SFT 0
/* 3D HP Control 1 (0xd2) */
#define RT5670_3D_CF_MASK (0x1 << 15)
#define RT5670_3D_CF_SFT 15
#define RT5670_3D_CF_DIS (0x0 << 15)
#define RT5670_3D_CF_EN (0x1 << 15)
#define RT5670_3D_HP_MASK (0x1 << 14)
#define RT5670_3D_HP_SFT 14
#define RT5670_3D_HP_DIS (0x0 << 14)
#define RT5670_3D_HP_EN (0x1 << 14)
#define RT5670_3D_BT_MASK (0x1 << 13)
#define RT5670_3D_BT_SFT 13
#define RT5670_3D_BT_DIS (0x0 << 13)
#define RT5670_3D_BT_EN (0x1 << 13)
#define RT5670_3D_1F_MIX_MASK (0x3 << 11)
#define RT5670_3D_1F_MIX_SFT 11
#define RT5670_3D_HP_M_MASK (0x1 << 10)
#define RT5670_3D_HP_M_SFT 10
#define RT5670_3D_HP_M_SUR (0x0 << 10)
#define RT5670_3D_HP_M_FRO (0x1 << 10)
#define RT5670_M_3D_HRTF_MASK (0x1 << 9)
#define RT5670_M_3D_HRTF_SFT 9
#define RT5670_M_3D_D2H_MASK (0x1 << 8)
#define RT5670_M_3D_D2H_SFT 8
#define RT5670_M_3D_D2R_MASK (0x1 << 7)
#define RT5670_M_3D_D2R_SFT 7
#define RT5670_M_3D_REVB_MASK (0x1 << 6)
#define RT5670_M_3D_REVB_SFT 6
/* Adjustable high pass filter control 1 (0xd3) */
#define RT5670_2ND_HPF_MASK (0x1 << 15)
#define RT5670_2ND_HPF_SFT 15
#define RT5670_2ND_HPF_DIS (0x0 << 15)
#define RT5670_2ND_HPF_EN (0x1 << 15)
#define RT5670_HPF_CF_L_MASK (0x7 << 12)
#define RT5670_HPF_CF_L_SFT 12
#define RT5670_1ST_HPF_MASK (0x1 << 11)
#define RT5670_1ST_HPF_SFT 11
#define RT5670_1ST_HPF_DIS (0x0 << 11)
#define RT5670_1ST_HPF_EN (0x1 << 11)
#define RT5670_HPF_CF_R_MASK (0x7 << 8)
#define RT5670_HPF_CF_R_SFT 8
#define RT5670_ZD_T_MASK (0x3 << 6)
#define RT5670_ZD_T_SFT 6
#define RT5670_ZD_F_MASK (0x3 << 4)
#define RT5670_ZD_F_SFT 4
#define RT5670_ZD_F_IM (0x0 << 4)
#define RT5670_ZD_F_ZC_IM (0x1 << 4)
#define RT5670_ZD_F_ZC_IOD (0x2 << 4)
#define RT5670_ZD_F_UN (0x3 << 4)
/* HP calibration control and Amp detection (0xd6) */
#define RT5670_SI_DAC_MASK (0x1 << 11)
#define RT5670_SI_DAC_SFT 11
#define RT5670_SI_DAC_AUTO (0x0 << 11)
#define RT5670_SI_DAC_TEST (0x1 << 11)
#define RT5670_DC_CAL_M_MASK (0x1 << 10)
#define RT5670_DC_CAL_M_SFT 10
#define RT5670_DC_CAL_M_CAL (0x0 << 10)
#define RT5670_DC_CAL_M_NOR (0x1 << 10)
#define RT5670_DC_CAL_MASK (0x1 << 9)
#define RT5670_DC_CAL_SFT 9
#define RT5670_DC_CAL_DIS (0x0 << 9)
#define RT5670_DC_CAL_EN (0x1 << 9)
#define RT5670_HPD_RCV_MASK (0x7 << 6)
#define RT5670_HPD_RCV_SFT 6
#define RT5670_HPD_PS_MASK (0x1 << 5)
#define RT5670_HPD_PS_SFT 5
#define RT5670_HPD_PS_DIS (0x0 << 5)
#define RT5670_HPD_PS_EN (0x1 << 5)
#define RT5670_CAL_M_MASK (0x1 << 4)
#define RT5670_CAL_M_SFT 4
#define RT5670_CAL_M_DEP (0x0 << 4)
#define RT5670_CAL_M_CAL (0x1 << 4)
#define RT5670_CAL_MASK (0x1 << 3)
#define RT5670_CAL_SFT 3
#define RT5670_CAL_DIS (0x0 << 3)
#define RT5670_CAL_EN (0x1 << 3)
#define RT5670_CAL_TEST_MASK (0x1 << 2)
#define RT5670_CAL_TEST_SFT 2
#define RT5670_CAL_TEST_DIS (0x0 << 2)
#define RT5670_CAL_TEST_EN (0x1 << 2)
#define RT5670_CAL_P_MASK (0x3)
#define RT5670_CAL_P_SFT 0
#define RT5670_CAL_P_NONE (0x0)
#define RT5670_CAL_P_CAL (0x1)
#define RT5670_CAL_P_DAC_CAL (0x2)
/* Soft volume and zero cross control 1 (0xd9) */
#define RT5670_SV_MASK (0x1 << 15)
#define RT5670_SV_SFT 15
#define RT5670_SV_DIS (0x0 << 15)
#define RT5670_SV_EN (0x1 << 15)
#define RT5670_SPO_SV_MASK (0x1 << 14)
#define RT5670_SPO_SV_SFT 14
#define RT5670_SPO_SV_DIS (0x0 << 14)
#define RT5670_SPO_SV_EN (0x1 << 14)
#define RT5670_OUT_SV_MASK (0x1 << 13)
#define RT5670_OUT_SV_SFT 13
#define RT5670_OUT_SV_DIS (0x0 << 13)
#define RT5670_OUT_SV_EN (0x1 << 13)
#define RT5670_HP_SV_MASK (0x1 << 12)
#define RT5670_HP_SV_SFT 12
#define RT5670_HP_SV_DIS (0x0 << 12)
#define RT5670_HP_SV_EN (0x1 << 12)
#define RT5670_ZCD_DIG_MASK (0x1 << 11)
#define RT5670_ZCD_DIG_SFT 11
#define RT5670_ZCD_DIG_DIS (0x0 << 11)
#define RT5670_ZCD_DIG_EN (0x1 << 11)
#define RT5670_ZCD_MASK (0x1 << 10)
#define RT5670_ZCD_SFT 10
#define RT5670_ZCD_PD (0x0 << 10)
#define RT5670_ZCD_PU (0x1 << 10)
#define RT5670_M_ZCD_MASK (0x3f << 4)
#define RT5670_M_ZCD_SFT 4
#define RT5670_M_ZCD_RM_L (0x1 << 9)
#define RT5670_M_ZCD_RM_R (0x1 << 8)
#define RT5670_M_ZCD_SM_L (0x1 << 7)
#define RT5670_M_ZCD_SM_R (0x1 << 6)
#define RT5670_M_ZCD_OM_L (0x1 << 5)
#define RT5670_M_ZCD_OM_R (0x1 << 4)
#define RT5670_SV_DLY_MASK (0xf)
#define RT5670_SV_DLY_SFT 0
/* Soft volume and zero cross control 2 (0xda) */
#define RT5670_ZCD_HP_MASK (0x1 << 15)
#define RT5670_ZCD_HP_SFT 15
#define RT5670_ZCD_HP_DIS (0x0 << 15)
#define RT5670_ZCD_HP_EN (0x1 << 15)
/* Codec Private Register definition */
/* 3D Speaker Control (0x63) */
#define RT5670_3D_SPK_MASK (0x1 << 15)
#define RT5670_3D_SPK_SFT 15
#define RT5670_3D_SPK_DIS (0x0 << 15)
#define RT5670_3D_SPK_EN (0x1 << 15)
#define RT5670_3D_SPK_M_MASK (0x3 << 13)
#define RT5670_3D_SPK_M_SFT 13
#define RT5670_3D_SPK_CG_MASK (0x1f << 8)
#define RT5670_3D_SPK_CG_SFT 8
#define RT5670_3D_SPK_SG_MASK (0x1f)
#define RT5670_3D_SPK_SG_SFT 0
/* Wind Noise Detection Control 1 (0x6c) */
#define RT5670_WND_MASK (0x1 << 15)
#define RT5670_WND_SFT 15
#define RT5670_WND_DIS (0x0 << 15)
#define RT5670_WND_EN (0x1 << 15)
/* Wind Noise Detection Control 2 (0x6d) */
#define RT5670_WND_FC_NW_MASK (0x3f << 10)
#define RT5670_WND_FC_NW_SFT 10
#define RT5670_WND_FC_WK_MASK (0x3f << 4)
#define RT5670_WND_FC_WK_SFT 4
/* Wind Noise Detection Control 3 (0x6e) */
#define RT5670_HPF_FC_MASK (0x3f << 6)
#define RT5670_HPF_FC_SFT 6
#define RT5670_WND_FC_ST_MASK (0x3f)
#define RT5670_WND_FC_ST_SFT 0
/* Wind Noise Detection Control 4 (0x6f) */
#define RT5670_WND_TH_LO_MASK (0x3ff)
#define RT5670_WND_TH_LO_SFT 0
/* Wind Noise Detection Control 5 (0x70) */
#define RT5670_WND_TH_HI_MASK (0x3ff)
#define RT5670_WND_TH_HI_SFT 0
/* Wind Noise Detection Control 8 (0x73) */
#define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
#define RT5670_WND_WIND_SFT 13
#define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
#define RT5670_WND_STRONG_SFT 12
enum {
RT5670_NO_WIND,
RT5670_BREEZE,
RT5670_STORM,
};
/* Dipole Speaker Interface (0x75) */
#define RT5670_DP_ATT_MASK (0x3 << 14)
#define RT5670_DP_ATT_SFT 14
#define RT5670_DP_SPK_MASK (0x1 << 10)
#define RT5670_DP_SPK_SFT 10
#define RT5670_DP_SPK_DIS (0x0 << 10)
#define RT5670_DP_SPK_EN (0x1 << 10)
/* EQ Pre Volume Control (0xb3) */
#define RT5670_EQ_PRE_VOL_MASK (0xffff)
#define RT5670_EQ_PRE_VOL_SFT 0
/* EQ Post Volume Control (0xb4) */
#define RT5670_EQ_PST_VOL_MASK (0xffff)
#define RT5670_EQ_PST_VOL_SFT 0
/* Jack Detect Control 3 (0xf8) */
#define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
#define RT5670_JD_CBJ_EN (0x1 << 7)
#define RT5670_JD_CBJ_POL (0x1 << 6)
#define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
#define RT5670_JD_TRI_CBJ_SEL_SFT (3)
#define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3)
#define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
#define RT5670_JD_CBJ_JD1_2 (0x2 << 3)
#define RT5670_JD_CBJ_JD2 (0x3 << 3)
#define RT5670_JD_CBJ_JD3 (0x4 << 3)
#define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3)
#define RT5670_JD_CBJ_MX0B_12 (0x6 << 3)
#define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3)
#define RT5670_JD_TRI_HPO_SEL_SFT (0)
#define RT5670_JD_HPO_GPIO_JD1 (0x0)
#define RT5670_JD_HPO_JD1_1 (0x1)
#define RT5670_JD_HPO_JD1_2 (0x2)
#define RT5670_JD_HPO_JD2 (0x3)
#define RT5670_JD_HPO_JD3 (0x4)
#define RT5670_JD_HPO_GPIO_JD2 (0x5)
#define RT5670_JD_HPO_MX0B_12 (0x6)
/* Digital Misc Control (0xfa) */
#define RT5670_RST_DSP (0x1 << 13)
#define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
#define RT5670_IF1_ADC1_IN1_SFT 12
#define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
#define RT5670_IF1_ADC1_IN2_SFT 11
#define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
#define RT5670_IF1_ADC2_IN1_SFT 10
/* General Control2 (0xfb) */
#define RT5670_RXDC_SRC_MASK (0x1 << 7)
#define RT5670_RXDC_SRC_STO (0x0 << 7)
#define RT5670_RXDC_SRC_MONO (0x1 << 7)
#define RT5670_RXDC_SRC_SFT (7)
#define RT5670_RXDP2_SEL_MASK (0x1 << 3)
#define RT5670_RXDP2_SEL_IF2 (0x0 << 3)
#define RT5670_RXDP2_SEL_ADC (0x1 << 3)
#define RT5670_RXDP2_SEL_SFT (3)
/* System Clock Source */
enum {
RT5670_SCLK_S_MCLK,
RT5670_SCLK_S_PLL1,
RT5670_SCLK_S_RCCLK,
};
/* PLL1 Source */
enum {
RT5670_PLL1_S_MCLK,
RT5670_PLL1_S_BCLK1,
RT5670_PLL1_S_BCLK2,
RT5670_PLL1_S_BCLK3,
RT5670_PLL1_S_BCLK4,
};
enum {
RT5670_AIF1,
RT5670_AIF2,
RT5670_AIF3,
RT5670_AIF4,
RT5670_AIFS,
};
enum {
RT5670_DMIC_DATA_GPIO6,
RT5670_DMIC_DATA_IN2P,
RT5670_DMIC_DATA_GPIO7,
};
enum {
RT5670_DMIC_DATA_GPIO8,
RT5670_DMIC_DATA_IN3N,
};
enum {
RT5670_DMIC_DATA_GPIO9,
RT5670_DMIC_DATA_GPIO10,
RT5670_DMIC_DATA_GPIO5,
};
struct rt5670_priv {
struct snd_soc_codec *codec;
struct rt5670_platform_data pdata;
struct regmap *regmap;
int sysclk;
int sysclk_src;
int lrck[RT5670_AIFS];
int bclk[RT5670_AIFS];
int master[RT5670_AIFS];
int pll_src;
int pll_in;
int pll_out;
int dsp_sw; /* expected parameter setting */
int dsp_rate;
int jack_type;
};
#endif /* __RT5670_H__ */
sound/soc/codecs/rt5677.c
View file @ c1bd940a
......@@ -27,6 +27,7 @@
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5677.h"
#define RT5677_DEVICE_ID 0x6327
......@@ -604,19 +605,19 @@ static const struct snd_kcontrol_new rt5677_snd_controls[] = {
adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO3 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO4 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("Mono ADC Boost Gain", RT5677_ADC_BST_CTRL2,
SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
};
......@@ -636,21 +637,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
{
struct snd_soc_codec *codec = w->codec;
struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i;
int rate, red, bound, temp;
rate = rt5677->sysclk;
red = 3000000 * 12;
for (i = 0; i < ARRAY_SIZE(div); i++) {
bound = div[i] * 3000000;
if (rate > bound)
continue;
temp = bound - rate;
if (temp < red) {
red = temp;
idx = i;
}
}
int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
if (idx < 0)
dev_err(codec->dev, "Failed to set DMIC clock\n");
......@@ -951,7 +938,7 @@ static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
/* Mux */
/* DAC1 L/R source */ /* MX-29 [10:8] */
/* DAC1 L/R Source */ /* MX-29 [10:8] */
static const char * const rt5677_dac1_src[] = {
"IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
"OB 01"
......@@ -962,9 +949,9 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
static const struct snd_kcontrol_new rt5677_dac1_mux =
SOC_DAPM_ENUM("DAC1 source", rt5677_dac1_enum);
SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
/* ADDA1 L/R source */ /* MX-29 [1:0] */
/* ADDA1 L/R Source */ /* MX-29 [1:0] */
static const char * const rt5677_adda1_src[] = {
"STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
};
......@@ -974,10 +961,10 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
static const struct snd_kcontrol_new rt5677_adda1_mux =
SOC_DAPM_ENUM("ADDA1 source", rt5677_adda1_enum);
SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
static const char * const rt5677_dac2l_src[] = {
"IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
"OB 2",
......@@ -988,7 +975,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
static const struct snd_kcontrol_new rt5677_dac2_l_mux =
SOC_DAPM_ENUM("DAC2 L source", rt5677_dac2l_enum);
SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
static const char * const rt5677_dac2r_src[] = {
"IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
......@@ -1000,9 +987,9 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
static const struct snd_kcontrol_new rt5677_dac2_r_mux =
SOC_DAPM_ENUM("DAC2 R source", rt5677_dac2r_enum);
SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
/*DAC3 L/R source*/ /* MX-16 [6:4] [2:0] */
/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
static const char * const rt5677_dac3l_src[] = {
"IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
"SLB DAC 4", "OB 4"
......@@ -1013,7 +1000,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
static const struct snd_kcontrol_new rt5677_dac3_l_mux =
SOC_DAPM_ENUM("DAC3 L source", rt5677_dac3l_enum);
SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
static const char * const rt5677_dac3r_src[] = {
"IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
......@@ -1025,9 +1012,9 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
static const struct snd_kcontrol_new rt5677_dac3_r_mux =
SOC_DAPM_ENUM("DAC3 R source", rt5677_dac3r_enum);
SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
/*DAC4 L/R source*/ /* MX-16 [14:12] [10:8] */
/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
static const char * const rt5677_dac4l_src[] = {
"IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
"SLB DAC 6", "OB 6"
......@@ -1038,7 +1025,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
static const struct snd_kcontrol_new rt5677_dac4_l_mux =
SOC_DAPM_ENUM("DAC4 L source", rt5677_dac4l_enum);
SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
static const char * const rt5677_dac4r_src[] = {
"IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
......@@ -1050,7 +1037,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
static const struct snd_kcontrol_new rt5677_dac4_r_mux =
SOC_DAPM_ENUM("DAC4 R source", rt5677_dac4r_enum);
SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
static const char * const rt5677_iob_bypass_src[] = {
......@@ -1062,35 +1049,35 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
SOC_DAPM_ENUM("OB01 Bypass source", rt5677_ob01_bypass_src_enum);
SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
SOC_DAPM_ENUM("OB23 Bypass source", rt5677_ob23_bypass_src_enum);
SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
SOC_DAPM_ENUM("IB01 Bypass source", rt5677_ib01_bypass_src_enum);
SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
SOC_DAPM_ENUM("IB23 Bypass source", rt5677_ib23_bypass_src_enum);
SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
SOC_DAPM_ENUM("IB45 Bypass source", rt5677_ib45_bypass_src_enum);
SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
static const char * const rt5677_stereo_adc2_src[] = {
......@@ -1102,21 +1089,21 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5677_stereo1_adc2_enum);
SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5677_stereo2_adc2_enum);
SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
SOC_DAPM_ENUM("Stereo3 ADC2 source", rt5677_stereo3_adc2_enum);
SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
static const char * const rt5677_dmic_src[] = {
......@@ -1128,44 +1115,44 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC L source", rt5677_mono_dmic_l_enum);
SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC R source", rt5677_mono_dmic_r_enum);
SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC source", rt5677_stereo1_dmic_enum);
SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC source", rt5677_stereo2_dmic_enum);
SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
SOC_DAPM_ENUM("Stereo3 DMIC source", rt5677_stereo3_dmic_enum);
SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
SOC_DAPM_ENUM("Stereo4 DMIC source", rt5677_stereo4_dmic_enum);
SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
/* Stereo2 ADC source */ /* MX-26 [0] */
/* Stereo2 ADC Source */ /* MX-26 [0] */
static const char * const rt5677_stereo2_adc_lr_src[] = {
"L", "LR"
};
......@@ -1175,7 +1162,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5677_stereo2_adc_lr_enum);
SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
static const char * const rt5677_stereo_adc1_src[] = {
......@@ -1187,23 +1174,23 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5677_stereo1_adc1_enum);
SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5677_stereo2_adc1_enum);
SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
SOC_DAPM_ENUM("Stereo3 ADC1 source", rt5677_stereo3_adc1_enum);
SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
/* Mono ADC Left source 2 */ /* MX-28 [11:10] */
/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
static const char * const rt5677_mono_adc2_l_src[] = {
"DD MIX1L", "DMIC", "MONO DAC MIXL"
};
......@@ -1213,9 +1200,9 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
SOC_DAPM_ENUM("Mono ADC2 L source", rt5677_mono_adc2_l_enum);
SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
/* Mono ADC Left source 1 */ /* MX-28 [13:12] */
/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
static const char * const rt5677_mono_adc1_l_src[] = {
"DD MIX1L", "ADC1", "MONO DAC MIXL"
};
......@@ -1225,9 +1212,9 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
SOC_DAPM_ENUM("Mono ADC1 L source", rt5677_mono_adc1_l_enum);
SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
/* Mono ADC Right source 2 */ /* MX-28 [3:2] */
/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
static const char * const rt5677_mono_adc2_r_src[] = {
"DD MIX1R", "DMIC", "MONO DAC MIXR"
};
......@@ -1237,9 +1224,9 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
SOC_DAPM_ENUM("Mono ADC2 R source", rt5677_mono_adc2_r_enum);
SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
/* Mono ADC Right source 1 */ /* MX-28 [5:4] */
/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
static const char * const rt5677_mono_adc1_r_src[] = {
"DD MIX1R", "ADC2", "MONO DAC MIXR"
};
......@@ -1249,7 +1236,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
SOC_DAPM_ENUM("Mono ADC1 R source", rt5677_mono_adc1_r_enum);
SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
static const char * const rt5677_stereo4_adc2_src[] = {
......@@ -1261,7 +1248,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
SOC_DAPM_ENUM("Stereo4 ADC2 source", rt5677_stereo4_adc2_enum);
SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
......@@ -1274,7 +1261,7 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
SOC_DAPM_ENUM("Stereo4 ADC1 source", rt5677_stereo4_adc1_enum);
SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
/* InBound0/1 Source */ /* MX-A3 [14:12] */
static const char * const rt5677_inbound01_src[] = {
......@@ -1416,7 +1403,7 @@ static SOC_ENUM_SINGLE_DECL(
static const struct snd_kcontrol_new rt5677_dac3_mux =
SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
/* PDM channel source */ /* MX-31 [13:12][9:8][5:4][1:0] */
/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
static const char * const rt5677_pdm_src[] = {
"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
};
......@@ -1426,28 +1413,28 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_l_enum);
SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_l_enum);
SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_r_enum);
SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_r_enum);
SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
static const char * const rt5677_if12_adc1_src[] = {
......@@ -1459,21 +1446,21 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
SOC_DAPM_ENUM("IF1 ADC1 source", rt5677_if1_adc1_enum);
SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
SOC_DAPM_ENUM("IF2 ADC1 source", rt5677_if2_adc1_enum);
SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
SOC_DAPM_ENUM("SLB ADC1 source", rt5677_slb_adc1_enum);
SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
static const char * const rt5677_if12_adc2_src[] = {
......@@ -1485,21 +1472,21 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
SOC_DAPM_ENUM("IF1 ADC2 source", rt5677_if1_adc2_enum);
SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
SOC_DAPM_ENUM("IF2 ADC2 source", rt5677_if2_adc2_enum);
SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
SOC_DAPM_ENUM("SLB ADC2 source", rt5677_slb_adc2_enum);
SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
static const char * const rt5677_if12_adc3_src[] = {
......@@ -1511,21 +1498,21 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
SOC_DAPM_ENUM("IF1 ADC3 source", rt5677_if1_adc3_enum);
SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
SOC_DAPM_ENUM("IF2 ADC3 source", rt5677_if2_adc3_enum);
SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
SOC_DAPM_ENUM("SLB ADC3 source", rt5677_slb_adc3_enum);
SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
static const char * const rt5677_if12_adc4_src[] = {
......@@ -1537,21 +1524,21 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
SOC_DAPM_ENUM("IF1 ADC4 source", rt5677_if1_adc4_enum);
SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
SOC_DAPM_ENUM("IF2 ADC4 source", rt5677_if2_adc4_enum);
SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
SOC_DAPM_ENUM("SLB ADC4 source", rt5677_slb_adc4_enum);
SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
static const char * const rt5677_if34_adc_src[] = {
......@@ -1564,14 +1551,14 @@ static SOC_ENUM_SINGLE_DECL(
RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
static const struct snd_kcontrol_new rt5677_if3_adc_mux =
SOC_DAPM_ENUM("IF3 ADC source", rt5677_if3_adc_enum);
SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if4_adc_enum, RT5677_IF4_DATA,
RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
static const struct snd_kcontrol_new rt5677_if4_adc_mux =
SOC_DAPM_ENUM("IF4 ADC source", rt5677_if4_adc_enum);
SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
......@@ -1670,6 +1657,13 @@ static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
RT5677_PWR_CLK_MB, 0);
break;
default:
return 0;
}
......@@ -1685,8 +1679,9 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("micbias1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
0, rt5677_set_micbias1_event, SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
......@@ -2798,21 +2793,6 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
{ "PDM2R", NULL, "PDM2 R Mux" },
};
static int get_clk_info(int sclk, int rate)
{
int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
if (sclk <= 0 || rate <= 0)
return -EINVAL;
rate = rate << 8;
for (i = 0; i < ARRAY_SIZE(pd); i++)
if (sclk == rate * pd[i])
return i;
return -EINVAL;
}
static int rt5677_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
......@@ -2822,7 +2802,7 @@ static int rt5677_hw_params(struct snd_pcm_substream *substream,
int pre_div, bclk_ms, frame_size;
rt5677->lrck[dai->id] = params_rate(params);
pre_div = get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
if (pre_div < 0) {
dev_err(codec->dev, "Unsupported clock setting\n");
return -EINVAL;
......@@ -3016,62 +2996,12 @@ static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
* Returns 0 for success or negative error code.
*/
static int rt5677_pll_calc(const unsigned int freq_in,
const unsigned int freq_out, struct rt5677_pll_code *pll_code)
const unsigned int freq_out, struct rl6231_pll_code *pll_code)
{
int max_n = RT5677_PLL_N_MAX, max_m = RT5677_PLL_M_MAX;
int k, red, n_t, pll_out, in_t;
int n = 0, m = 0, m_t = 0;
int out_t, red_t = abs(freq_out - freq_in);
bool m_bp = false, k_bp = false;
if (RT5677_PLL_INP_MAX < freq_in || RT5677_PLL_INP_MIN > freq_in)
if (RT5677_PLL_INP_MIN > freq_in)
return -EINVAL;
k = 100000000 / freq_out - 2;
if (k > RT5677_PLL_K_MAX)
k = RT5677_PLL_K_MAX;
for (n_t = 0; n_t <= max_n; n_t++) {
in_t = freq_in / (k + 2);
pll_out = freq_out / (n_t + 2);
if (in_t < 0)
continue;
if (in_t == pll_out) {
m_bp = true;
n = n_t;
goto code_find;
}
red = abs(in_t - pll_out);
if (red < red_t) {
m_bp = true;
n = n_t;
m = m_t;
if (red == 0)
goto code_find;
red_t = red;
}
for (m_t = 0; m_t <= max_m; m_t++) {
out_t = in_t / (m_t + 2);
red = abs(out_t - pll_out);
if (red < red_t) {
m_bp = false;
n = n_t;
m = m_t;
if (red == 0)
goto code_find;
red_t = red;
}
}
}
pr_debug("Only get approximation about PLL\n");
code_find:
pll_code->m_bp = m_bp;
pll_code->k_bp = k_bp;
pll_code->m_code = m;
pll_code->n_code = n;
pll_code->k_code = k;
return 0;
return rl6231_pll_calc(freq_in, freq_out, pll_code);
}
static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
......@@ -3079,7 +3009,7 @@ static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
{
struct snd_soc_codec *codec = dai->codec;
struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
struct rt5677_pll_code pll_code;
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
......@@ -3137,15 +3067,12 @@ static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
return ret;
}
dev_dbg(codec->dev, "m_bypass=%d k_bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, pll_code.k_bp,
(pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
(pll_code.k_bp ? 0 : pll_code.k_code));
dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
pll_code.n_code << RT5677_PLL_N_SFT |
pll_code.k_bp << RT5677_PLL_K_BP_SFT |
(pll_code.k_bp ? 0 : pll_code.k_code));
pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
pll_code.m_bp << RT5677_PLL_M_BP_SFT);
......@@ -3197,7 +3124,7 @@ static int rt5677_set_bias_level(struct snd_soc_codec *codec,
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0000);
regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
......@@ -3454,14 +3381,8 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
regmap_update_bits(rt5677->regmap, RT5677_IN1,
RT5677_IN_DF2, RT5677_IN_DF2);
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
rt5677_dai, ARRAY_SIZE(rt5677_dai));
if (ret < 0)
goto err;
return 0;
err:
return ret;
}
static int rt5677_i2c_remove(struct i2c_client *i2c)
......@@ -3480,18 +3401,7 @@ static struct i2c_driver rt5677_i2c_driver = {
.remove = rt5677_i2c_remove,
.id_table = rt5677_i2c_id,
};
static int __init rt5677_modinit(void)
{
return i2c_add_driver(&rt5677_i2c_driver);
}
module_init(rt5677_modinit);
static void __exit rt5677_modexit(void)
{
i2c_del_driver(&rt5677_i2c_driver);
}
module_exit(rt5677_modexit);
module_i2c_driver(rt5677_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5677 driver");
MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
......
sound/soc/codecs/rt5677.h
View file @ c1bd940a
......@@ -1393,13 +1393,6 @@
#define RT5677_DSP_IB_9_L (0x1 << 1)
#define RT5677_DSP_IB_9_L_SFT 1
/* Debug String Length */
#define RT5677_REG_DISP_LEN 23
#define RT5677_NO_JACK BIT(0)
#define RT5677_HEADSET_DET BIT(1)
#define RT5677_HEADPHO_DET BIT(2)
/* System Clock Source */
enum {
RT5677_SCLK_S_MCLK,
......@@ -1425,14 +1418,6 @@ enum {
RT5677_AIFS,
};
struct rt5677_pll_code {
bool m_bp; /* Indicates bypass m code or not. */
bool k_bp; /* Indicates bypass k code or not. */
int m_code;
int n_code;
int k_code;
};
struct rt5677_priv {
struct snd_soc_codec *codec;
struct rt5677_platform_data pdata;
......
sound/soc/s6000/Kconfig
View file @ c1bd940a
config SND_S6000_SOC
tristate "SoC Audio for the Stretch s6000 family"
depends on XTENSA_VARIANT_S6000
depends on XTENSA_VARIANT_S6000 || COMPILE_TEST
depends on HAS_IOMEM
select SND_S6000_SOC_PCM if XTENSA_VARIANT_S6000
help
Say Y or M if you want to add support for codecs attached to
s6000 family chips. You will also need to select the platform
to support below.
config SND_S6000_SOC_PCM
tristate
config SND_S6000_SOC_I2S
tristate
config SND_S6000_SOC_S6IPCAM
tristate "SoC Audio support for Stretch 6105 IP Camera"
depends on SND_S6000_SOC && XTENSA_PLATFORM_S6105
bool "SoC Audio support for Stretch 6105 IP Camera"
depends on SND_S6000_SOC=y
depends on I2C=y
depends on XTENSA_PLATFORM_S6105 || COMPILE_TEST
select SND_S6000_SOC_I2S
select SND_SOC_TLV320AIC3X
help
......
sound/soc/s6000/Makefile
View file @ c1bd940a
......@@ -2,7 +2,7 @@
snd-soc-s6000-objs := s6000-pcm.o
snd-soc-s6000-i2s-objs := s6000-i2s.o
obj-$(CONFIG_SND_S6000_SOC) += snd-soc-s6000.o
obj-$(CONFIG_SND_S6000_SOC_PCM) += snd-soc-s6000.o
obj-$(CONFIG_SND_S6000_SOC_I2S) += snd-soc-s6000-i2s.o
# s6105 Machine Support
......
sound/soc/s6000/s6105-ipcam.c
View file @ c1bd940a
......@@ -19,8 +19,6 @@
#include <sound/pcm.h>
#include <sound/soc.h>
#include <variant/dmac.h>
#include "s6000-pcm.h"
#include "s6000-i2s.h"
......@@ -135,22 +133,8 @@ static const struct snd_kcontrol_new audio_out_mux = {
/* Logic for a aic3x as connected on the s6105 ip camera ref design */
static int s6105_aic3x_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_codec *codec = rtd->codec;
struct snd_soc_dapm_context *dapm = &codec->dapm;
struct snd_soc_card *card = rtd->card;
/* not present */
snd_soc_dapm_nc_pin(dapm, "MONO_LOUT");
snd_soc_dapm_nc_pin(dapm, "LINE2L");
snd_soc_dapm_nc_pin(dapm, "LINE2R");
/* not connected */
snd_soc_dapm_nc_pin(dapm, "MIC3L"); /* LINE2L on this chip */
snd_soc_dapm_nc_pin(dapm, "MIC3R"); /* LINE2R on this chip */
snd_soc_dapm_nc_pin(dapm, "LLOUT");
snd_soc_dapm_nc_pin(dapm, "RLOUT");
snd_soc_dapm_nc_pin(dapm, "HPRCOM");
/* must correspond to audio_out_mux.private_value initializer */
snd_soc_dapm_disable_pin(&card->dapm, "Audio Out Differential");
......@@ -182,6 +166,7 @@ static struct snd_soc_card snd_soc_card_s6105 = {
.num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
.dapm_routes = audio_map,
.num_dapm_routes = ARRAY_SIZE(audio_map),
.fully_routed = true,
};
static struct s6000_snd_platform_data s6105_snd_data __initdata = {
......
sound/soc/samsung/Kconfig
View file @ c1bd940a
config SND_SOC_SAMSUNG
tristate "ASoC support for Samsung"
depends on PLAT_SAMSUNG
select S3C2410_DMA if ARCH_S3C24XX
select S3C64XX_PL080 if ARCH_S3C64XX
select SND_S3C_DMA if !ARCH_S3C24XX
select SND_S3C_DMA_LEGACY if ARCH_S3C24XX
select SND_SOC_GENERIC_DMAENGINE_PCM if !ARCH_S3C24XX
depends on S3C64XX_PL080 || !ARCH_S3C64XX
depends on S3C24XX_DMAC || !ARCH_S3C24XX
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for codecs attached to
the Samsung SoCs' Audio interfaces. You will also need to
select the audio interfaces to support below.
config SND_S3C_DMA
tristate
config SND_S3C_DMA_LEGACY
tristate
config SND_S3C24XX_I2S
tristate
select S3C24XX_DMA
config SND_S3C_I2SV2_SOC
tristate
......@@ -27,7 +18,6 @@ config SND_S3C_I2SV2_SOC
config SND_S3C2412_SOC_I2S
tristate
select SND_S3C_I2SV2_SOC
select S3C2410_DMA
config SND_SAMSUNG_PCM
tristate
......@@ -55,7 +45,7 @@ config SND_SOC_SAMSUNG_NEO1973_WM8753
config SND_SOC_SAMSUNG_JIVE_WM8750
tristate "SoC I2S Audio support for Jive"
depends on SND_SOC_SAMSUNG && MACH_JIVE
depends on SND_SOC_SAMSUNG && MACH_JIVE && I2C
select SND_SOC_WM8750
select SND_S3C2412_SOC_I2S
help
......@@ -63,7 +53,7 @@ config SND_SOC_SAMSUNG_JIVE_WM8750
config SND_SOC_SAMSUNG_SMDK_WM8580
tristate "SoC I2S Audio support for WM8580 on SMDK"
depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDK6440 || MACH_SMDK6450 || MACH_SMDKV210 || MACH_SMDKC110)
depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDKV210 || MACH_SMDKC110)
depends on REGMAP_I2C
select SND_SOC_WM8580
select SND_SAMSUNG_I2S
......@@ -83,7 +73,6 @@ config SND_SOC_SAMSUNG_SMDK_WM8994
config SND_SOC_SAMSUNG_SMDK2443_WM9710
tristate "SoC AC97 Audio support for SMDK2443 - WM9710"
depends on SND_SOC_SAMSUNG && MACH_SMDK2443
select S3C2410_DMA
select AC97_BUS
select SND_SOC_AC97_CODEC
select SND_SAMSUNG_AC97
......@@ -94,7 +83,6 @@ config SND_SOC_SAMSUNG_SMDK2443_WM9710
config SND_SOC_SAMSUNG_LN2440SBC_ALC650
tristate "SoC AC97 Audio support for LN2440SBC - ALC650"
depends on SND_SOC_SAMSUNG && ARCH_S3C24XX
select S3C2410_DMA
select AC97_BUS
select SND_SOC_AC97_CODEC
select SND_SAMSUNG_AC97
......@@ -154,7 +142,7 @@ config SND_SOC_SAMSUNG_SMDK_WM9713
config SND_SOC_SMARTQ
tristate "SoC I2S Audio support for SmartQ board"
depends on SND_SOC_SAMSUNG && MACH_SMARTQ
depends on SND_SOC_SAMSUNG && MACH_SMARTQ && I2C
select SND_SAMSUNG_I2S
select SND_SOC_WM8750
......@@ -178,7 +166,7 @@ config SND_SOC_SAMSUNG_SMDK_SPDIF
config SND_SOC_SMDK_WM8580_PCM
tristate "SoC PCM Audio support for WM8580 on SMDK"
depends on SND_SOC_SAMSUNG && (MACH_SMDK6450 || MACH_SMDKV210 || MACH_SMDKC110)
depends on SND_SOC_SAMSUNG && (MACH_SMDKV210 || MACH_SMDKC110)
depends on REGMAP_I2C
select SND_SOC_WM8580
select SND_SAMSUNG_PCM
......@@ -206,7 +194,7 @@ config SND_SOC_SPEYSIDE
config SND_SOC_TOBERMORY
tristate "Audio support for Wolfson Tobermory"
depends on SND_SOC_SAMSUNG && MACH_WLF_CRAGG_6410 && INPUT
depends on SND_SOC_SAMSUNG && MACH_WLF_CRAGG_6410 && INPUT && I2C
select SND_SAMSUNG_I2S
select SND_SOC_WM8962
......@@ -222,7 +210,7 @@ config SND_SOC_BELLS
config SND_SOC_LOWLAND
tristate "Audio support for Wolfson Lowland"
depends on SND_SOC_SAMSUNG && MACH_WLF_CRAGG_6410
depends on SND_SOC_SAMSUNG && MACH_WLF_CRAGG_6410 && I2C
select SND_SAMSUNG_I2S
select SND_SOC_WM5100
select SND_SOC_WM9081
......@@ -236,10 +224,18 @@ config SND_SOC_LITTLEMILL
config SND_SOC_SNOW
tristate "Audio support for Google Snow boards"
depends on SND_SOC_SAMSUNG
depends on SND_SOC_SAMSUNG && I2C
select SND_SOC_MAX98090
select SND_SOC_MAX98095
select SND_SAMSUNG_I2S
help
Say Y if you want to add audio support for various Snow
boards based on Exynos5 series of SoCs.
config SND_SOC_ODROIDX2
tristate "Audio support for Odroid-X2 and Odroid-U3"
depends on SND_SOC_SAMSUNG
select SND_SOC_MAX98090
select SND_SAMSUNG_I2S
help
Say Y here to enable audio support for the Odroid-X2/U3.
sound/soc/samsung/Makefile
View file @ c1bd940a
# S3c24XX Platform Support
snd-soc-s3c-dma-objs := dmaengine.o
snd-soc-s3c-dma-legacy-objs := dma.o
snd-soc-idma-objs := idma.o
snd-soc-s3c24xx-i2s-objs := s3c24xx-i2s.o
snd-soc-s3c2412-i2s-objs := s3c2412-i2s.o
......@@ -10,8 +9,7 @@ snd-soc-samsung-spdif-objs := spdif.o
snd-soc-pcm-objs := pcm.o
snd-soc-i2s-objs := i2s.o
obj-$(CONFIG_SND_S3C_DMA) += snd-soc-s3c-dma.o
obj-$(CONFIG_SND_S3C_DMA_LEGACY) += snd-soc-s3c-dma-legacy.o
obj-$(CONFIG_SND_SOC_SAMSUNG) += snd-soc-s3c-dma.o
obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o
obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o
obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o
......@@ -46,6 +44,7 @@ snd-soc-tobermory-objs := tobermory.o
snd-soc-lowland-objs := lowland.o
snd-soc-littlemill-objs := littlemill.o
snd-soc-bells-objs := bells.o
snd-soc-odroidx2-max98090-objs := odroidx2_max98090.o
obj-$(CONFIG_SND_SOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o
obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
......@@ -71,3 +70,4 @@ obj-$(CONFIG_SND_SOC_TOBERMORY) += snd-soc-tobermory.o
obj-$(CONFIG_SND_SOC_LOWLAND) += snd-soc-lowland.o
obj-$(CONFIG_SND_SOC_LITTLEMILL) += snd-soc-littlemill.o
obj-$(CONFIG_SND_SOC_BELLS) += snd-soc-bells.o
obj-$(CONFIG_SND_SOC_ODROIDX2) += snd-soc-odroidx2-max98090.o
sound/soc/samsung/ac97.c
View file @ c1bd940a
......@@ -19,7 +19,6 @@
#include <sound/soc.h>
#include <mach/dma.h>
#include "regs-ac97.h"
#include <linux/platform_data/asoc-s3c.h>
......@@ -39,30 +38,15 @@ struct s3c_ac97_info {
};
static struct s3c_ac97_info s3c_ac97;
static struct s3c_dma_client s3c_dma_client_out = {
.name = "AC97 PCMOut"
};
static struct s3c_dma_client s3c_dma_client_in = {
.name = "AC97 PCMIn"
};
static struct s3c_dma_client s3c_dma_client_micin = {
.name = "AC97 MicIn"
};
static struct s3c_dma_params s3c_ac97_pcm_out = {
.client = &s3c_dma_client_out,
.dma_size = 4,
};
static struct s3c_dma_params s3c_ac97_pcm_in = {
.client = &s3c_dma_client_in,
.dma_size = 4,
};
static struct s3c_dma_params s3c_ac97_mic_in = {
.client = &s3c_dma_client_micin,
.dma_size = 4,
};
......@@ -225,9 +209,6 @@ static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
u32 ac_glbctrl;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct s3c_dma_params *dma_data =
snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
......@@ -253,11 +234,6 @@ static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
if (!dma_data->ops)
dma_data->ops = samsung_dma_get_ops();
dma_data->ops->started(dma_data->channel);
return 0;
}
......@@ -265,9 +241,6 @@ static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
u32 ac_glbctrl;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct s3c_dma_params *dma_data =
snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
......@@ -287,11 +260,6 @@ static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
if (!dma_data->ops)
dma_data->ops = samsung_dma_get_ops();
dma_data->ops->started(dma_data->channel);
return 0;
}
......
sound/soc/samsung/dma.c deleted 100644 → 0
View file @ b0ae27c4
/*
* dma.c -- ALSA Soc Audio Layer
*
* (c) 2006 Wolfson Microelectronics PLC.
* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
*
* Copyright 2004-2005 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <asm/dma.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include "dma.h"
#define ST_RUNNING (1<<0)
#define ST_OPENED (1<<1)
static const struct snd_pcm_hardware dma_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID,
.buffer_bytes_max = 128*1024,
.period_bytes_min = PAGE_SIZE,
.period_bytes_max = PAGE_SIZE*2,
.periods_min = 2,
.periods_max = 128,
.fifo_size = 32,
};
struct runtime_data {
spinlock_t lock;
int state;
unsigned int dma_loaded;
unsigned int dma_period;
dma_addr_t dma_start;
dma_addr_t dma_pos;
dma_addr_t dma_end;
struct s3c_dma_params *params;
};
static void audio_buffdone(void *data);
/* dma_enqueue
*
* place a dma buffer onto the queue for the dma system
* to handle.
*/
static void dma_enqueue(struct snd_pcm_substream *substream)
{
struct runtime_data *prtd = substream->runtime->private_data;
dma_addr_t pos = prtd->dma_pos;
unsigned int limit;
struct samsung_dma_prep dma_info;
pr_debug("Entered %s\n", __func__);
limit = (prtd->dma_end - prtd->dma_start) / prtd->dma_period;
pr_debug("%s: loaded %d, limit %d\n",
__func__, prtd->dma_loaded, limit);
dma_info.cap = (samsung_dma_has_circular() ? DMA_CYCLIC : DMA_SLAVE);
dma_info.direction =
(substream->stream == SNDRV_PCM_STREAM_PLAYBACK
? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
dma_info.fp = audio_buffdone;
dma_info.fp_param = substream;
dma_info.period = prtd->dma_period;
dma_info.len = prtd->dma_period*limit;
if (dma_info.cap == DMA_CYCLIC) {
dma_info.buf = pos;
prtd->params->ops->prepare(prtd->params->ch, &dma_info);
prtd->dma_loaded += limit;
return;
}
while (prtd->dma_loaded < limit) {
pr_debug("dma_loaded: %d\n", prtd->dma_loaded);
if ((pos + dma_info.period) > prtd->dma_end) {
dma_info.period = prtd->dma_end - pos;
pr_debug("%s: corrected dma len %ld\n",
__func__, dma_info.period);
}
dma_info.buf = pos;
prtd->params->ops->prepare(prtd->params->ch, &dma_info);
prtd->dma_loaded++;
pos += prtd->dma_period;
if (pos >= prtd->dma_end)
pos = prtd->dma_start;
}
prtd->dma_pos = pos;
}
static void audio_buffdone(void *data)
{
struct snd_pcm_substream *substream = data;
struct runtime_data *prtd = substream->runtime->private_data;
pr_debug("Entered %s\n", __func__);
if (prtd->state & ST_RUNNING) {
prtd->dma_pos += prtd->dma_period;
if (prtd->dma_pos >= prtd->dma_end)
prtd->dma_pos = prtd->dma_start;
if (substream)
snd_pcm_period_elapsed(substream);
spin_lock(&prtd->lock);
if (!samsung_dma_has_circular()) {
prtd->dma_loaded--;
dma_enqueue(substream);
}
spin_unlock(&prtd->lock);
}
}
static int dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct runtime_data *prtd = runtime->private_data;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
unsigned long totbytes = params_buffer_bytes(params);
struct s3c_dma_params *dma =
snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
struct samsung_dma_req req;
struct samsung_dma_config config;
pr_debug("Entered %s\n", __func__);
/* return if this is a bufferless transfer e.g.
* codec <--> BT codec or GSM modem -- lg FIXME */
if (!dma)
return 0;
/* this may get called several times by oss emulation
* with different params -HW */
if (prtd->params == NULL) {
/* prepare DMA */
prtd->params = dma;
pr_debug("params %p, client %p, channel %d\n", prtd->params,
prtd->params->client, prtd->params->channel);
prtd->params->ops = samsung_dma_get_ops();
req.cap = (samsung_dma_has_circular() ?
DMA_CYCLIC : DMA_SLAVE);
req.client = prtd->params->client;
config.direction =
(substream->stream == SNDRV_PCM_STREAM_PLAYBACK
? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
config.width = prtd->params->dma_size;
config.fifo = prtd->params->dma_addr;
prtd->params->ch = prtd->params->ops->request(
prtd->params->channel, &req, rtd->cpu_dai->dev,
prtd->params->ch_name);
if (!prtd->params->ch) {
pr_err("Failed to allocate DMA channel\n");
return -ENXIO;
}
prtd->params->ops->config(prtd->params->ch, &config);
}
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
runtime->dma_bytes = totbytes;
spin_lock_irq(&prtd->lock);
prtd->dma_loaded = 0;
prtd->dma_period = params_period_bytes(params);
prtd->dma_start = runtime->dma_addr;
prtd->dma_pos = prtd->dma_start;
prtd->dma_end = prtd->dma_start + totbytes;
spin_unlock_irq(&prtd->lock);
return 0;
}
static int dma_hw_free(struct snd_pcm_substream *substream)
{
struct runtime_data *prtd = substream->runtime->private_data;
pr_debug("Entered %s\n", __func__);
snd_pcm_set_runtime_buffer(substream, NULL);
if (prtd->params) {
prtd->params->ops->flush(prtd->params->ch);
prtd->params->ops->release(prtd->params->ch,
prtd->params->client);
prtd->params = NULL;
}
return 0;
}
static int dma_prepare(struct snd_pcm_substream *substream)
{
struct runtime_data *prtd = substream->runtime->private_data;
int ret = 0;
pr_debug("Entered %s\n", __func__);
/* return if this is a bufferless transfer e.g.
* codec <--> BT codec or GSM modem -- lg FIXME */
if (!prtd->params)
return 0;
/* flush the DMA channel */
prtd->params->ops->flush(prtd->params->ch);
prtd->dma_loaded = 0;
prtd->dma_pos = prtd->dma_start;
/* enqueue dma buffers */
dma_enqueue(substream);
return ret;
}
static int dma_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct runtime_data *prtd = substream->runtime->private_data;
int ret = 0;
pr_debug("Entered %s\n", __func__);
spin_lock(&prtd->lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
prtd->state |= ST_RUNNING;
prtd->params->ops->trigger(prtd->params->ch);
break;
case SNDRV_PCM_TRIGGER_STOP:
prtd->state &= ~ST_RUNNING;
prtd->params->ops->stop(prtd->params->ch);
break;
default:
ret = -EINVAL;
break;
}
spin_unlock(&prtd->lock);
return ret;
}
static snd_pcm_uframes_t
dma_pointer(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct runtime_data *prtd = runtime->private_data;
unsigned long res;
pr_debug("Entered %s\n", __func__);
res = prtd->dma_pos - prtd->dma_start;
pr_debug("Pointer offset: %lu\n", res);
/* we seem to be getting the odd error from the pcm library due
* to out-of-bounds pointers. this is maybe due to the dma engine
* not having loaded the new values for the channel before being
* called... (todo - fix )
*/
if (res >= snd_pcm_lib_buffer_bytes(substream)) {
if (res == snd_pcm_lib_buffer_bytes(substream))
res = 0;
}
return bytes_to_frames(substream->runtime, res);
}
static int dma_open(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct runtime_data *prtd;
pr_debug("Entered %s\n", __func__);
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
snd_soc_set_runtime_hwparams(substream, &dma_hardware);
prtd = kzalloc(sizeof(struct runtime_data), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
spin_lock_init(&prtd->lock);
runtime->private_data = prtd;
return 0;
}
static int dma_close(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct runtime_data *prtd = runtime->private_data;
pr_debug("Entered %s\n", __func__);
if (!prtd)
pr_debug("dma_close called with prtd == NULL\n");
kfree(prtd);
return 0;
}
static int dma_mmap(struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
struct snd_pcm_runtime *runtime = substream->runtime;
pr_debug("Entered %s\n", __func__);
return dma_mmap_writecombine(substream->pcm->card->dev, vma,
runtime->dma_area,
runtime->dma_addr,
runtime->dma_bytes);
}
static struct snd_pcm_ops dma_ops = {
.open = dma_open,
.close = dma_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = dma_hw_params,
.hw_free = dma_hw_free,
.prepare = dma_prepare,
.trigger = dma_trigger,
.pointer = dma_pointer,
.mmap = dma_mmap,
};
static int preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
struct snd_pcm_substream *substream = pcm->streams[stream].substream;
struct snd_dma_buffer *buf = &substream->dma_buffer;
size_t size = dma_hardware.buffer_bytes_max;
pr_debug("Entered %s\n", __func__);
buf->dev.type = SNDRV_DMA_TYPE_DEV;
buf->dev.dev = pcm->card->dev;
buf->private_data = NULL;
buf->area = dma_alloc_writecombine(pcm->card->dev, size,
&buf->addr, GFP_KERNEL);
if (!buf->area)
return -ENOMEM;
buf->bytes = size;
return 0;
}
static void dma_free_dma_buffers(struct snd_pcm *pcm)
{
struct snd_pcm_substream *substream;
struct snd_dma_buffer *buf;
int stream;
pr_debug("Entered %s\n", __func__);
for (stream = 0; stream < 2; stream++) {
substream = pcm->streams[stream].substream;
if (!substream)
continue;
buf = &substream->dma_buffer;
if (!buf->area)
continue;
dma_free_writecombine(pcm->card->dev, buf->bytes,
buf->area, buf->addr);
buf->area = NULL;
}
}
static int dma_new(struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
pr_debug("Entered %s\n", __func__);
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
ret = preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_PLAYBACK);
if (ret)
goto out;
}
if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
ret = preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_CAPTURE);
if (ret)
goto out;
}
out:
return ret;
}
static struct snd_soc_platform_driver samsung_asoc_platform = {
.ops = &dma_ops,
.pcm_new = dma_new,
.pcm_free = dma_free_dma_buffers,
};
void samsung_asoc_init_dma_data(struct snd_soc_dai *dai,
struct s3c_dma_params *playback,
struct s3c_dma_params *capture)
{
snd_soc_dai_init_dma_data(dai, playback, capture);
}
EXPORT_SYMBOL_GPL(samsung_asoc_init_dma_data);
int samsung_asoc_dma_platform_register(struct device *dev)
{
return devm_snd_soc_register_platform(dev, &samsung_asoc_platform);
}
EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_register);
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("Samsung ASoC DMA Driver");
MODULE_LICENSE("GPL");
sound/soc/samsung/dma.h
View file @ c1bd940a
......@@ -14,17 +14,10 @@
#include <sound/dmaengine_pcm.h>
struct s3c_dma_client {
char *name;
};
struct s3c_dma_params {
struct s3c_dma_client *client; /* stream identifier */
int channel; /* Channel ID */
dma_addr_t dma_addr;
int dma_size; /* Size of the DMA transfer */
unsigned ch;
struct samsung_dma_ops *ops;
char *ch_name;
struct snd_dmaengine_dai_dma_data dma_data;
};
......
sound/soc/samsung/dmaengine.c
View file @ c1bd940a
......@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/amba/pl08x.h>
#include <linux/platform_data/dma-s3c24xx.h>
#include <sound/core.h>
#include <sound/pcm.h>
......@@ -29,6 +30,8 @@
#ifdef CONFIG_ARCH_S3C64XX
#define filter_fn pl08x_filter_id
#elif defined(CONFIG_ARCH_S3C24XX)
#define filter_fn s3c24xx_dma_filter
#else
#define filter_fn NULL
#endif
......
sound/soc/samsung/i2s.c
View file @ c1bd940a
......@@ -1221,11 +1221,7 @@ static int samsung_i2s_probe(struct platform_device *pdev)
pri_dai->dma_playback.dma_addr = regs_base + I2STXD;
pri_dai->dma_capture.dma_addr = regs_base + I2SRXD;
pri_dai->dma_playback.client =
(struct s3c_dma_client *)&pri_dai->dma_playback;
pri_dai->dma_playback.ch_name = "tx";
pri_dai->dma_capture.client =
(struct s3c_dma_client *)&pri_dai->dma_capture;
pri_dai->dma_capture.ch_name = "rx";
pri_dai->dma_playback.dma_size = 4;
pri_dai->dma_capture.dma_size = 4;
......@@ -1243,8 +1239,6 @@ static int samsung_i2s_probe(struct platform_device *pdev)
goto err;
}
sec_dai->dma_playback.dma_addr = regs_base + I2STXDS;
sec_dai->dma_playback.client =
(struct s3c_dma_client *)&sec_dai->dma_playback;
sec_dai->dma_playback.ch_name = "tx-sec";
if (!np) {
......
sound/soc/samsung/idma.c
View file @ c1bd940a
......@@ -261,10 +261,9 @@ static int idma_mmap(struct snd_pcm_substream *substream,
static irqreturn_t iis_irq(int irqno, void *dev_id)
{
struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id;
u32 iiscon, iisahb, val, addr;
u32 iisahb, val, addr;
iisahb = readl(idma.regs + I2SAHB);
iiscon = readl(idma.regs + I2SCON);
val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0;
......
sound/soc/samsung/odroidx2_max98090.c 0 → 100644
View file @ c1bd940a
/*
* Copyright (C) 2014 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/of.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "i2s.h"
struct odroidx2_drv_data {
const struct snd_soc_dapm_widget *dapm_widgets;
unsigned int num_dapm_widgets;
};
/* The I2S CDCLK output clock frequency for the MAX98090 codec */
#define MAX98090_MCLK 19200000
static int odroidx2_late_probe(struct snd_soc_card *card)
{
struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
struct snd_soc_dai *cpu_dai = card->rtd[0].cpu_dai;
int ret;
ret = snd_soc_dai_set_sysclk(codec_dai, 0, MAX98090_MCLK,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
/* Set the cpu DAI configuration in order to use CDCLK */
return snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK,
0, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_dapm_widget odroidx2_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_MIC("DMIC", NULL),
};
static const struct snd_soc_dapm_widget odroidu3_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
};
static struct snd_soc_dai_link odroidx2_dai[] = {
{
.name = "MAX98090",
.stream_name = "MAX98090 PCM",
.codec_dai_name = "HiFi",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
}
};
static struct snd_soc_card odroidx2 = {
.owner = THIS_MODULE,
.dai_link = odroidx2_dai,
.num_links = ARRAY_SIZE(odroidx2_dai),
.fully_routed = true,
.late_probe = odroidx2_late_probe,
};
struct odroidx2_drv_data odroidx2_drvdata = {
.dapm_widgets = odroidx2_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(odroidx2_dapm_widgets),
};
struct odroidx2_drv_data odroidu3_drvdata = {
.dapm_widgets = odroidu3_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(odroidu3_dapm_widgets),
};
static const struct of_device_id odroidx2_audio_of_match[] = {
{
.compatible = "samsung,odroidx2-audio",
.data = &odroidx2_drvdata,
}, {
.compatible = "samsung,odroidu3-audio",
.data = &odroidu3_drvdata,
},
{ },
};
MODULE_DEVICE_TABLE(of, odroidx2_audio_of_match);
static int odroidx2_audio_probe(struct platform_device *pdev)
{
struct device_node *snd_node = pdev->dev.of_node;
struct snd_soc_card *card = &odroidx2;
struct device_node *i2s_node, *codec_node;
struct odroidx2_drv_data *dd;
const struct of_device_id *of_id;
int ret;
of_id = of_match_node(odroidx2_audio_of_match, snd_node);
dd = (struct odroidx2_drv_data *)of_id->data;
card->num_dapm_widgets = dd->num_dapm_widgets;
card->dapm_widgets = dd->dapm_widgets;
card->dev = &pdev->dev;
ret = snd_soc_of_parse_card_name(card, "samsung,model");
if (ret < 0)
return ret;
ret = snd_soc_of_parse_audio_routing(card, "samsung,audio-routing");
if (ret < 0)
return ret;
codec_node = of_parse_phandle(snd_node, "samsung,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Failed parsing samsung,i2s-codec property\n");
return -EINVAL;
}
i2s_node = of_parse_phandle(snd_node, "samsung,i2s-controller", 0);
if (!i2s_node) {
dev_err(&pdev->dev,
"Failed parsing samsung,i2s-controller property\n");
ret = -EINVAL;
goto err_put_codec_n;
}
odroidx2_dai[0].codec_of_node = codec_node;
odroidx2_dai[0].cpu_of_node = i2s_node;
odroidx2_dai[0].platform_of_node = i2s_node;
ret = snd_soc_register_card(card);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
ret);
goto err_put_i2s_n;
}
return 0;
err_put_i2s_n:
of_node_put(i2s_node);
err_put_codec_n:
of_node_put(codec_node);
return ret;
}
static int odroidx2_audio_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
snd_soc_unregister_card(card);
of_node_put((struct device_node *)odroidx2_dai[0].cpu_of_node);
of_node_put((struct device_node *)odroidx2_dai[0].codec_of_node);
return 0;
}
static struct platform_driver odroidx2_audio_driver = {
.driver = {
.name = "odroidx2-audio",
.owner = THIS_MODULE,
.of_match_table = odroidx2_audio_of_match,
.pm = &snd_soc_pm_ops,
},
.probe = odroidx2_audio_probe,
.remove = odroidx2_audio_remove,
};
module_platform_driver(odroidx2_audio_driver);
MODULE_AUTHOR("Chen Zhen <zhen1.chen@samsung.com>");
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
MODULE_DESCRIPTION("ALSA SoC Odroid X2/U3 Audio Support");
MODULE_LICENSE("GPL v2");
sound/soc/samsung/pcm.c
View file @ c1bd940a
......@@ -131,32 +131,20 @@ struct s3c_pcm_info {
struct s3c_dma_params *dma_capture;
};
static struct s3c_dma_client s3c_pcm_dma_client_out = {
.name = "PCM Stereo out"
};
static struct s3c_dma_client s3c_pcm_dma_client_in = {
.name = "PCM Stereo in"
};
static struct s3c_dma_params s3c_pcm_stereo_out[] = {
[0] = {
.client = &s3c_pcm_dma_client_out,
.dma_size = 4,
},
[1] = {
.client = &s3c_pcm_dma_client_out,
.dma_size = 4,
},
};
static struct s3c_dma_params s3c_pcm_stereo_in[] = {
[0] = {
.client = &s3c_pcm_dma_client_in,
.dma_size = 4,
},
[1] = {
.client = &s3c_pcm_dma_client_in,
.dma_size = 4,
},
};
......
sound/soc/samsung/s3c-i2s-v2.c
View file @ c1bd940a
......@@ -22,8 +22,6 @@
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <mach/dma.h>
#include "regs-i2s-v2.h"
#include "s3c-i2s-v2.h"
#include "dma.h"
......@@ -392,8 +390,6 @@ static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
unsigned long irqs;
int ret = 0;
struct s3c_dma_params *dma_data =
snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
pr_debug("Entered %s\n", __func__);
......@@ -424,13 +420,6 @@ static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
local_irq_restore(irqs);
/*
* Load the next buffer to DMA to meet the reqirement
* of the auto reload mechanism of S3C24XX.
* This call won't bother S3C64XX.
*/
s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
break;
case SNDRV_PCM_TRIGGER_STOP:
......@@ -644,12 +633,6 @@ int s3c_i2sv2_probe(struct snd_soc_dai *dai,
/* record our i2s structure for later use in the callbacks */
snd_soc_dai_set_drvdata(dai, i2s);
i2s->regs = ioremap(base, 0x100);
if (i2s->regs == NULL) {
dev_err(dev, "cannot ioremap registers\n");
return -ENXIO;
}
i2s->iis_pclk = clk_get(dev, "iis");
if (IS_ERR(i2s->iis_pclk)) {
dev_err(dev, "failed to get iis_clock\n");
......@@ -729,7 +712,7 @@ int s3c_i2sv2_register_component(struct device *dev, int id,
struct snd_soc_component_driver *cmp_drv,
struct snd_soc_dai_driver *dai_drv)
{
struct snd_soc_dai_ops *ops = dai_drv->ops;
struct snd_soc_dai_ops *ops = (struct snd_soc_dai_ops *)dai_drv->ops;
ops->trigger = s3c2412_i2s_trigger;
if (!ops->hw_params)
......
sound/soc/samsung/s3c2412-i2s.c
View file @ c1bd940a
......@@ -33,25 +33,15 @@
#include "regs-i2s-v2.h"
#include "s3c2412-i2s.h"
static struct s3c_dma_client s3c2412_dma_client_out = {
.name = "I2S PCM Stereo out"
};
static struct s3c_dma_client s3c2412_dma_client_in = {
.name = "I2S PCM Stereo in"
};
static struct s3c_dma_params s3c2412_i2s_pcm_stereo_out = {
.client = &s3c2412_dma_client_out,
.channel = DMACH_I2S_OUT,
.dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD,
.ch_name = "tx",
.dma_size = 4,
};
static struct s3c_dma_params s3c2412_i2s_pcm_stereo_in = {
.client = &s3c2412_dma_client_in,
.channel = DMACH_I2S_IN,
.dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD,
.ch_name = "rx",
.dma_size = 4,
};
......@@ -63,6 +53,9 @@ static int s3c2412_i2s_probe(struct snd_soc_dai *dai)
pr_debug("Entered %s\n", __func__);
samsung_asoc_init_dma_data(dai, &s3c2412_i2s_pcm_stereo_out,
&s3c2412_i2s_pcm_stereo_in);
ret = s3c_i2sv2_probe(dai, &s3c2412_i2s, S3C2410_PA_IIS);
if (ret)
return ret;
......@@ -70,17 +63,16 @@ static int s3c2412_i2s_probe(struct snd_soc_dai *dai)
s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in;
s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out;
s3c2412_i2s.iis_cclk = clk_get(dai->dev, "i2sclk");
s3c2412_i2s.iis_cclk = devm_clk_get(dai->dev, "i2sclk");
if (IS_ERR(s3c2412_i2s.iis_cclk)) {
pr_err("failed to get i2sclk clock\n");
iounmap(s3c2412_i2s.regs);
return PTR_ERR(s3c2412_i2s.iis_cclk);
}
/* Set MPLL as the source for IIS CLK */
clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
clk_enable(s3c2412_i2s.iis_cclk);
clk_prepare_enable(s3c2412_i2s.iis_cclk);
s3c2412_i2s.iis_cclk = s3c2412_i2s.iis_pclk;
......@@ -93,9 +85,7 @@ static int s3c2412_i2s_probe(struct snd_soc_dai *dai)
static int s3c2412_i2s_remove(struct snd_soc_dai *dai)
{
clk_disable(s3c2412_i2s.iis_cclk);
clk_put(s3c2412_i2s.iis_cclk);
iounmap(s3c2412_i2s.regs);
clk_disable_unprepare(s3c2412_i2s.iis_cclk);
return 0;
}
......@@ -105,18 +95,10 @@ static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct s3c_i2sv2_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
struct s3c_dma_params *dma_data;
u32 iismod;
pr_debug("Entered %s\n", __func__);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = i2s->dma_playback;
else
dma_data = i2s->dma_capture;
snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
iismod = readl(i2s->regs + S3C2412_IISMOD);
pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
......@@ -169,6 +151,15 @@ static const struct snd_soc_component_driver s3c2412_i2s_component = {
static int s3c2412_iis_dev_probe(struct platform_device *pdev)
{
int ret = 0;
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
s3c2412_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(s3c2412_i2s.regs))
return PTR_ERR(s3c2412_i2s.regs);
s3c2412_i2s_pcm_stereo_out.dma_addr = res->start + S3C2412_IISTXD;
s3c2412_i2s_pcm_stereo_in.dma_addr = res->start + S3C2412_IISRXD;
ret = s3c_i2sv2_register_component(&pdev->dev, -1,
&s3c2412_i2s_component,
......
sound/soc/samsung/s3c24xx-i2s.c
View file @ c1bd940a
......@@ -31,25 +31,15 @@
#include "dma.h"
#include "s3c24xx-i2s.h"
static struct s3c_dma_client s3c24xx_dma_client_out = {
.name = "I2S PCM Stereo out"
};
static struct s3c_dma_client s3c24xx_dma_client_in = {
.name = "I2S PCM Stereo in"
};
static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
.client = &s3c24xx_dma_client_out,
.channel = DMACH_I2S_OUT,
.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
.ch_name = "tx",
.dma_size = 2,
};
static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
.client = &s3c24xx_dma_client_in,
.channel = DMACH_I2S_IN,
.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
.ch_name = "rx",
.dma_size = 2,
};
......@@ -231,18 +221,12 @@ static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct s3c_dma_params *dma_data;
struct snd_dmaengine_dai_dma_data *dma_data;
u32 iismod;
pr_debug("Entered %s\n", __func__);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = &s3c24xx_i2s_pcm_stereo_out;
else
dma_data = &s3c24xx_i2s_pcm_stereo_in;
snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
dma_data = snd_soc_dai_get_dma_data(dai, substream);
/* Working copies of register */
iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
......@@ -251,11 +235,11 @@ static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
switch (params_width(params)) {
case 8:
iismod &= ~S3C2410_IISMOD_16BIT;
dma_data->dma_size = 1;
dma_data->addr_width = 1;
break;
case 16:
iismod |= S3C2410_IISMOD_16BIT;
dma_data->dma_size = 2;
dma_data->addr_width = 2;
break;
default:
return -EINVAL;
......@@ -270,8 +254,6 @@ static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int ret = 0;
struct s3c_dma_params *dma_data =
snd_soc_dai_get_dma_data(dai, substream);
pr_debug("Entered %s\n", __func__);
......@@ -290,7 +272,6 @@ static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
else
s3c24xx_snd_txctrl(1);
s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
......@@ -380,17 +361,15 @@ static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
{
pr_debug("Entered %s\n", __func__);
s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
if (s3c24xx_i2s.regs == NULL)
return -ENXIO;
samsung_asoc_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
&s3c24xx_i2s_pcm_stereo_in);
s3c24xx_i2s.iis_clk = clk_get(dai->dev, "iis");
s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
if (IS_ERR(s3c24xx_i2s.iis_clk)) {
pr_err("failed to get iis_clock\n");
iounmap(s3c24xx_i2s.regs);
return PTR_ERR(s3c24xx_i2s.iis_clk);
}
clk_enable(s3c24xx_i2s.iis_clk);
clk_prepare_enable(s3c24xx_i2s.iis_clk);
/* Configure the I2S pins (GPE0...GPE4) in correct mode */
s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
......@@ -414,7 +393,7 @@ static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
clk_disable(s3c24xx_i2s.iis_clk);
clk_disable_unprepare(s3c24xx_i2s.iis_clk);
return 0;
}
......@@ -422,7 +401,7 @@ static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
{
pr_debug("Entered %s\n", __func__);
clk_enable(s3c24xx_i2s.iis_clk);
clk_prepare_enable(s3c24xx_i2s.iis_clk);
writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
......@@ -474,6 +453,19 @@ static const struct snd_soc_component_driver s3c24xx_i2s_component = {
static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
{
int ret = 0;
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Can't get IO resource.\n");
return -ENOENT;
}
s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
if (s3c24xx_i2s.regs == NULL)
return -ENXIO;
s3c24xx_i2s_pcm_stereo_out.dma_addr = res->start + S3C2410_IISFIFO;
s3c24xx_i2s_pcm_stereo_in.dma_addr = res->start + S3C2410_IISFIFO;
ret = devm_snd_soc_register_component(&pdev->dev,
&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
......
sound/soc/samsung/smdk_wm8580pcm.c
View file @ c1bd940a
......@@ -25,7 +25,7 @@
* o '0' means 'OFF'
* o 'X' means 'Don't care'
*
* SMDK6410, SMDK6440, SMDK6450 Base B/D: CFG1-0000, CFG2-1111
* SMDK6410 Base B/D: CFG1-0000, CFG2-1111
* SMDKC110, SMDKV210: CFGB11-100100, CFGB12-0000
*/
......
sound/soc/samsung/snow.c
View file @ c1bd940a
......@@ -92,6 +92,9 @@ static int snow_probe(struct platform_device *pdev)
card->dev = &pdev->dev;
/* Update card-name if provided through DT, else use default name */
snd_soc_of_parse_card_name(card, "samsung,model");
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
......@@ -103,6 +106,7 @@ static int snow_probe(struct platform_device *pdev)
static const struct of_device_id snow_of_match[] = {
{ .compatible = "google,snow-audio-max98090", },
{ .compatible = "google,snow-audio-max98091", },
{ .compatible = "google,snow-audio-max98095", },
{},
};
......
sound/soc/samsung/spdif.c
View file @ c1bd940a
......@@ -93,10 +93,6 @@ struct samsung_spdif_info {
struct s3c_dma_params *dma_playback;
};
static struct s3c_dma_client spdif_dma_client_out = {
.name = "S/PDIF Stereo out",
};
static struct s3c_dma_params spdif_stereo_out;
static struct samsung_spdif_info spdif_info;
......@@ -435,7 +431,6 @@ static int spdif_probe(struct platform_device *pdev)
}
spdif_stereo_out.dma_size = 2;
spdif_stereo_out.client = &spdif_dma_client_out;
spdif_stereo_out.dma_addr = mem_res->start + DATA_OUTBUF;
spdif_stereo_out.channel = dma_res->start;
......
sound/soc/sh/fsi.c
View file @ c1bd940a
......@@ -260,12 +260,12 @@ struct fsi_priv {
u32 fmt;
int chan_num:16;
int clk_master:1;
int clk_cpg:1;
int spdif:1;
int enable_stream:1;
int bit_clk_inv:1;
int lr_clk_inv:1;
unsigned int clk_master:1;
unsigned int clk_cpg:1;
unsigned int spdif:1;
unsigned int enable_stream:1;
unsigned int bit_clk_inv:1;
unsigned int lr_clk_inv:1;
};
struct fsi_stream_handler {
......
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