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Commit c2974933 authored by Antonio Borneo's avatar Antonio Borneo Committed by Marc Zyngier
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irqchip/stm32-exti: Simplify irq description table 

Having removed the event trigger type from struct stm32_desc_irq
makes worthless keep using a struct.

Replace the struct by a single dimension array and use 8 bit type
to reduce the overal memory footprint.
On armv7a this patch reduces by 7% the size of the driver, from
   text    data     bss     dec     hex filename
   6977     424       4    7405    1ced irq-stm32-exti.o
to
   6449     424       4    6877    1add irq-stm32-exti.o
Signed-off-by: default avatarAntonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220606162757.415354-7-antonio.borneo@foss.st.com
parent ce4ef8f9
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Inline Side-by-side
Showing with 101 additions and 119 deletions
drivers/irqchip/irq-stm32-exti.c
View file @ c2974933
...@@ -39,16 +39,10 @@ struct stm32_exti_bank { ...@@ -39,16 +39,10 @@ struct stm32_exti_bank {
#define UNDEF_REG ~0 #define UNDEF_REG ~0
struct stm32_desc_irq {
u32 exti;
u32 irq_parent;
};
struct stm32_exti_drv_data { struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks; const struct stm32_exti_bank **exti_banks;
const struct stm32_desc_irq *desc_irqs; const u8 *desc_irqs;
u32 bank_nr; u32 bank_nr;
u32 irq_nr;
}; };
struct stm32_exti_chip_data { struct stm32_exti_chip_data {
...@@ -176,126 +170,114 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { ...@@ -176,126 +170,114 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
static struct irq_chip stm32_exti_h_chip; static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct; static struct irq_chip stm32_exti_h_chip_direct;
static const struct stm32_desc_irq stm32mp1_desc_irq[] = { #define EXTI_INVALID_IRQ U8_MAX
{ .exti = 0, .irq_parent = 6 }, #define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
{ .exti = 1, .irq_parent = 7 },
{ .exti = 2, .irq_parent = 8 }, static const u8 stm32mp1_desc_irq[] = {
{ .exti = 3, .irq_parent = 9 }, /* default value */
{ .exti = 4, .irq_parent = 10 }, [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
{ .exti = 5, .irq_parent = 23 },
{ .exti = 6, .irq_parent = 64 }, [0] = 6,
{ .exti = 7, .irq_parent = 65 }, [1] = 7,
{ .exti = 8, .irq_parent = 66 }, [2] = 8,
{ .exti = 9, .irq_parent = 67 }, [3] = 9,
{ .exti = 10, .irq_parent = 40 }, [4] = 10,
{ .exti = 11, .irq_parent = 42 }, [5] = 23,
{ .exti = 12, .irq_parent = 76 }, [6] = 64,
{ .exti = 13, .irq_parent = 77 }, [7] = 65,
{ .exti = 14, .irq_parent = 121 }, [8] = 66,
{ .exti = 15, .irq_parent = 127 }, [9] = 67,
{ .exti = 16, .irq_parent = 1 }, [10] = 40,
{ .exti = 19, .irq_parent = 3 }, [11] = 42,
{ .exti = 21, .irq_parent = 31 }, [12] = 76,
{ .exti = 22, .irq_parent = 33 }, [13] = 77,
{ .exti = 23, .irq_parent = 72 }, [14] = 121,
{ .exti = 24, .irq_parent = 95 }, [15] = 127,
{ .exti = 25, .irq_parent = 107 }, [16] = 1,
{ .exti = 26, .irq_parent = 37 }, [19] = 3,
{ .exti = 27, .irq_parent = 38 }, [21] = 31,
{ .exti = 28, .irq_parent = 39 }, [22] = 33,
{ .exti = 29, .irq_parent = 71 }, [23] = 72,
{ .exti = 30, .irq_parent = 52 }, [24] = 95,
{ .exti = 31, .irq_parent = 53 }, [25] = 107,
{ .exti = 32, .irq_parent = 82 }, [26] = 37,
{ .exti = 33, .irq_parent = 83 }, [27] = 38,
{ .exti = 47, .irq_parent = 93 }, [28] = 39,
{ .exti = 48, .irq_parent = 138 }, [29] = 71,
{ .exti = 50, .irq_parent = 139 }, [30] = 52,
{ .exti = 52, .irq_parent = 140 }, [31] = 53,
{ .exti = 53, .irq_parent = 141 }, [32] = 82,
{ .exti = 54, .irq_parent = 135 }, [33] = 83,
{ .exti = 61, .irq_parent = 100 }, [47] = 93,
{ .exti = 65, .irq_parent = 144 }, [48] = 138,
{ .exti = 68, .irq_parent = 143 }, [50] = 139,
{ .exti = 70, .irq_parent = 62 }, [52] = 140,
{ .exti = 73, .irq_parent = 129 }, [53] = 141,
[54] = 135,
[61] = 100,
[65] = 144,
[68] = 143,
[70] = 62,
[73] = 129,
}; };
static const struct stm32_desc_irq stm32mp13_desc_irq[] = { static const u8 stm32mp13_desc_irq[] = {
{ .exti = 0, .irq_parent = 6 }, /* default value */
{ .exti = 1, .irq_parent = 7 }, [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
{ .exti = 2, .irq_parent = 8 },
{ .exti = 3, .irq_parent = 9 }, [0] = 6,
{ .exti = 4, .irq_parent = 10 }, [1] = 7,
{ .exti = 5, .irq_parent = 24 }, [2] = 8,
{ .exti = 6, .irq_parent = 65 }, [3] = 9,
{ .exti = 7, .irq_parent = 66 }, [4] = 10,
{ .exti = 8, .irq_parent = 67 }, [5] = 24,
{ .exti = 9, .irq_parent = 68 }, [6] = 65,
{ .exti = 10, .irq_parent = 41 }, [7] = 66,
{ .exti = 11, .irq_parent = 43 }, [8] = 67,
{ .exti = 12, .irq_parent = 77 }, [9] = 68,
{ .exti = 13, .irq_parent = 78 }, [10] = 41,
{ .exti = 14, .irq_parent = 106 }, [11] = 43,
{ .exti = 15, .irq_parent = 109 }, [12] = 77,
{ .exti = 16, .irq_parent = 1 }, [13] = 78,
{ .exti = 19, .irq_parent = 3 }, [14] = 106,
{ .exti = 21, .irq_parent = 32 }, [15] = 109,
{ .exti = 22, .irq_parent = 34 }, [16] = 1,
{ .exti = 23, .irq_parent = 73 }, [19] = 3,
{ .exti = 24, .irq_parent = 93 }, [21] = 32,
{ .exti = 25, .irq_parent = 114 }, [22] = 34,
{ .exti = 26, .irq_parent = 38 }, [23] = 73,
{ .exti = 27, .irq_parent = 39 }, [24] = 93,
{ .exti = 28, .irq_parent = 40 }, [25] = 114,
{ .exti = 29, .irq_parent = 72 }, [26] = 38,
{ .exti = 30, .irq_parent = 53 }, [27] = 39,
{ .exti = 31, .irq_parent = 54 }, [28] = 40,
{ .exti = 32, .irq_parent = 83 }, [29] = 72,
{ .exti = 33, .irq_parent = 84 }, [30] = 53,
{ .exti = 44, .irq_parent = 96 }, [31] = 54,
{ .exti = 47, .irq_parent = 92 }, [32] = 83,
{ .exti = 48, .irq_parent = 116 }, [33] = 84,
{ .exti = 50, .irq_parent = 117 }, [44] = 96,
{ .exti = 52, .irq_parent = 118 }, [47] = 92,
{ .exti = 53, .irq_parent = 119 }, [48] = 116,
{ .exti = 68, .irq_parent = 63 }, [50] = 117,
{ .exti = 70, .irq_parent = 98 }, [52] = 118,
[53] = 119,
[68] = 63,
[70] = 98,
}; };
static const struct stm32_exti_drv_data stm32mp1_drv_data = { static const struct stm32_exti_drv_data stm32mp1_drv_data = {
.exti_banks = stm32mp1_exti_banks, .exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp1_desc_irq, .desc_irqs = stm32mp1_desc_irq,
.irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
}; };
static const struct stm32_exti_drv_data stm32mp13_drv_data = { static const struct stm32_exti_drv_data stm32mp13_drv_data = {
.exti_banks = stm32mp1_exti_banks, .exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp13_desc_irq, .desc_irqs = stm32mp13_desc_irq,
.irq_nr = ARRAY_SIZE(stm32mp13_desc_irq),
}; };
static const struct
stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
irq_hw_number_t hwirq)
{
const struct stm32_desc_irq *desc = NULL;
int i;
if (!drv_data->desc_irqs)
return NULL;
for (i = 0; i < drv_data->irq_nr; i++) {
desc = &drv_data->desc_irqs[i];
if (desc->exti == hwirq)
break;
}
return desc;
}
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{ {
struct stm32_exti_chip_data *chip_data = gc->private; struct stm32_exti_chip_data *chip_data = gc->private;
...@@ -713,7 +695,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, ...@@ -713,7 +695,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
{ {
struct stm32_exti_host_data *host_data = dm->host_data; struct stm32_exti_host_data *host_data = dm->host_data;
struct stm32_exti_chip_data *chip_data; struct stm32_exti_chip_data *chip_data;
const struct stm32_desc_irq *desc; u8 desc_irq;
struct irq_fwspec *fwspec = data; struct irq_fwspec *fwspec = data;
struct irq_fwspec p_fwspec; struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq; irq_hw_number_t hwirq;
...@@ -728,21 +710,21 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm, ...@@ -728,21 +710,21 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
bank = hwirq / IRQS_PER_BANK; bank = hwirq / IRQS_PER_BANK;
chip_data = &host_data->chips_data[bank]; chip_data = &host_data->chips_data[bank];
desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
if (!desc)
return -EINVAL;
event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst); event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
&stm32_exti_h_chip : &stm32_exti_h_chip_direct; &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
if (desc->irq_parent) {
if (!host_data->drv_data || !host_data->drv_data->desc_irqs)
return -EINVAL;
desc_irq = host_data->drv_data->desc_irqs[hwirq];
if (desc_irq != EXTI_INVALID_IRQ) {
p_fwspec.fwnode = dm->parent->fwnode; p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3; p_fwspec.param_count = 3;
p_fwspec.param[0] = GIC_SPI; p_fwspec.param[0] = GIC_SPI;
p_fwspec.param[1] = desc->irq_parent; p_fwspec.param[1] = desc_irq;
p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
......
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