From c412123f2fa31bb032efa5f6f66b951de8714ab8 Mon Sep 17 00:00:00 2001
From: Lucas Stach <l.stach@pengutronix.de>
Date: Fri, 25 Jan 2019 17:20:33 +0100
Subject: [PATCH] arm64: dts: imx8mq: properly describe IRQ hierarchy
The GPCv2 sits between most of the peripherals and the GIC and
functions as a wakeup controller for the CPU cores.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 892063a7c26c..603b2ec80ed6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -11,8 +11,7 @@
#include "imx8mq-pinfunc.h"
/ {
- /* This should really be the GPC, but we need a driver for this first */
- interrupt-parent = <&gic>;
+ interrupt-parent = <&gpc>;
#address-cells = <2>;
#size-cells = <2>;
@@ -257,6 +256,9 @@ clk: clock-controller@30380000 {
gpc: gpc@303a0000 {
compatible = "fsl,imx8mq-gpc";
reg = <0x303a0000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
pgc {
#address-cells = <1>;
--
2.30.9