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Commit c42bee96 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update for Bonnell 

Events are still at version 4:
    https://download.01.org/perfmon/BNL
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

Tested:

Not tested on a Bonnell, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-10-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 09625cff
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tools/perf/pmu-events/arch/x86/bonnell/frontend.json
View file @ c42bee96
[ [
{ {
"EventCode": "0x80", "BriefDescription": "BACLEARS asserted.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x3", "EventCode": "0xE6",
"EventName": "ICACHE.ACCESSES", "EventName": "BACLEARS.ANY",
"SampleAfterValue": "200000", "SampleAfterValue": "2000000",
"BriefDescription": "Instruction fetches." "UMask": "0x1"
}, },
{ {
"EventCode": "0x80", "BriefDescription": "Cycles during which instruction fetches are stalled.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0x86",
"EventName": "ICACHE.HIT", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "200000", "SampleAfterValue": "2000000",
"BriefDescription": "Icache hit" "UMask": "0x1"
}, },
{ {
"EventCode": "0x80", "BriefDescription": "Decode stall due to IQ full",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x2", "EventCode": "0x87",
"EventName": "ICACHE.MISSES", "EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "200000", "SampleAfterValue": "2000000",
"BriefDescription": "Icache miss" "UMask": "0x2"
}, },
{ {
"EventCode": "0x86", "BriefDescription": "Decode stall due to PFB empty",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0x87",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
"BriefDescription": "Cycles during which instruction fetches are stalled." "UMask": "0x1"
}, },
{ {
"EventCode": "0x87", "BriefDescription": "Instruction fetches.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0x80",
"EventName": "DECODE_STALL.PFB_EMPTY", "EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "2000000", "SampleAfterValue": "200000",
"BriefDescription": "Decode stall due to PFB empty" "UMask": "0x3"
}, },
{ {
"EventCode": "0x87", "BriefDescription": "Icache hit",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x2", "EventCode": "0x80",
"EventName": "DECODE_STALL.IQ_FULL", "EventName": "ICACHE.HIT",
"SampleAfterValue": "2000000", "SampleAfterValue": "200000",
"BriefDescription": "Decode stall due to IQ full" "UMask": "0x1"
}, },
{ {
"EventCode": "0xAA", "BriefDescription": "Icache miss",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0x80",
"EventName": "MACRO_INSTS.NON_CISC_DECODED", "EventName": "ICACHE.MISSES",
"SampleAfterValue": "2000000", "SampleAfterValue": "200000",
"BriefDescription": "Non-CISC nacro instructions decoded" "UMask": "0x2"
}, },
{ {
"BriefDescription": "All Instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA", "EventCode": "0xAA",
"EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000",
"UMask": "0x3"
},
{
"BriefDescription": "CISC macro instructions decoded",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x2", "EventCode": "0xAA",
"EventName": "MACRO_INSTS.CISC_DECODED", "EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
"BriefDescription": "CISC macro instructions decoded" "UMask": "0x2"
}, },
{ {
"EventCode": "0xAA", "BriefDescription": "Non-CISC nacro instructions decoded",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x3", "EventCode": "0xAA",
"EventName": "MACRO_INSTS.ALL_DECODED", "EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
"BriefDescription": "All Instructions decoded" "UMask": "0x1"
}, },
{ {
"EventCode": "0xA9", "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "CounterMask": "1",
"EventCode": "0xA9",
"EventName": "UOPS.MS_CYCLES", "EventName": "UOPS.MS_CYCLES",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", "UMask": "0x1"
"CounterMask": "1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/bonnell/memory.json
View file @ c42bee96
[ [
{ {
"EventCode": "0x5", "BriefDescription": "Nonzero segbase 1 bubble",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0xf",
"EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Memory references that cross an 8-byte boundary."
},
{
"EventCode": "0x5", "EventCode": "0x5",
"Counter": "0,1", "EventName": "MISALIGN_MEM_REF.BUBBLE",
"UMask": "0x9",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Load splits" "UMask": "0x97"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Nonzero segbase load 1 bubble",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0xa", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT", "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Store splits" "UMask": "0x91"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Load splits",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x8f", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR", "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)" "UMask": "0x9"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Load splits (At Retirement)",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x89", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Load splits (At Retirement)" "UMask": "0x89"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x8a", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Store splits (Ar Retirement)" "UMask": "0x94"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "ld-op-st splits",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x8c", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT", "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "ld-op-st splits" "UMask": "0x8c"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Memory references that cross an 8-byte boundary.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x97", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.BUBBLE", "EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase 1 bubble" "UMask": "0xf"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x91", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE", "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase load 1 bubble" "UMask": "0x8f"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Nonzero segbase store 1 bubble",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x92", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE", "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase store 1 bubble" "UMask": "0x92"
}, },
{ {
"EventCode": "0x5", "BriefDescription": "Store splits",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x94", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble" "UMask": "0xa"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Store splits (Ar Retirement)",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x81", "EventCode": "0x5",
"EventName": "PREFETCH.PREFETCHT0", "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed." "UMask": "0x8a"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "L1 hardware prefetch request",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x82", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT1", "EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "200000", "SampleAfterValue": "2000000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed." "UMask": "0x10"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x84", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT2", "EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed." "UMask": "0x88"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x86", "EventCode": "0x7",
"EventName": "PREFETCH.SW_L2", "EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed" "UMask": "0x81"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x88", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHNTA", "EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed" "UMask": "0x82"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x10", "EventCode": "0x7",
"EventName": "PREFETCH.HW_PREFETCH", "EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "2000000", "SampleAfterValue": "200000",
"BriefDescription": "L1 hardware prefetch request" "UMask": "0x84"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Any Software prefetch",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0xf", "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH", "EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Any Software prefetch" "UMask": "0xf"
}, },
{ {
"EventCode": "0x7", "BriefDescription": "Any Software prefetch",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x8f", "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Any Software prefetch" "UMask": "0x8f"
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000",
"UMask": "0x86"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
View file @ c42bee96
[ [
{ {
"EventCode": "0x8", "BriefDescription": "Memory accesses that missed the DTLB.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x7", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS", "EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Memory accesses that missed the DTLB." "UMask": "0x7"
}, },
{ {
"EventCode": "0x8", "BriefDescription": "DTLB misses due to load operations.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x5", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "DTLB misses due to load operations." "UMask": "0x5"
}, },
{ {
"EventCode": "0x8", "BriefDescription": "DTLB misses due to store operations.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x9", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "L0 DTLB misses due to load operations." "UMask": "0x6"
}, },
{ {
"EventCode": "0x8", "BriefDescription": "L0 DTLB misses due to load operations.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x6", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "DTLB misses due to store operations." "UMask": "0x9"
}, },
{ {
"EventCode": "0x8", "BriefDescription": "L0 DTLB misses due to store operations",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0xa", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "L0 DTLB misses due to store operations" "UMask": "0xa"
}, },
{ {
"EventCode": "0xC", "BriefDescription": "ITLB flushes.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x3", "EventCode": "0x82",
"EventName": "PAGE_WALKS.WALKS", "EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Number of page-walks executed." "UMask": "0x4"
}, },
{ {
"EventCode": "0xC", "BriefDescription": "ITLB hits.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x3", "EventCode": "0x82",
"EventName": "PAGE_WALKS.CYCLES", "EventName": "ITLB.HIT",
"SampleAfterValue": "2000000", "SampleAfterValue": "200000",
"BriefDescription": "Duration of page-walks in core cycles" "UMask": "0x1"
}, },
{ {
"EventCode": "0xC", "BriefDescription": "ITLB misses.",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0x82",
"EventName": "PAGE_WALKS.D_SIDE_WALKS", "EventName": "ITLB.MISSES",
"PEBS": "2",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Number of D-side only page walks" "UMask": "0x2"
}, },
{ {
"EventCode": "0xC", "BriefDescription": "Retired loads that miss the DTLB (precise event).",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0xCB",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"SampleAfterValue": "2000000", "PEBS": "1",
"BriefDescription": "Duration of D-side only page walks" "SampleAfterValue": "200000",
"UMask": "0x4"
}, },
{ {
"EventCode": "0xC", "BriefDescription": "Duration of page-walks in core cycles",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x2", "EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_WALKS", "EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "200000", "SampleAfterValue": "2000000",
"BriefDescription": "Number of I-Side page walks" "UMask": "0x3"
}, },
{ {
"EventCode": "0xC", "BriefDescription": "Duration of D-side only page walks",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x2", "EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES", "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
"BriefDescription": "Duration of I-Side page walks" "UMask": "0x1"
}, },
{ {
"EventCode": "0x82", "BriefDescription": "Number of D-side only page walks",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x1", "EventCode": "0xC",
"EventName": "ITLB.HIT", "EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "ITLB hits." "UMask": "0x1"
}, },
{ {
"EventCode": "0x82", "BriefDescription": "Duration of I-Side page walks",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x4", "EventCode": "0xC",
"EventName": "ITLB.FLUSH", "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "200000", "SampleAfterValue": "2000000",
"BriefDescription": "ITLB flushes." "UMask": "0x2"
}, },
{ {
"PEBS": "2", "BriefDescription": "Number of I-Side page walks",
"EventCode": "0x82",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x2", "EventCode": "0xC",
"EventName": "ITLB.MISSES", "EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "ITLB misses." "UMask": "0x2"
}, },
{ {
"PEBS": "1", "BriefDescription": "Number of page-walks executed.",
"EventCode": "0xCB",
"Counter": "0,1", "Counter": "0,1",
"UMask": "0x4", "EventCode": "0xC",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (precise event)." "UMask": "0x3"
} }
] ]
\ No newline at end of file
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