Skip to content

L
linux
Commit c720a1f5 authored by Michal Simek's avatar Michal Simek
Browse files
Options

arm64: zynqmp: Describe TI phy as ethernet-phy-id 

TI DP83867 is using strapping based on MIO pins. Tristate setup can
influence PHY address. That's why switch description with ethernet-phy-id
compatible string which enable calling reset. PHY itself setups phy address
after power up or reset. Phy reset is done via gpio.
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com
parent 4e4ddd3d
Hide whitespace changes
Inline Side-by-side
Showing with 90 additions and 46 deletions
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View file @ c720a1f5
...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
/* /*
* dts file for Xilinx ZynqMP ZCU102 RevA * dts file for Xilinx ZynqMP ZCU102 RevA
* *
* (C) Copyright 2015 - 2021, Xilinx, Inc. * (C) Copyright 2015 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@amd.com> * Michal Simek <michal.simek@amd.com>
*/ */
...@@ -200,13 +201,19 @@ &gem3 { ...@@ -200,13 +201,19 @@ &gem3 {
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@21 { mdio: mdio {
reg = <21>; #address-cells = <1>;
ti,rx-internal-delay = <0x8>; #size-cells = <0>;
ti,tx-internal-delay = <0xa>; phy0: ethernet-phy@21 {
ti,fifo-depth = <0x1>; #phy-cells = <1>;
ti,dp83867-rxctrl-strap-quirk; compatible = "ethernet-phy-id2000.a231";
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
}; };
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
View file @ c720a1f5
...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
/* /*
* dts file for Xilinx ZynqMP ZCU102 RevB * dts file for Xilinx ZynqMP ZCU102 RevB
* *
* (C) Copyright 2016 - 2021, Xilinx, Inc. * (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@amd.com> * Michal Simek <michal.simek@amd.com>
*/ */
...@@ -16,16 +17,20 @@ / { ...@@ -16,16 +17,20 @@ / {
&gem3 { &gem3 {
phy-handle = <&phyc>; phy-handle = <&phyc>;
phyc: ethernet-phy@c { mdio: mdio {
reg = <0xc>; phyc: ethernet-phy@c {
ti,rx-internal-delay = <0x8>; #phy-cells = <0x1>;
ti,tx-internal-delay = <0xa>; compatible = "ethernet-phy-id2000.a231";
ti,fifo-depth = <0x1>; reg = <0xc>;
ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>;
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
/* Cleanup from RevA */
/delete-node/ ethernet-phy@21;
}; };
/* Cleanup from RevA */
/delete-node/ ethernet-phy@21;
}; };
/* Fix collision with u61 */ /* Fix collision with u61 */
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View file @ c720a1f5
...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
/* /*
* dts file for Xilinx ZynqMP ZCU104 * dts file for Xilinx ZynqMP ZCU104
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@amd.com> * Michal Simek <michal.simek@amd.com>
*/ */
...@@ -109,12 +110,19 @@ &gem3 { ...@@ -109,12 +110,19 @@ &gem3 {
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { mdio: mdio {
reg = <0xc>; #address-cells = <1>;
ti,rx-internal-delay = <0x8>; #size-cells = <0>;
ti,tx-internal-delay = <0xa>; phy0: ethernet-phy@c {
ti,fifo-depth = <0x1>; #phy-cells = <1>;
ti,dp83867-rxctrl-strap-quirk; compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
}; };
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
View file @ c720a1f5
...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
/* /*
* dts file for Xilinx ZynqMP ZCU104 * dts file for Xilinx ZynqMP ZCU104
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@amd.com> * Michal Simek <michal.simek@amd.com>
*/ */
...@@ -114,12 +115,19 @@ &gem3 { ...@@ -114,12 +115,19 @@ &gem3 {
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { mdio: mdio {
reg = <0xc>; #address-cells = <1>;
ti,rx-internal-delay = <0x8>; #size-cells = <0>;
ti,tx-internal-delay = <0xa>; phy0: ethernet-phy@c {
ti,fifo-depth = <0x1>; #phy-cells = <1>;
ti,dp83867-rxctrl-strap-quirk; compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
}; };
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View file @ c720a1f5
...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
/* /*
* dts file for Xilinx ZynqMP ZCU106 * dts file for Xilinx ZynqMP ZCU106
* *
* (C) Copyright 2016 - 2021, Xilinx, Inc. * (C) Copyright 2016 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@amd.com> * Michal Simek <michal.simek@amd.com>
*/ */
...@@ -212,12 +213,19 @@ &gem3 { ...@@ -212,12 +213,19 @@ &gem3 {
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { mdio: mdio {
reg = <0xc>; #address-cells = <1>;
ti,rx-internal-delay = <0x8>; #size-cells = <0>;
ti,tx-internal-delay = <0xa>; phy0: ethernet-phy@c {
ti,fifo-depth = <0x1>; #phy-cells = <1>;
ti,dp83867-rxctrl-strap-quirk; reg = <0xc>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
};
}; };
}; };
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View file @ c720a1f5
...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
/* /*
* dts file for Xilinx ZynqMP ZCU111 * dts file for Xilinx ZynqMP ZCU111
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* *
* Michal Simek <michal.simek@amd.com> * Michal Simek <michal.simek@amd.com>
*/ */
...@@ -172,12 +173,19 @@ &gem3 { ...@@ -172,12 +173,19 @@ &gem3 {
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c { mdio: mdio {
reg = <0xc>; #address-cells = <1>;
ti,rx-internal-delay = <0x8>; #size-cells = <0>;
ti,tx-internal-delay = <0xa>; phy0: ethernet-phy@c {
ti,fifo-depth = <0x1>; #phy-cells = <1>;
ti,dp83867-rxctrl-strap-quirk; compatible = "ethernet-phy-id2000.a231";
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
};
}; };
}; };
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7