Commit c772b44e authored by Jiang Liu's avatar Jiang Liu Committed by Bjorn Helgaas

cxgb3: Use PCI Express Capability accessors

Use PCI Express Capability access functions to simplify cxgb3 driver.

[bhelgaas: split cxgb3 and cxgb4 into separate patches]
Signed-off-by: default avatarJiang Liu <jiang.liu@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 9503e255
...@@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap) ...@@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap)
unsigned int log2_width, pldsize; unsigned int log2_width, pldsize;
unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
pci_read_config_word(adap->pdev, pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val);
adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
&val);
pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
pci_read_config_word(adap->pdev, 0x2, &devid); pci_read_config_word(adap->pdev, 0x2, &devid);
if (devid == 0x37) { if (devid == 0x37) {
pci_write_config_word(adap->pdev, pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,
adap->pdev->pcie_cap + PCI_EXP_DEVCTL, val & ~PCI_EXP_DEVCTL_READRQ &
val & ~PCI_EXP_DEVCTL_READRQ & ~PCI_EXP_DEVCTL_PAYLOAD);
~PCI_EXP_DEVCTL_PAYLOAD);
pldsize = 0; pldsize = 0;
} }
pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL, pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val);
&val);
fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
...@@ -3425,15 +3421,13 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params) ...@@ -3425,15 +3421,13 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
static void get_pci_mode(struct adapter *adapter, struct pci_params *p) static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
{ {
static unsigned short speed_map[] = { 33, 66, 100, 133 }; static unsigned short speed_map[] = { 33, 66, 100, 133 };
u32 pci_mode, pcie_cap; u32 pci_mode;
pcie_cap = pci_pcie_cap(adapter->pdev); if (pci_is_pcie(adapter->pdev)) {
if (pcie_cap) {
u16 val; u16 val;
p->variant = PCI_VARIANT_PCIE; p->variant = PCI_VARIANT_PCIE;
pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
&val);
p->width = (val >> 4) & 0x3f; p->width = (val >> 4) & 0x3f;
return; return;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment