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Commit c7930112 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.15 kernel cycle, no
  core changes at all this time, just driver work!

  New drivers:

   - New subdriver for Intel Keem Bay (an ARM-based SoC)

   - New subdriver for Qualcomm MDM9607 and SM6115

   - New subdriver for ST Microelectronics STM32MP135

   - New subdriver for Freescale i.MX8ULP ("Ultra Low Power")

   - New subdriver for Ingenic X2100

   - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO

   - Support Samsung Exynos850

   - Support Renesas RZ/G2L

  Enhancements:

   - A major refactoring of the Rockchip driver, breaking part of it out
     to a separate GPIO driver in drivers/gpio

   - Pin bias support on Renesas r8a77995

   - Add SCI pins support to Ingenic JZ4755 and JZ4760

   - Mediatek device tree bindings converted to YAML"

* tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits)
  pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
  pinctrl: samsung: Add Exynos850 SoC specific data
  dt-bindings: pinctrl: samsung: Add Exynos850 doc
  MAINTAINERS: Add maintainers for amd-pinctrl driver
  pinctrl: Add Intel Keem Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver
  pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device
  dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property
  dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML
  dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments
  dt-bindings: mediatek: convert pinctrl to yaml
  arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl
  arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl
  pinctrl: ingenic: Add .max_register in regmap_config
  pinctrl: ingenic: Fix bias config for X2000(E)
  pinctrl: ingenic: Fix incorrect pull up/down info
  pinctrl: Ingenic: Add pinctrl driver for X2100.
  dt-bindings: pinctrl: Add bindings for Ingenic X2100.
  pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760.
  pinctrl: Ingenic: Improve the code.
  ...
parents 75d6e7d9 04853352
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Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX8ULP IOMUX Controller
maintainers:
- Jacky Bai <ping.bai@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
const: fsl,imx8ulp-iomuxc1
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 5 integers and represents the mux and config
setting for one pin. The first 4 integers <mux_config_reg input_reg
mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_config_reg" indicates the offset of mux register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_mode" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
iomuxc: pinctrl@298c0000 {
compatible = "fsl,imx8ulp-iomuxc1";
reg = <0x298c0000 0x10000>;
pinctrl_lpuart5: lpuart5grp {
fsl,pins =
<0x0138 0x08F0 0x4 0x3 0x3>,
<0x013C 0x08EC 0x4 0x3 0x3>;
};
};
...
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
View file @ c7930112
...@@ -19,10 +19,10 @@ description: > ...@@ -19,10 +19,10 @@ description: >
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B, and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128 the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins. pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO 160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains
ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports, 6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO
PA to PG, for a total of 224 pins. ports, PA to PG, for a total of 224 pins.
maintainers: maintainers:
- Paul Cercueil <paul@crapouillou.net> - Paul Cercueil <paul@crapouillou.net>
...@@ -47,6 +47,7 @@ properties: ...@@ -47,6 +47,7 @@ properties:
- ingenic,x1500-pinctrl - ingenic,x1500-pinctrl
- ingenic,x1830-pinctrl - ingenic,x1830-pinctrl
- ingenic,x2000-pinctrl - ingenic,x2000-pinctrl
- ingenic,x2100-pinctrl
- items: - items:
- const: ingenic,jz4760b-pinctrl - const: ingenic,jz4760b-pinctrl
- const: ingenic,jz4760-pinctrl - const: ingenic,jz4760-pinctrl
...@@ -85,6 +86,7 @@ patternProperties: ...@@ -85,6 +86,7 @@ patternProperties:
- ingenic,x1500-gpio - ingenic,x1500-gpio
- ingenic,x1830-gpio - ingenic,x1830-gpio
- ingenic,x2000-gpio - ingenic,x2000-gpio
- ingenic,x2100-gpio
reg: reg:
items: items:
......
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Keem Bay pin controller Device Tree Bindings
maintainers:
- Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
description: |
Intel Keem Bay SoC integrates a pin controller which enables control
of pin directions, input/output values and configuration
for a total of 80 pins.
properties:
compatible:
const: intel,keembay-pinctrl
reg:
maxItems: 2
gpio-controller: true
'#gpio-cells':
const: 2
ngpios:
description: The number of GPIOs exposed.
const: 80
interrupts:
description:
Specifies the interrupt lines to be used by the controller.
Each interrupt line is shared by upto 4 GPIO lines.
maxItems: 8
interrupt-controller: true
'#interrupt-cells':
const: 2
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
description:
Child nodes can be specified to contain pin configuration information,
which can then be utilized by pinctrl client devices.
The following properties are supported.
properties:
pins:
description: |
The name(s) of the pins to be configured in the child node.
Supported pin names are "GPIO0" up to "GPIO79".
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
description: IO pads drive strength in milli Ampere.
enum: [2, 4, 8, 12]
bias-bus-hold:
type: boolean
input-schmitt-enable:
type: boolean
slew-rate:
description: GPIO slew rate control.
0 - Fast(~100MHz)
1 - Slow(~50MHz)
enum: [0, 1]
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- ngpios
- '#gpio-cells'
- interrupts
- interrupt-controller
- '#interrupt-cells'
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
// Example 1
gpio@0 {
compatible = "intel,keembay-pinctrl";
reg = <0x600b0000 0x88>,
<0x600b0190 0x1ac>;
gpio-controller;
ngpios = <0x50>;
#gpio-cells = <0x2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
};
// Example 2
gpio@1 {
compatible = "intel,keembay-pinctrl";
reg = <0x600c0000 0x88>,
<0x600c0190 0x1ac>;
gpio-controller;
ngpios = <0x50>;
#gpio-cells = <0x2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
};
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
View file @ c7930112
...@@ -43,19 +43,19 @@ group emmc_nb ...@@ -43,19 +43,19 @@ group emmc_nb
group pwm0 group pwm0
- pin 11 (GPIO1-11) - pin 11 (GPIO1-11)
- functions pwm, gpio - functions pwm, led, gpio
group pwm1 group pwm1
- pin 12 - pin 12
- functions pwm, gpio - functions pwm, led, gpio
group pwm2 group pwm2
- pin 13 - pin 13
- functions pwm, gpio - functions pwm, led, gpio
group pwm3 group pwm3
- pin 14 - pin 14
- functions pwm, gpio - functions pwm, led, gpio
group pmic1 group pmic1
- pin 7 - pin 7
......
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT65xx Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
enum:
- mediatek,mt2701-pinctrl
- mediatek,mt2712-pinctrl
- mediatek,mt6397-pinctrl
- mediatek,mt7623-pinctrl
- mediatek,mt8127-pinctrl
- mediatek,mt8135-pinctrl
- mediatek,mt8167-pinctrl
- mediatek,mt8173-pinctrl
- mediatek,mt8516-pinctrl
reg:
maxItems: 1
pins-are-numbered:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Specify the subnodes are using numbered pinmux to specify pins.
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
mediatek,pctl-regmap:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
description: |
Should be phandles of the syscfg node.
interrupt-controller: true
interrupts:
minItems: 1
maxItems: 3
"#interrupt-cells":
const: 2
required:
- compatible
- pins-are-numbered
- gpio-controller
- "#gpio-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up:
description: |
Besides generic pinconfig options, it can be used as the pull up
settings for 2 pull resistors, R0 and R1. User can configure those
special pins. Some macros have been defined for this usage, such
as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
valid arguments.
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
description: |
Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8135-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0-0 {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
i2c2_pins_a: i2c2-0 {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3-0 {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT6797 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT6797 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6797-pinctrl
reg:
minItems: 5
maxItems: 5
reg-names:
items:
- const: gpio
- const: iocfgl
- const: iocfgb
- const: iocfgr
- const: iocfgt
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- reg-names
- gpio-controller
- "#gpio-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-enable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 8, 12, 16]
slew-rate:
enum: [0, 1]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart_pins_a: uart-0 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8183 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT8183 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8183-pinctrl
reg:
minItems: 10
maxItems: 10
reg-names:
items:
- const: iocfg0
- const: iocfg1
- const: iocfg2
- const: iocfg3
- const: iocfg4
- const: iocfg5
- const: iocfg6
- const: iocfg7
- const: iocfg8
- const: eint
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
gpio-ranges:
minItems: 1
maxItems: 5
description: |
GPIO valid number range.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- gpio-ranges
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c-0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c-1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt deleted 100644 → 0
View file @ 75d6e7d9
* Mediatek MT65XX Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
"mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
Eg: <&pio 6 0>
<[phandle of the gpio controller node]
[line number within the gpio controller]
[flags]>
Values for gpio specifier:
- Line number: is a value between 0 to 202.
- Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
Only the following flags are supported:
0 - GPIO_ACTIVE_HIGH
1 - GPIO_ACTIVE_LOW
Optional properties:
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
- reg: physicall address base for EINT registers
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
So when config bias-pull-up, it support arguments for those special pins.
Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
See dt-bindings/pinctrl/mt65xx.h.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
Examples:
#include "mt8135-pinfunc.h"
...
{
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0@0 {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1@0 {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <55>;
};
};
i2c2_pins_a: i2c2@0 {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3@0 {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <55>;
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <55>;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
};
};
...
}
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt deleted 100644 → 0
View file @ 75d6e7d9
* MediaTek MT6797 Pin Controller
The MediaTek's MT6797 Pin controller is used to control SoC pins.
Required properties:
- compatible: Value should be one of the following.
"mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
- reg: Should contain address and size for gpio, iocfgl, iocfgb,
iocfgr and iocfgt register bases.
- reg-names: An array of strings describing the "reg" entries. Must
contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
Optional properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
input-schmitt-disable, output-enable output-low, output-high,
drive-strength, and slew-rate are valid.
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
'1' for slower slew rate respectively. Valid arguments for 'drive-strength'
is limited, such as 2, 4, 8, 12, or 16 in mA.
Some optional vendor properties as defined are valid to specify in a
pinconf subnode:
- mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
- mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
- mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
or 3 for the advanced pull-up resistors.
- mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
or 3 for the advanced pull-down resistors.
Examples:
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart1_pins_a: uart1 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt deleted 100644 → 0
View file @ 75d6e7d9
* Mediatek MT8183 Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
- gpio-ranges : gpio valid number range.
- reg: physical address base for gpio base registers. There are 10 GPIO
physical address base in mt8183.
Optional properties:
- reg-names: gpio base register names. There are 10 gpio base register
names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
"iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint".
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs to sysirq.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
output-high, input-schmitt-enable, input-schmitt-disable
and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01,
10 or 11. So It needs config "mediatek,pull-up-adv" or
"mediatek,pull-down-adv" to support arguments for those special pins.
Valid arguments are from 0 to 3.
mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
It can only support 2/4/6/8/10/12/14/16mA in mt8183.
For I2C pins, there are existing generic driving setup and the specific
driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
adjustment in generic driving setup. But in specific driving setup,
they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup for I2C pins, the existing generic driving setup will be
disabled. For some special features, we need the I2C pins specific
driving setup. The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of
the generic driving property.
We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
It is used to enable or disable the specific driving setup.
E1E0 is used to describe the detail strength specification of the I2C pin.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
Examples:
#include "mt8183-pinfunc.h"
...
{
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
...
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml
View file @ c7930112
...@@ -80,10 +80,7 @@ patternProperties: ...@@ -80,10 +80,7 @@ patternProperties:
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength: drive-strength:
description: | enum: [2, 4, 6, 8, 10, 12, 14, 16]
It can support some arguments which is from 0 to 7. It can only support
2/4/6/8/10/12/14/16mA in mt8195.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
bias-pull-down: true bias-pull-down: true
......
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MDM9607 TLMM block
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
MDM9607 platform.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,mdm9607-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
required:
- compatible
- reg
additionalProperties: false
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-mdm9607-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-mdm9607-tlmm-state"
'$defs':
qcom-mdm9607-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3 ]
minItems: 1
maxItems: 16
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3,
atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,mdm9607-tlmm";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 80>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt deleted 100644 → 0
View file @ 75d6e7d9
Qualcomm PMIC GPIO block
This binding describes the GPIO block(s) found in the 8xxx series of
PMIC's from Qualcomm.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,pm8005-gpio"
"qcom,pm8018-gpio"
"qcom,pm8038-gpio"
"qcom,pm8058-gpio"
"qcom,pm8916-gpio"
"qcom,pm8917-gpio"
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8950-gpio"
"qcom,pm8994-gpio"
"qcom,pm8998-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8950-gpio"
"qcom,pmi8994-gpio"
"qcom,pmi8998-gpio"
"qcom,pms405-gpio"
"qcom,pm660-gpio"
"qcom,pm660l-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm8350-gpio"
"qcom,pm8350b-gpio"
"qcom,pm8350c-gpio"
"qcom,pmk8350-gpio"
"qcom,pm7325-gpio"
"qcom,pmr735a-gpio"
"qcom,pmr735b-gpio"
"qcom,pm6150-gpio"
"qcom,pm6150l-gpio"
"qcom,pm8008-gpio"
"qcom,pmx55-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base of the GPIO block and length.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Must contain an array of encoded interrupt specifiers for
each available GPIO
- gpio-controller:
Usage: required
Value type: <none>
Definition: Mark the device node as a GPIO controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: Must be 2;
the first cell will be used to define gpio number and the
second denotes the flags for this gpio
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin or a list of pins. This configuration can include the
mux function to select on those pin(s), and various pin configuration
parameters, as listed below.
SUBNODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio1-gpio4 for pm8005
gpio1-gpio6 for pm8018
gpio1-gpio12 for pm8038
gpio1-gpio40 for pm8058
gpio1-gpio4 for pm8916
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio8 for pm8950 (hole on gpio3)
gpio1-gpio22 for pm8994
gpio1-gpio26 for pm8998
gpio1-gpio22 for pma8084
gpio1-gpio2 for pmi8950
gpio1-gpio10 for pmi8994
gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7
and gpio8)
gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
gpio1-gpio12 for pm8150l (hole on gpio7)
gpio1-gpio10 for pm8350
gpio1-gpio8 for pm8350b
gpio1-gpio9 for pm8350c
gpio1-gpio4 for pmk8350
gpio1-gpio10 for pm7325
gpio1-gpio4 for pmr735a
gpio1-gpio4 for pmr735b
gpio1-gpio10 for pm6150
gpio1-gpio12 for pm6150l
gpio1-gpio2 for pm8008
gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Valid values are:
"normal",
"paired",
"func1",
"func2",
"dtest1",
"dtest2",
"dtest3",
"dtest4",
And following values are supported by LV/MV GPIO subtypes:
"func3",
"func4"
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <empty>
Definition: The specified pins should be configured as pull up.
- qcom,pull-up-strength:
Usage: optional
Value type: <u32>
Definition: Specifies the strength to use for pull up, if selected.
Valid values are; as defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>:
1: 30uA (PMIC_GPIO_PULL_UP_30)
2: 1.5uA (PMIC_GPIO_PULL_UP_1P5)
3: 31.5uA (PMIC_GPIO_PULL_UP_31P5)
4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30)
If this property is omitted 30uA strength will be used if
pull up is selected
- bias-high-impedance:
Usage: optional
Value type: <none>
Definition: The specified pins will put in high-Z mode and disabled.
- input-enable:
Usage: optional
Value type: <none>
Definition: The specified pins are put in input mode.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
- power-source:
Usage: optional
Value type: <u32>
Definition: Selects the power source for the specified pins. Valid
power sources are defined per chip in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
- qcom,drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins. Value
drive strengths are:
0: no (PMIC_GPIO_STRENGTH_NO)
1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V
2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V
3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V
as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h>
- drive-push-pull:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in push-pull mode.
- drive-open-drain:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in open-drain mode.
- drive-open-source:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in open-source mode.
- qcom,analog-pass:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in analog-pass-through mode.
- qcom,atest:
Usage: optional
Value type: <u32>
Definition: Selects ATEST rail to route to GPIO when it's configured
in analog-pass-through mode.
Valid values are 1-4 corresponding to ATEST1 to ATEST4.
- qcom,dtest-buffer:
Usage: optional
Value type: <u32>
Definition: Selects DTEST rail to route to GPIO when it's configured
as digital input.
Valid values are 1-4 corresponding to DTEST1 to DTEST4.
Example:
pm8921_gpio: gpio@150 {
compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio";
reg = <0x150 0x160>;
interrupts = <192 1>, <193 1>, <194 1>,
<195 1>, <196 1>, <197 1>,
<198 1>, <199 1>, <200 1>,
<201 1>, <202 1>, <203 1>,
<204 1>, <205 1>, <206 1>,
<207 1>, <208 1>, <209 1>,
<210 1>, <211 1>, <212 1>,
<213 1>, <214 1>, <215 1>,
<216 1>, <217 1>, <218 1>,
<219 1>, <220 1>, <221 1>,
<222 1>, <223 1>, <224 1>,
<225 1>, <226 1>, <227 1>,
<228 1>, <229 1>, <230 1>,
<231 1>, <232 1>, <233 1>,
<234 1>, <235 1>;
gpio-controller;
#gpio-cells = <2>;
pm8921_gpio_keys: gpio-keys {
volume-keys {
pins = "gpio20", "gpio21";
function = "normal";
input-enable;
bias-pull-up;
drive-push-pull;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8921_GPIO_S4>;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PMIC GPIO block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
This binding describes the GPIO block(s) found in the 8xxx series of
PMIC's from Qualcomm.
properties:
compatible:
items:
- enum:
- qcom,pm660-gpio
- qcom,pm660l-gpio
- qcom,pm6150-gpio
- qcom,pm6150l-gpio
- qcom,pm7325-gpio
- qcom,pm8005-gpio
- qcom,pm8008-gpio
- qcom,pm8018-gpio
- qcom,pm8038-gpio
- qcom,pm8058-gpio
- qcom,pm8150-gpio
- qcom,pm8150b-gpio
- qcom,pm8350-gpio
- qcom,pm8350b-gpio
- qcom,pm8350c-gpio
- qcom,pm8916-gpio
- qcom,pm8917-gpio
- qcom,pm8921-gpio
- qcom,pm8941-gpio
- qcom,pm8950-gpio
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
- qcom,pmi8950-gpio
- qcom,pmi8994-gpio
- qcom,pmi8998-gpio
- qcom,pmk8350-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
- qcom,pms405-gpio
- qcom,pmx55-gpio
- enum:
- qcom,spmi-gpio
- qcom,ssbi-gpio
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
gpio-ranges:
maxItems: 1
'#gpio-cells':
const: 2
description:
The first cell will be used to define gpio number and the
second denotes the flags for this gpio
additionalProperties: false
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- interrupt-controller
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-pmic-gpio-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-pmic-gpio-state"
$defs:
qcom-pmic-gpio-state:
type: object
allOf:
- $ref: "pinmux-node.yaml"
- $ref: "pincfg-node.yaml"
properties:
pins:
description:
List of gpio pins affected by the properties specified in
this subnode. Valid pins are
- gpio1-gpio10 for pm6150
- gpio1-gpio12 for pm6150l
- gpio1-gpio10 for pm7325
- gpio1-gpio4 for pm8005
- gpio1-gpio2 for pm8008
- gpio1-gpio6 for pm8018
- gpio1-gpio12 for pm8038
- gpio1-gpio40 for pm8058
- gpio1-gpio10 for pm8150 (holes on gpio2, gpio5,
gpio7 and gpio8)
- gpio1-gpio12 for pm8150b (holes on gpio3, gpio4
and gpio7)
- gpio1-gpio12 for pm8150l (hole on gpio7)
- gpio1-gpio4 for pm8916
- gpio1-gpio10 for pm8350
- gpio1-gpio8 for pm8350b
- gpio1-gpio9 for pm8350c
- gpio1-gpio38 for pm8917
- gpio1-gpio44 for pm8921
- gpio1-gpio36 for pm8941
- gpio1-gpio8 for pm8950 (hole on gpio3)
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio2 for pmi8950
- gpio1-gpio10 for pmi8994
- gpio1-gpio4 for pmk8350
- gpio1-gpio4 for pmr735a
- gpio1-gpio4 for pmr735b
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9
and gpio10)
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
items:
pattern: "^gpio([0-9]+)$"
function:
items:
- enum:
- normal
- paired
- func1
- func2
- dtest1
- dtest2
- dtest3
- dtest4
- func3 # supported by LV/MV GPIO subtypes
- func4 # supported by LV/MV GPIO subtypes
bias-disable: true
bias-pull-down: true
bias-pull-up: true
qcom,pull-up-strength:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies the strength to use for pull up, if selected.
Valid values are defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
If this property is omitted 30uA strength will be used
if pull up is selected
enum: [0, 1, 2, 3]
bias-high-impedance: true
input-enable: true
output-high: true
output-low: true
power-source: true
qcom,drive-strength:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects the drive strength for the specified pins
Valid drive strength values are defined in
<dt-bindings/pinctrl/qcom,pmic-gpio.h>
enum: [0, 1, 2, 3]
drive-push-pull: true
drive-open-drain: true
drive-open-source: true
qcom,analog-pass:
$ref: /schemas/types.yaml#/definitions/flag
description:
The specified pins are configured in
analog-pass-through mode.
qcom,atest:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects ATEST rail to route to GPIO when it's
configured in analog-pass-through mode.
enum: [1, 2, 3, 4]
qcom,dtest-buffer:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Selects DTEST rail to route to GPIO when it's
configured as digital input.
enum: [1, 2, 3, 4]
required:
- pins
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
pm8921_gpio: gpio@150 {
compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio";
reg = <0x150 0x160>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
gpio-ranges = <&pm8921_gpio 0 0 44>;
#gpio-cells = <2>;
pm8921_gpio_keys: gpio-keys-state {
volume-keys {
pins = "gpio20", "gpio21";
function = "normal";
input-enable;
bias-pull-up;
drive-push-pull;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8921_GPIO_S4>;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
maintainers:
- Iskren Chernev <iskren.chernev@gmail.com>
description:
This binding describes the Top Level Mode Multiplexer block found in the
SM4250/6115 platforms.
properties:
compatible:
const: qcom,sm6115-tlmm
reg:
minItems: 3
maxItems: 3
reg-names:
items:
- const: west
- const: south
- const: east
interrupts:
description: Specifies the TLMM summary IRQ
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
description:
Specifies the PIN numbers and Flags, as defined in defined in
include/dt-bindings/interrupt-controller/irq.h
const: 2
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
wakeup-parent:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-state$':
oneOf:
- $ref: "#/$defs/qcom-sm6115-tlmm-state"
- patternProperties:
".*":
$ref: "#/$defs/qcom-sm6115-tlmm-state"
'$defs':
qcom-sm6115-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
wlan1_adc0, elan1_adc1 ]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x500000 0x400000>,
<0x900000 0x400000>,
<0xd00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 114>;
sdc2_on_state: sdc2-on-state {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio88";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L combined Pin and GPIO controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
enum:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
E.g. "RZG2L_GPIO(39, 1)" for P39_1.
gpio-ranges:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
items:
- description: GPIO_RSTN signal
- description: GPIO_PORT_RESETN signal
- description: GPIO_SPARE_RESETN signal
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZG2L_PORT_PINMUX()
helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
pins: true
drive-strength:
enum: [ 2, 4, 8, 12 ]
power-source:
enum: [ 1800, 2500, 3300 ]
slew-rate: true
gpio-hog: true
gpios: true
input-enable: true
output-high: true
output-low: true
line-name: true
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- clocks
- power-domains
- resets
examples:
- |
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a07g044-pinctrl";
reg = <0x11030000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
resets = <&cpg R9A07G044_GPIO_RSTN>,
<&cpg R9A07G044_GPIO_PORT_RESETN>,
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
power-domains = <&cpg>;
scif0_pins: serial0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) 0>;
output-high;
line-name = "sd1_pwr_en";
};
sdhi1_pins: sd1 {
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
<RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
power-source = <3300>;
};
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
};
};
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
View file @ c7930112
...@@ -22,6 +22,7 @@ Required Properties: ...@@ -22,6 +22,7 @@ Required Properties:
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of - reg: Base address of the pin controller hardware module and length of
the address space it occupies. the address space it occupies.
......
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View file @ c7930112
...@@ -24,6 +24,7 @@ properties: ...@@ -24,6 +24,7 @@ properties:
- st,stm32f746-pinctrl - st,stm32f746-pinctrl
- st,stm32f769-pinctrl - st,stm32f769-pinctrl
- st,stm32h743-pinctrl - st,stm32h743-pinctrl
- st,stm32mp135-pinctrl
- st,stm32mp157-pinctrl - st,stm32mp157-pinctrl
- st,stm32mp157-z-pinctrl - st,stm32mp157-z-pinctrl
......
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt deleted 100644 → 0
View file @ 75d6e7d9
Binding for Xilinx Zynq Pinctrl
Required properties:
- compatible: "xlnx,zynq-pinctrl"
- syscon: phandle to SLCR
- reg: Offset and length of pinctrl space in SLCR
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Zynq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Required properties for pinmux nodes are:
- groups: A list of pinmux groups.
- function: The name of a pinmux function to activate for the specified set
of groups.
Required properties for configuration nodes:
One of:
- pins: a list of pin names
- groups: A list of pinmux groups.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
groups, function
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
low-power-disable, low-power-enable
Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
respectively.
Valid values for groups are:
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp,
ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
Valid values for pins are:
MIO0 - MIO53
Valid values for function are:
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
The following driver-specific properties as defined here are valid to specify in
a pin configuration subnode:
- io-standard: Configure the pin to use the selected IO standard according to
this mapping:
1: LVCMOS18
2: LVCMOS25
3: LVCMOS33
4: HSTL
Example:
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml 0 → 100644
View file @ c7930112
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Zynq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
properties:
compatible:
const: xlnx,zynq-pinctrl
reg:
description: Specifies the base address and size of the SLCR space.
maxItems: 1
syscon:
description:
phandle to the SLCR.
patternProperties:
'^(.*-)?(default|gpio)$':
type: object
patternProperties:
'^mux':
type: object
description:
Pinctrl node's client devices use subnodes for pin muxes,
which in turn use below standard properties.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of groups to select (either this or "pins" must be
specified), available groups for this subnode.
items:
enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp,
can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp,
can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp,
can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp,
can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp,
can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp,
can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp,
uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp,
uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp,
uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp,
uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp,
uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp,
i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp,
i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp,
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp,
i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp,
i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp,
ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp,
swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp,
swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp,
gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp,
gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp,
gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp,
gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp,
gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp,
gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp,
gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp,
gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp,
gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp,
usb1_0_grp]
maxItems: 54
function:
description:
Specify the alternative function to be configured for the
given pin groups.
enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk,
qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc,
sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0,
can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
usb0, usb1]
required:
- groups
- function
additionalProperties: false
'^conf':
type: object
description:
Pinctrl node's client devices use subnodes for pin configurations,
which in turn use the standard properties below.
$ref: pincfg-node.yaml#
properties:
groups:
description:
List of pin groups as mentioned above.
pins:
description:
List of pin names to select in this subnode.
items:
pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
maxItems: 54
bias-pull-up: true
bias-pull-down: true
bias-disable: true
bias-high-impedance: true
low-power-enable: true
low-power-disable: true
slew-rate:
enum: [0, 1]
power-source:
enum: [1, 2, 3, 4]
oneOf:
- required: [ groups ]
- required: [ pins ]
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-zynq.h>
pinctrl0: pinctrl@700 {
compatible = "xlnx,zynq-pinctrl";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};
uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
...
MAINTAINERS
View file @ c7930112
...@@ -14727,6 +14727,12 @@ F: Documentation/driver-api/pin-control.rst ...@@ -14727,6 +14727,12 @@ F: Documentation/driver-api/pin-control.rst
F: drivers/pinctrl/ F: drivers/pinctrl/
F: include/linux/pinctrl/ F: include/linux/pinctrl/
PIN CONTROLLER - AMD
M: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
S: Maintained
F: drivers/pinctrl/pinctrl-amd.c
PIN CONTROLLER - FREESCALE PIN CONTROLLER - FREESCALE
M: Dong Aisheng <aisheng.dong@nxp.com> M: Dong Aisheng <aisheng.dong@nxp.com>
M: Fabio Estevam <festevam@gmail.com> M: Fabio Estevam <festevam@gmail.com>
...@@ -14745,12 +14751,19 @@ S: Maintained ...@@ -14745,12 +14751,19 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
F: drivers/pinctrl/intel/ F: drivers/pinctrl/intel/
PIN CONTROLLER - KEEMBAY
M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
S: Supported
F: drivers/pinctrl/pinctrl-keembay*
PIN CONTROLLER - MEDIATEK PIN CONTROLLER - MEDIATEK
M: Sean Wang <sean.wang@kernel.org> M: Sean Wang <sean.wang@kernel.org>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt F: Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
F: drivers/pinctrl/mediatek/ F: drivers/pinctrl/mediatek/
PIN CONTROLLER - MICROCHIP AT91 PIN CONTROLLER - MICROCHIP AT91
......
arch/arm/boot/dts/mt8135.dtsi
View file @ c7930112
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt8135-resets.h> #include <dt-bindings/reset/mt8135-resets.h>
#include "mt8135-pinfunc.h" #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
/ { / {
#address-cells = <2>; #address-cells = <2>;
......
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file @ c7930112
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#include <dt-bindings/reset-controller/mt8183-resets.h> #include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
#include "mt8183-pinfunc.h" #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
/ { / {
compatible = "mediatek,mt8183"; compatible = "mediatek,mt8183";
......
drivers/pinctrl/Kconfig
View file @ c7930112
...@@ -248,12 +248,15 @@ config PINCTRL_SX150X ...@@ -248,12 +248,15 @@ config PINCTRL_SX150X
- 16 bits: sx1509q, sx1506q - 16 bits: sx1509q, sx1506q
config PINCTRL_PISTACHIO config PINCTRL_PISTACHIO
def_bool y if MACH_PISTACHIO bool "IMG Pistachio SoC pinctrl driver"
depends on OF && (MIPS || COMPILE_TEST)
depends on GPIOLIB depends on GPIOLIB
select PINMUX select PINMUX
select GENERIC_PINCONF select GENERIC_PINCONF
select GPIOLIB_IRQCHIP select GPIOLIB_IRQCHIP
select OF_GPIO select OF_GPIO
help
This support pinctrl and gpio driver for IMG Pistachio SoC.
config PINCTRL_ST config PINCTRL_ST
bool bool
...@@ -404,6 +407,25 @@ config PINCTRL_K210 ...@@ -404,6 +407,25 @@ config PINCTRL_K210
Add support for the Canaan Kendryte K210 RISC-V SOC Field Add support for the Canaan Kendryte K210 RISC-V SOC Field
Programmable IO Array (FPIOA) controller. Programmable IO Array (FPIOA) controller.
config PINCTRL_KEEMBAY
tristate "Pinctrl driver for Intel Keem Bay SoC"
depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
depends on HAS_IOMEM
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
select GPIOLIB_IRQCHIP
select GPIO_GENERIC
help
This selects pin control driver for the Intel Keembay SoC.
It provides pin config functions such as pullup, pulldown,
interrupt, drive strength, sec lock, schmitt trigger, slew
rate control and direction control. This module will be
called as pinctrl-keembay.
source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/actions/Kconfig"
source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/bcm/Kconfig"
......
drivers/pinctrl/Makefile
View file @ c7930112
...@@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o ...@@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o
obj-y += actions/ obj-y += actions/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
......
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View file @ c7930112
...@@ -133,8 +133,8 @@ static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx, ...@@ -133,8 +133,8 @@ static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
} }
/** /**
* Search for the signal expression needed to enable the pin's signal for the * aspeed_find_expr_by_name - Search for the signal expression needed to
* requested function. * enable the pin's signal for the requested function.
* *
* @exprs: List of signal expressions (haystack) * @exprs: List of signal expressions (haystack)
* @name: The name of the requested function (needle) * @name: The name of the requested function (needle)
......
drivers/pinctrl/aspeed/pinmux-aspeed.c
View file @ c7930112
...@@ -59,7 +59,8 @@ int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, ...@@ -59,7 +59,8 @@ int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
} }
/** /**
* Query the enabled or disabled state for a mux function's signal on a pin * aspeed_sig_expr_eval - Query the enabled or disabled state for a
* mux function's signal on a pin
* *
* @ctx: The driver context for the pinctrl IP * @ctx: The driver context for the pinctrl IP
* @expr: An expression controlling the signal for a mux function on a pin * @expr: An expression controlling the signal for a mux function on a pin
......
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View file @ c7930112
...@@ -416,8 +416,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) ...@@ -416,8 +416,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
} }
} }
/* This should not happen, every IRQ has a bank */ /* This should not happen, every IRQ has a bank */
if (i == BCM2835_NUM_IRQS) BUG_ON(i == BCM2835_NUM_IRQS);
BUG();
chained_irq_enter(host_chip, desc); chained_irq_enter(host_chip, desc);
......
drivers/pinctrl/freescale/Kconfig
View file @ c7930112
...@@ -166,6 +166,13 @@ config PINCTRL_IMX8DXL ...@@ -166,6 +166,13 @@ config PINCTRL_IMX8DXL
help help
Say Y here to enable the imx8dxl pinctrl driver Say Y here to enable the imx8dxl pinctrl driver
config PINCTRL_IMX8ULP
tristate "IMX8ULP pinctrl driver"
depends on ARCH_MXC
select PINCTRL_IMX
help
Say Y here to enable the imx8ulp pinctrl driver
config PINCTRL_VF610 config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver" bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610 depends on SOC_VF610
......
drivers/pinctrl/freescale/Makefile
View file @ c7930112
...@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o ...@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
......
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
View file @ c7930112
...@@ -155,7 +155,7 @@ static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = { ...@@ -155,7 +155,7 @@ static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = {
}; };
static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { static const struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
.pins = imx8dxl_pinctrl_pads, .pins = imx8dxl_pinctrl_pads,
.npins = ARRAY_SIZE(imx8dxl_pinctrl_pads), .npins = ARRAY_SIZE(imx8dxl_pinctrl_pads),
.flags = IMX_USE_SCU, .flags = IMX_USE_SCU,
......
drivers/pinctrl/freescale/pinctrl-imx8mn.c
View file @ c7930112
...@@ -317,7 +317,7 @@ static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = { ...@@ -317,7 +317,7 @@ static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD), IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD),
}; };
static struct imx_pinctrl_soc_info imx8mn_pinctrl_info = { static const struct imx_pinctrl_soc_info imx8mn_pinctrl_info = {
.pins = imx8mn_pinctrl_pads, .pins = imx8mn_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mn_pinctrl_pads), .npins = ARRAY_SIZE(imx8mn_pinctrl_pads),
.gpr_compatible = "fsl,imx8mn-iomuxc-gpr", .gpr_compatible = "fsl,imx8mn-iomuxc-gpr",
......
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
View file @ c7930112
...@@ -194,7 +194,7 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { ...@@ -194,7 +194,7 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B), IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
}; };
static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = { static const struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads, .pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads), .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU, .flags = IMX_USE_SCU,
......
drivers/pinctrl/freescale/pinctrl-imx8ulp.c 0 → 100644
View file @ c7930112
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx8ulp_pads {
IMX8ULP_PAD_PTD0 = 0,
IMX8ULP_PAD_PTD1,
IMX8ULP_PAD_PTD2,
IMX8ULP_PAD_PTD3,
IMX8ULP_PAD_PTD4,
IMX8ULP_PAD_PTD5,
IMX8ULP_PAD_PTD6,
IMX8ULP_PAD_PTD7,
IMX8ULP_PAD_PTD8,
IMX8ULP_PAD_PTD9,
IMX8ULP_PAD_PTD10,
IMX8ULP_PAD_PTD11,
IMX8ULP_PAD_PTD12,
IMX8ULP_PAD_PTD13,
IMX8ULP_PAD_PTD14,
IMX8ULP_PAD_PTD15,
IMX8ULP_PAD_PTD16,
IMX8ULP_PAD_PTD17,
IMX8ULP_PAD_PTD18,
IMX8ULP_PAD_PTD19,
IMX8ULP_PAD_PTD20,
IMX8ULP_PAD_PTD21,
IMX8ULP_PAD_PTD22,
IMX8ULP_PAD_PTD23,
IMX8ULP_PAD_RESERVE0,
IMX8ULP_PAD_RESERVE1,
IMX8ULP_PAD_RESERVE2,
IMX8ULP_PAD_RESERVE3,
IMX8ULP_PAD_RESERVE4,
IMX8ULP_PAD_RESERVE5,
IMX8ULP_PAD_RESERVE6,
IMX8ULP_PAD_RESERVE7,
IMX8ULP_PAD_PTE0,
IMX8ULP_PAD_PTE1,
IMX8ULP_PAD_PTE2,
IMX8ULP_PAD_PTE3,
IMX8ULP_PAD_PTE4,
IMX8ULP_PAD_PTE5,
IMX8ULP_PAD_PTE6,
IMX8ULP_PAD_PTE7,
IMX8ULP_PAD_PTE8,
IMX8ULP_PAD_PTE9,
IMX8ULP_PAD_PTE10,
IMX8ULP_PAD_PTE11,
IMX8ULP_PAD_PTE12,
IMX8ULP_PAD_PTE13,
IMX8ULP_PAD_PTE14,
IMX8ULP_PAD_PTE15,
IMX8ULP_PAD_PTE16,
IMX8ULP_PAD_PTE17,
IMX8ULP_PAD_PTE18,
IMX8ULP_PAD_PTE19,
IMX8ULP_PAD_PTE20,
IMX8ULP_PAD_PTE21,
IMX8ULP_PAD_PTE22,
IMX8ULP_PAD_PTE23,
IMX8ULP_PAD_RESERVE8,
IMX8ULP_PAD_RESERVE9,
IMX8ULP_PAD_RESERVE10,
IMX8ULP_PAD_RESERVE11,
IMX8ULP_PAD_RESERVE12,
IMX8ULP_PAD_RESERVE13,
IMX8ULP_PAD_RESERVE14,
IMX8ULP_PAD_RESERVE15,
IMX8ULP_PAD_PTF0,
IMX8ULP_PAD_PTF1,
IMX8ULP_PAD_PTF2,
IMX8ULP_PAD_PTF3,
IMX8ULP_PAD_PTF4,
IMX8ULP_PAD_PTF5,
IMX8ULP_PAD_PTF6,
IMX8ULP_PAD_PTF7,
IMX8ULP_PAD_PTF8,
IMX8ULP_PAD_PTF9,
IMX8ULP_PAD_PTF10,
IMX8ULP_PAD_PTF11,
IMX8ULP_PAD_PTF12,
IMX8ULP_PAD_PTF13,
IMX8ULP_PAD_PTF14,
IMX8ULP_PAD_PTF15,
IMX8ULP_PAD_PTF16,
IMX8ULP_PAD_PTF17,
IMX8ULP_PAD_PTF18,
IMX8ULP_PAD_PTF19,
IMX8ULP_PAD_PTF20,
IMX8ULP_PAD_PTF21,
IMX8ULP_PAD_PTF22,
IMX8ULP_PAD_PTF23,
IMX8ULP_PAD_PTF24,
IMX8ULP_PAD_PTF25,
IMX8ULP_PAD_PTF26,
IMX8ULP_PAD_PTF27,
IMX8ULP_PAD_PTF28,
IMX8ULP_PAD_PTF29,
IMX8ULP_PAD_PTF30,
IMX8ULP_PAD_PTF31,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
};
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
else
reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
.pins = imx8ulp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
.gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
};
static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8ulp-iomuxc1", },
{ /* sentinel */ }
};
static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info);
}
static struct platform_driver imx8ulp_pinctrl_driver = {
.driver = {
.name = "imx8ulp-pinctrl",
.of_match_table = imx8ulp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8ulp_pinctrl_probe,
};
static int __init imx8ulp_pinctrl_init(void)
{
return platform_driver_register(&imx8ulp_pinctrl_driver);
}
arch_initcall(imx8ulp_pinctrl_init);
MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver");
MODULE_LICENSE("GPL v2");
drivers/pinctrl/mediatek/pinctrl-mt8365.c
View file @ c7930112
...@@ -485,7 +485,6 @@ static struct platform_driver mtk_pinctrl_driver = { ...@@ -485,7 +485,6 @@ static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pinctrl_probe, .probe = mtk_pinctrl_probe,
.driver = { .driver = {
.name = "mediatek-mt8365-pinctrl", .name = "mediatek-mt8365-pinctrl",
.owner = THIS_MODULE,
.of_match_table = mt8365_pctrl_match, .of_match_table = mt8365_pctrl_match,
.pm = &mtk_eint_pm_ops, .pm = &mtk_eint_pm_ops,
}, },
......
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View file @ c7930112
...@@ -167,10 +167,14 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { ...@@ -167,10 +167,14 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"), PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), "pwm", "led"),
PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), "pwm", "led"),
PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
"pwm", "led"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
...@@ -184,10 +188,6 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { ...@@ -184,10 +188,6 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
18, 2, "gpio", "uart"), 18, 2, "gpio", "uart"),
PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
}; };
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
......
drivers/pinctrl/pinctrl-ingenic.c
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/pinctrl-keembay.c 0 → 100644
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/pinctrl-single.c
View file @ c7930112
...@@ -1115,7 +1115,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, ...@@ -1115,7 +1115,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
{ {
const char *name = "pinctrl-single,bits"; const char *name = "pinctrl-single,bits";
struct pcs_func_vals *vals; struct pcs_func_vals *vals;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
int npins_in_row; int npins_in_row;
struct pcs_function *function = NULL; struct pcs_function *function = NULL;
...@@ -1125,6 +1125,11 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, ...@@ -1125,6 +1125,11 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
return -EINVAL; return -EINVAL;
} }
if (PCS_HAS_PINCONF) {
dev_err(pcs->dev, "pinconf not supported\n");
return -ENOTSUPP;
}
npins_in_row = pcs->width / pcs->bits_per_pin; npins_in_row = pcs->width / pcs->bits_per_pin;
vals = devm_kzalloc(pcs->dev, vals = devm_kzalloc(pcs->dev,
...@@ -1212,29 +1217,19 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, ...@@ -1212,29 +1217,19 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
goto free_pins; goto free_pins;
} }
gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (gsel < 0) { if (res < 0)
res = gsel;
goto free_function; goto free_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP; (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name; (*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name; (*map)->data.mux.function = np->name;
if (PCS_HAS_PINCONF) {
dev_err(pcs->dev, "pinconf not supported\n");
goto free_pingroups;
}
*num_maps = 1; *num_maps = 1;
mutex_unlock(&pcs->mutex); mutex_unlock(&pcs->mutex);
return 0; return 0;
free_pingroups:
pinctrl_generic_remove_group(pcs->pctl, gsel);
*num_maps = 1;
free_function: free_function:
pinmux_generic_remove_function(pcs->pctl, fsel); pinmux_generic_remove_function(pcs->pctl, fsel);
free_pins: free_pins:
......
drivers/pinctrl/pinctrl-stmfx.c
View file @ c7930112
...@@ -566,7 +566,7 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) ...@@ -566,7 +566,7 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
u8 pending[NR_GPIO_REGS]; u8 pending[NR_GPIO_REGS];
u8 src[NR_GPIO_REGS] = {0, 0, 0}; u8 src[NR_GPIO_REGS] = {0, 0, 0};
unsigned long n, status; unsigned long n, status;
int ret; int i, ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
&pending, NR_GPIO_REGS); &pending, NR_GPIO_REGS);
...@@ -576,7 +576,9 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) ...@@ -576,7 +576,9 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
src, NR_GPIO_REGS); src, NR_GPIO_REGS);
status = *(unsigned long *)pending; BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
status |= (unsigned long)pending[i] << (i * 8);
for_each_set_bit(n, &status, gc->ngpio) { for_each_set_bit(n, &status, gc->ngpio) {
handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
stmfx_pinctrl_irq_toggle_trigger(pctl, n); stmfx_pinctrl_irq_toggle_trigger(pctl, n);
......
drivers/pinctrl/pinctrl-zynq.c
View file @ c7930112
...@@ -1028,6 +1028,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, ...@@ -1028,6 +1028,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
break; break;
} }
case PIN_CONFIG_IOSTANDARD: case PIN_CONFIG_IOSTANDARD:
case PIN_CONFIG_POWER_SOURCE:
arg = zynq_pinconf_iostd_get(reg); arg = zynq_pinconf_iostd_get(reg);
break; break;
default: default:
...@@ -1078,6 +1079,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, ...@@ -1078,6 +1079,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
break; break;
case PIN_CONFIG_IOSTANDARD: case PIN_CONFIG_IOSTANDARD:
case PIN_CONFIG_POWER_SOURCE:
if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) { if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
dev_warn(pctldev->dev, dev_warn(pctldev->dev,
"unsupported IO standard '%u'\n", "unsupported IO standard '%u'\n",
......
drivers/pinctrl/pinctrl-zynqmp.c
View file @ c7930112
...@@ -866,15 +866,6 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev) ...@@ -866,15 +866,6 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev)
return ret; return ret;
} }
static int zynqmp_pinctrl_remove(struct platform_device *pdev)
{
struct zynqmp_pinctrl *pctrl = platform_get_drvdata(pdev);
pinctrl_unregister(pctrl->pctrl);
return 0;
}
static const struct of_device_id zynqmp_pinctrl_of_match[] = { static const struct of_device_id zynqmp_pinctrl_of_match[] = {
{ .compatible = "xlnx,zynqmp-pinctrl" }, { .compatible = "xlnx,zynqmp-pinctrl" },
{ } { }
...@@ -887,7 +878,6 @@ static struct platform_driver zynqmp_pinctrl_driver = { ...@@ -887,7 +878,6 @@ static struct platform_driver zynqmp_pinctrl_driver = {
.of_match_table = zynqmp_pinctrl_of_match, .of_match_table = zynqmp_pinctrl_of_match,
}, },
.probe = zynqmp_pinctrl_probe, .probe = zynqmp_pinctrl_probe,
.remove = zynqmp_pinctrl_remove,
}; };
module_platform_driver(zynqmp_pinctrl_driver); module_platform_driver(zynqmp_pinctrl_driver);
......
drivers/pinctrl/qcom/Kconfig
View file @ c7930112
...@@ -88,6 +88,14 @@ config PINCTRL_MSM8960 ...@@ -88,6 +88,14 @@ config PINCTRL_MSM8960
This is the pinctrl, pinmux, pinconf and gpiolib driver for the This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8960 platform. Qualcomm TLMM block found in the Qualcomm 8960 platform.
config PINCTRL_MDM9607
tristate "Qualcomm 9607 pin controller driver"
depends on GPIOLIB && OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9607 platform.
config PINCTRL_MDM9615 config PINCTRL_MDM9615
tristate "Qualcomm 9615 pin controller driver" tristate "Qualcomm 9615 pin controller driver"
depends on OF depends on OF
...@@ -256,6 +264,15 @@ config PINCTRL_SDX55 ...@@ -256,6 +264,15 @@ config PINCTRL_SDX55
Qualcomm Technologies Inc TLMM block found on the Qualcomm Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX55 platform. Technologies Inc SDX55 platform.
config PINCTRL_SM6115
tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"
depends on GPIOLIB && OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6115 and SM4250 platforms.
config PINCTRL_SM6125 config PINCTRL_SM6125
tristate "Qualcomm Technologies Inc SM6125 pin controller driver" tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
depends on OF depends on OF
......
drivers/pinctrl/qcom/Makefile
View file @ c7930112
...@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o ...@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
...@@ -30,6 +31,7 @@ obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o ...@@ -30,6 +31,7 @@ obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
......
drivers/pinctrl/qcom/pinctrl-mdm9607.c 0 → 100644
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/qcom/pinctrl-sm6115.c 0 → 100644
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View file @ c7930112
...@@ -1104,39 +1104,42 @@ static int pmic_gpio_remove(struct platform_device *pdev) ...@@ -1104,39 +1104,42 @@ static int pmic_gpio_remove(struct platform_device *pdev)
} }
static const struct of_device_id pmic_gpio_of_match[] = { static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
/* pm8950 has 8 GPIOs with holes on 3 */
{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
/* pm8150b has 12 GPIOs with holes on 3, r and 7 */ /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
/* pm8150l has 12 GPIOs with holes on 7 */ /* pm8150l has 12 GPIOs with holes on 7 */
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
/* pm8950 has 8 GPIOs with holes on 3 */
{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
{ }, { },
......
drivers/pinctrl/renesas/Kconfig
View file @ c7930112
...@@ -37,6 +37,7 @@ config PINCTRL_RENESAS ...@@ -37,6 +37,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_RZG2L if ARCH_R9A07G044
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
...@@ -176,6 +177,16 @@ config PINCTRL_RZA2 ...@@ -176,6 +177,16 @@ config PINCTRL_RZA2
help help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZG2L
bool "pin control support for RZ/G2L" if COMPILE_TEST
depends on OF
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
config PINCTRL_PFC_R8A77470 config PINCTRL_PFC_R8A77470
bool "pin control support for RZ/G1C" if COMPILE_TEST bool "pin control support for RZ/G1C" if COMPILE_TEST
select PINCTRL_SH_PFC select PINCTRL_SH_PFC
......
drivers/pinctrl/renesas/Makefile
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/renesas/core.c
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/renesas/pfc-r8a77995.c
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/renesas/pinctrl-rzg2l.c 0 → 100644
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/renesas/pinctrl.c
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/renesas/sh_pfc.h
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/samsung/pinctrl-exynos.h
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/samsung/pinctrl-samsung.c
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/samsung/pinctrl-samsung.h
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/stm32/Kconfig
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/stm32/Makefile
View file @ c7930112
This diff is collapsed.
drivers/pinctrl/stm32/pinctrl-stm32mp135.c 0 → 100644
View file @ c7930112
This diff is collapsed.
include/dt-bindings/pinctrl/pinctrl-zynq.h 0 → 100644
View file @ c7930112
This diff is collapsed.
include/dt-bindings/pinctrl/rzg2l-pinctrl.h 0 → 100644
View file @ c7930112
This diff is collapsed.
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