Commit c79a3ccb authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding

dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties

The cpu_lp clock property is only needed when the CPUfreq driver
supports CPU cluster switching. But it was not a design for this driver
and it didn't handle that as well. So removing this property.

Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: default avatarJon Hunter <jonathanh@nvidia.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 73688f7d
...@@ -9,7 +9,6 @@ Required properties: ...@@ -9,7 +9,6 @@ Required properties:
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries: - clock-names: Must include the following entries:
- cpu_g: Clock mux for the fast CPU cluster. - cpu_g: Clock mux for the fast CPU cluster.
- cpu_lp: Clock mux for the low-power CPU cluster.
- pll_x: Fast PLL clocksource. - pll_x: Fast PLL clocksource.
- pll_p: Auxiliary PLL used during fast PLL rate changes. - pll_p: Auxiliary PLL used during fast PLL rate changes.
- dfll: Fast DFLL clocksource that also automatically scales CPU voltage. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
...@@ -30,11 +29,10 @@ cpus { ...@@ -30,11 +29,10 @@ cpus {
reg = <0>; reg = <0>;
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
<&tegra_car TEGRA124_CLK_CCLK_LP>,
<&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_X>,
<&tegra_car TEGRA124_CLK_PLL_P>, <&tegra_car TEGRA124_CLK_PLL_P>,
<&dfll>; <&dfll>;
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
clock-latency = <300000>; clock-latency = <300000>;
}; };
......
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